JP3340592B2 - Circuit diagram creation device and circuit diagram translation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit diagram creating apparatus for creating a program which operates on a programmable controller (hereinafter abbreviated as PC), and an apparatus for converting this circuit diagram into a language for PC. About.

[0002]

2. Description of the Related Art Conventionally, FA (Factory Automation)
Or CIM (Cmoputer Integrated Manufacturin)
g) In the production line of the factory where the conversion has been performed, for example, physical information indicating that the number of products passing through the exit of the belt conveyor has reached a predetermined quantity, or a dangerous area when the cutting machine is operating. There are various information to be controlled, such as logical information indicating that a moving object has been detected. A programmable controller (hereinafter, referred to as a PC) is widely used as a device for performing a predetermined output control (sequence control) in an automated production line in accordance with the various detected information.

[0003] This method of programming a PC involves a completely different description format from ordinary computer programming. Generally, for example, a contact (normally open switch) A,
B, D, b contacts (normally closed switch) E, coils C, F
A development diagram (ladder diagram) of a relay circuit using a symbol mark such as is used. Alternatively, for example, a condition table shown in FIG. 33 may be used.

FIGS. 32 and 33 show the same program contents except for the description format. That is, in both figures, the relay circuit a-1 of FIG.
Correspond to each other, and represent an output C conditioned on input A and input B.
Similarly, a relay circuit a-2 and a condition table column b-2 correspond to each other, and represent an output F conditioned on an input D and an input E.

FIG. 34 shows a relay circuit a-
35 shows the operation of the program corresponding to the contents of the column 1 of the condition table 1 or the truth table in the truth table.
Shows the operation of the program corresponding to the contents of the relay circuit a-2 or the column b-2 of the condition table in a truth table.

[0006] These descriptions are generally converted into a program of a predetermined format by a programming device (program loader) and stored in a PC. This program is generally not a machine language that can be executed as it is inside the PC.
C is described in an intermediate language that is easy to analyze.

The basic structure of this intermediate language is, for example,
It has a functional (action) language structure having the form of “(F op1 op2... Opn)”. In the above basic structure, "(" indicates the start of an instruction, "F" indicates the name of the instruction, and ")" indicates the end of the instruction. Also, "op1",
“Op2”,..., “Opn”, etc. are operands of an instruction, and these operands can further become an instruction to take a hierarchical structure as a whole. This functional language has a one-to-one correspondence with a machine language that operates directly on a PC, and can be easily converted to a machine language.

[0008] In general, on-site aspects such as the progress of the process and the work procedure are fluid. For this reason, the procedure (program) of the sequence control on the site is not originally determined in its specifications from the beginning, and changes and corrections are constantly repeated according to the actual conditions of the site during the test operation or actual operation of the PC. It is determined by things. Therefore, in order to easily cope with these changes, it is desirable that the above-mentioned ladder diagram and condition table can easily describe any complicated control contents corresponding to the changes.

However, since the ladder diagram simulates the logic by the flow of electric current, when converting the logic into a circuit, electrical expertise is required to some extent. For example, by converting the flow of the logic into the flow of the current in the logic circuit of FIG. 36, a ladder diagram of FIG. 37 can be created. However, this conversion requires a high degree of skill and is easy for a beginner to use. There was a problem that it was not possible.

Further, it takes considerable skill to recognize that the ladder diagram of FIG. 37 is equivalent to the logic circuit of FIG. 36, which is also difficult for a beginner to recognize. There was a problem.

[0011] Further, the method using the condition table also has the following problem. That is, for example, in the case of a simple logic circuit as shown in FIG. 38, it can be converted to the condition table shown in FIG. 39. However, as in the above-described logic circuit of FIG. In the case of a complicated logic circuit (deep logic) used for an operation, it cannot be converted into a condition table. Further, a logic circuit including a circuit 41 having a delay operation as shown in FIG. 40 cannot be represented by a condition table. As described above, the condition table cannot describe all necessary logic circuits, and there is a problem that the use of the condition table is limited.

For this reason, the present applicant can create any logic circuit including a delay operation (timer) without requiring specialized knowledge, and can describe any logic circuit including a delay operation (timer). Invention relating to a programming method (table-form circuit description) that can be performed, and a language conversion device (functional-type language conversion device) for converting the table-form circuit description into a program for PC (functional language) (Japanese Patent Laid-Open No. 6-149311). Was previously filed.

[0013]

By the way, the monitoring of the starting condition and the operating condition of the automatic operation and the like in the circuit for performing the sequence operation is performed by using the external input contact information of the PC individually assigned according to the condition or the PC. Is transmitted to the monitoring device as the monitoring information.

In order to transmit these pieces of monitoring information to a monitoring device and to use a monitoring program operating on this monitoring device in common, one word in a memory, which is an access unit, stores each of the above conditions. It is convenient to collect the following external input contact information and the contents of the internal memory.

However, when the starting conditions and operating conditions of the automatic operation and the like assigned to the bit memory are rearranged in the word memory, the ladder diagram and the FB diagram are expressed as shown in FIGS. 41 and 42, respectively. And the circuit becomes very long, so that the labor for creating the circuit diagram increases.

In the case of the above-described circuit description in the form of a table, the entire table becomes large and long as shown in FIG.
Poor readability. In each of the above figures, I.I. 001
A, I. 0005, I. 003B, I.C. 0003 is external input contact information. 0000, M0001, M.P.
0002, M. 000F represents the 0th, 1, 2, and Fth bits of the word memory (WM000), which is an internal memory that can be accessed in one word.

On the other hand, in the case of a ladder diagram, when starting conditions and operating conditions are created using the word memory created as described above, it is necessary to create a circuit as shown in FIG.

However, in this case, the word memory (WS0)
103 (in the example of FIG. 44, WS0103.0, WS0103.1, WS010).
3.2) and this condition (M.0 in the example of FIG. 44).
002), the connection (logical product circuit) of each bit of the word memory (WS0103) which determines this condition is difficult to understand, and the readability is poor.

The condition monitoring word memory created as shown in FIG. 44 has no means for visually recognizing the actual operating state of the circuit.
When a failure or the like occurs, it is difficult to immediately determine the cause.

For example, in the above-mentioned Japanese Patent Laid-Open Publication No. Hei 6-149311, in order to easily create a program that prepares all the operating conditions and the like of the devices, the configuration is such that the inputs constituting one output condition are vertically aligned. When an output condition is not satisfied, an input condition that cannot satisfy the output condition can be easily found by monitoring an input condition arranged below the output condition. However, in actual control, if the input condition is not satisfied due to some factor (primary factor: primary failure factor) and the output condition is not satisfied, the input condition is further satisfied by the secondary factor of the output. There are many things that don't work. At that time, the monitor described in Japanese Patent Application Laid-Open No. 6-149311 cannot find a true factor for which the output condition is not satisfied because neither the primary factor nor the secondary factor is satisfied.

The present invention has been made in view of the above-mentioned problems. The present invention relates to external input contact information to be monitored when monitoring start-up conditions such as automatic operation and operating conditions, and monitoring information such as an internal memory in one word. It is a first object of the present invention to enable a circuit description to be collected in a memory to be described in a tabular format with good readability by a small-scale circuit.

A second aspect of the present invention is to enable a circuit for creating start-up conditions and operating conditions to be described in a tabular form excellent in readability using the word memory used for collecting monitoring information as described above. The purpose of.

Further, a condition monitoring word memory provided for monitoring the above-mentioned starting conditions and operating conditions is provided with means for making it easy to visually recognize the actual operating state of the circuit. A third object is to provide a circuit description in a tabular form that allows quick grasp.

A fourth object of the present invention is to provide a method of converting the above-described circuit description in a table format into a language for a PC.

[0025]

The means of the present invention will be described with reference to FIG. A circuit diagram creating apparatus according to the present invention creates a circuit diagram describing a program operating on a programmable controller.

The circuit diagram creation apparatus of the present invention describes various information in a circuit diagram creation area having the following format. That is,
The circuit diagram creation area includes a plurality of output description lines 10 for describing an output and a plurality of input description lines 20 for describing an input corresponding to the output. Each of the output description lines 10-1, 10-2,... Has an output name section 11 for describing a name of an output signal and an output condition section 12 for describing an output condition. On the other hand, each input description line 20-1, 20
., Have an input name part 21 for describing the name of the input signal and an input condition part 22 for describing the input condition. Further, a plurality of input description lines 20-1, 20-2,.
.. Has a logic unit 23 for describing a logic circuit.

The description means in the circuit diagram creation device is a logic unit 2
In 3, an input symbol meaning the input of a signal having the name described in the input name section 11 and a logical operation symbol meaning a logical operation on the input signal are described.

In the output condition section 12, the output condition section 12 converts the input signal whose name is described in the input name section 21 or the logical operation result of the logic section 23 into the output description line (here, “A”). Is written in the output memory 31 corresponding to the row 10-3) in which is written (in this case, represented by "A"). The output memory 31 is, for example, a word memory.

Further, the description means includes an input condition unit 22
, The input signal whose name is described in the input name section 21 or the logical operation result of the logic section 23
Describes a bit position designation symbol for designating a bit position in the output memory 31 when writing to the. The output memory 31 is provided corresponding to an output description line in which the memory allocation symbol is described.

The storage means in the circuit diagram creation device stores each symbol described by the description means in association with the circuit diagram description area in the above format. In addition to the above-described functions, the above description means allows the output condition unit 12 to execute the processing based on the contents of the monitoring memory 32 corresponding to the output description line (here, the line 10-1 in which “F” is entered). A highlighting symbol (in this case, represented by “F”) for designating the corresponding one of the bit position designating symbols is described.

The circuit diagram translation device of the present invention translates a circuit diagram created by the above-described circuit diagram creation device into a language for a programmable controller and has the following means.
The input / output condition extraction / storage means extracts output conditions from the output condition unit 12 and extracts and stores input conditions from the input condition unit 22.

The output line information extraction / storage means extracts an output name from the output name section 11 and stores it as output line information. The input logic extraction / storage means converts the logic circuit described in the logic unit 23 into a corresponding statement in a predetermined language and stores it.

The bit collection instruction creating means extracts an output description line in which the memory allocation symbol is described by referring to the input / output condition extracting / storing means, and creates a base address of the output memory 31 from the extracted information. I do. Also, the extraction information stored in the input / output condition extraction / storage means, the output line information extraction / storage means and the input logic extraction / storage means is read, and the extracted information and the base address of the output memory 31 are read out. A bit collection for writing an input signal corresponding to an input description line in which the memory bit position designation symbol is described or a logical operation result of the logic unit in a bit of the output memory 31 designated by the memory bit position designation symbol An instruction is created and stored in a predetermined area of the storage means.

The monitoring word generation command creating means refers to the input / output condition extracting / storing means and the output line information extracting / storing means to extract an output description line in which the highlighting symbol is described, and extract the output description line. Based on the contents of the monitoring memory 32 corresponding to the output description line, a monitoring word generation instruction for highlighting the corresponding symbol in the bit position designation symbol is created. Then, this is stored in a predetermined area of the storage means.

[0035]

In the circuit diagram creating apparatus of the present invention, a memory bit position designating symbol designating a bit position of the output memory 31 is described in the input condition section 22 of a predetermined input description line (here, 20-2) ( Here, it can be described in the shaded area). Bits in the output memory 31 designated by the memory bit position designation symbol include, for example, the logic unit 23
Are written to the row 20-2.

On the other hand, a predetermined output description line (here, 10
In the output condition section 12 of -3), a memory allocation symbol indicating that data is stored in the output memory 31 corresponding to the own row can be described.

Therefore, by using the memory bit position designation symbol and the memory allocation symbol together, it is determined whether or not data is stored in the output memory 31 and in which bit is stored if the data is stored. Can be recognized.

Further, if the output memory is constituted by a word memory, external input contact information and monitoring information such as an internal memory which need to be monitored for monitoring the starting condition and the exercise condition can be stored.
The circuit description for the above information can be collected in an arbitrary word, and the circuit description for the information can be described in a small-scale circuit with good readability. Can be well described.

Further, a predetermined output description line (here, 10
-1), the output description line (1
Based on the contents of the monitoring memory 32 corresponding to 0-1), it is possible to describe a highlighting symbol for highlighting a corresponding bit position designation symbol. For example, if the content of the monitoring memory 32 matches the bit position designation symbol described in the input condition part 22 of the input description line 20-2, writing to the output memory is performed according to the bit position designation symbol. The bit position designation symbol corresponding to the signal is highlighted.

Therefore, since the starting conditions and operating conditions relating to the processing currently being executed on the programmable controller can be highlighted, it is possible to easily recognize when any of those conditions is missing due to a failure or the like. .

The circuit diagram translating apparatus of the present invention decodes a circuit diagram created by the circuit diagram creating apparatus, extracts input / output conditions, logical operations, and the like, and designates bit position designation symbols, memory allocation symbols, highlight symbols. , A bit collection instruction and a monitoring word generation instruction for the programmable controller are generated.

That is, when monitoring start-up conditions, operation conditions, and the like of automatic operation and the like, monitor information such as external input contact information and internal memory (these names are:
(Described in the input name part 21) in a one-word memory, and starting conditions and movements using the external input contact information, the internal memory, etc. collected in the one-word memory. A circuit description for describing conditions and the like is converted into a language operable on a programmable controller. Also, the highlighting symbol described in the output condition part 12 of the output description line of the circuit diagram of the above format is used to create the output memory (word memory) according to the contents of the monitoring memory corresponding to the output description line. Are converted into program instructions operable on a programmable controller to highlight the bit position symbols used in the program.

The instructions generated by the above conversion are described in an intermediate language (functional language) corresponding to a machine language that can be directly understood by the programmable controller, for example, 1: 1.

[0044]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram for explaining a tabular circuit description method for creating a program operating on a PC according to one embodiment of the present invention.

This tabular description is equivalent to the logic circuit shown in FIG. That is, the tabular circuit description shown in FIG. 2 defines the logic circuit shown in FIG. The tabular circuit description includes a plurality of output description lines 100 for describing an output and a plurality of input description lines 200 for describing an input corresponding to the output.

The output description line 100 includes an output name part a for describing the name of the output signal, a timer setting value part c for describing the timer setting, an output condition part e for describing the output condition, and a comment part g for describing the comment. Consists of

The input description line 200 includes an input name section b for describing the name of an input signal, a logic section d for describing a logic circuit, an input condition section f for describing input conditions, and a comment section h for describing a comment. .

Next, the meanings of the symbols described in the logic part d, output condition part e, and input condition part f shown in FIG. 2 will be described with reference to FIG. <Symbol of logic part d> Arrow: An input symbol meaning input of an input signal.

Arrow with a black circle added at the center: An input inversion symbol meaning an inversion input of the input signal. One vertical line: a logical sum symbol indicating a logical sum of input signals.

Two parallel vertical lines: a logical product symbol indicating a logical product of input signals. <Symbol of output condition part e> W: Set symbol indicating that the result of the logical operation is substituted into the output signal.

S: A set symbol that turns on the output signal when the logical operation result is true, and means no processing when the logical operation result is false. R: The output signal is turned off when the logical operation result is true
And a reset symbol that means no processing when the logical operation result is false.

A means that a signal input to the position (input description line) of the input condition part f is substituted into a bit position in the output word memory specified by the input condition part f. Word memory allocation symbol.

F: highlighting the word memory bit position symbol (this symbol will be described later) of the input condition part f which is writing to the OFF bit on the output word memory. The highlight symbol that means. <Symbol of input condition part f> ・ ・ ・: Positive logic symbol meaning that the signal of the input name part b of the corresponding input description line 200 or the result of the logic part d is used.

X: A negative logic symbol meaning that the signal of the input name part b of the corresponding input description line 200 or the result of the logic part d is used after being inverted. “0” to “9” and “A” to “F”... Word memory bit position designation symbols that designate the bit positions of the output word memory to which the input signals of the corresponding input description line 200 are substituted.

FIG. 5 is a block diagram showing an overall configuration of a circuit diagram translating apparatus for converting the above-described table-form circuit description shown in FIG. 2 into a functional language. This functional language has a one-to-one correspondence with a machine language that operates directly on a PC, and is easily converted to this machine language by compiling.

The source storage device 401 stores the tabular circuit description shown in FIG. Input / output condition extraction device 411
Searches for the output condition part e shown in FIG. The line number of the output description line where the above “W”, “R” or “S” symbol exists, and the symbol written in the output description line where those symbols exist are extracted.

Then, the result of the extraction is stored in the input / output condition storage device 412. The "A" or "F" symbol (A output or F output) in the output condition part e is extracted for each column where the "W" symbol (W instruction) exists, and the "A" or "F" symbol exists. Information about the output description line is stored in the input / output condition storage device 412 for each column. The input condition part f is searched in units of columns to extract the “O” or “X” symbols, and stores these symbols in the input / output condition storage device 412. The input condition unit f is searched for each column to extract the bit position of the output word memory set by the word memory bit position symbol, and the extraction result is stored in the input / output condition storage device 412.

The output line extracting device 421 searches the output name part a and the timer set value part c for each line, and extracts the output name and the timer set value. Then, these are stored in the output line information storage device 422.

The input logic extraction device 431 searches the result of the logic part d for each input description line and performs the following processing. The last part of the logical part symbol in the searched input description line (result)
If exists, trace the logic from its end and translate this logic into a functional language. Then, the converted functional language is stored in the input logic storage device 432. If a logical part symbol does not exist in the searched input description line, the name of the corresponding line of the input name part b is extracted, and this name is stored in the input logical storage device 432.

The W, S, R instruction preparing device 413 searches the information of each column of the output condition part e and the input condition part f stored in the input / output condition storage device 412 in order from the first column. Each symbol of “W”, “S” or “R” is extracted as each instruction of “W”, “S” or “R” of the functional language, respectively, and these are extracted in a predetermined form of the functional language storage device 501. Store in area.

Based on the information stored in the output line information storage device 422, the timer instruction creation device 423 outputs, for all output description lines in which the timer value is set in the timer setting value portion c, the output name portion thereof. Extract the output name from a.
Then, a timer current value name is created based on the output name. Further, these are stored in a predetermined area in the functional language storage device 501.

The bit collection instruction creation device (A instruction creation device) 441 performs the following processes 1 to 3 based on the information stored in the input / output condition storage device 412. The output condition part e checks whether there is an output description line in which the "A" symbol exists, and if there is, determines the bit base address from the word address corresponding to the name described in the output description line of the output description line. And stores it in the bit base address storage device 442. In the input condition part f, all columns (corresponding columns) in which the "A" symbol exists are searched, and an input description in which word memory bit position symbols (hexadecimal values of "0" to "F") exist in these corresponding columns Extract the line number of the line. Then, the name (applicable name) of the line having this line number is extracted from the input logical storage device 432. 1 indicated by the word memory bit position symbol extracted in the above-mentioned process in the bit base address created in the above-mentioned process.
An instruction for writing the corresponding name extracted in the above process is created in a bit address obtained by adding a hexadecimal value, and this is stored in the bit collection instruction storage device 443.

The & instruction creation device 433 performs the following processes 1 to 3 based on the information stored in the input / output condition storage device 412. "W", "S" or "R" in the output condition part e
In the output description line where a symbol is present, when there are a plurality of “○”, “×”, or multiple word memory bit position symbols (hexadecimal value) in the input condition part f of the column where the symbol is present (the corresponding column), “ The && instruction is stored in a predetermined area of the functional language storage device 501, and this storage is stored.
If there is only one “「 ”,“ × ”or word memory bit position symbol (hexadecimal value) in the corresponding column,
No action is taken. The line numbers of the input description lines in which “○” or “×” exists in the corresponding column in the input condition part f are extracted, and the names described in the input name part b of the input description lines having these line numbers ( The corresponding name is read from the input logical storage device 432 and stored in a predetermined area of the functional language storage device 501.

In this processing, if the mark is "x", the processing differs depending on whether the corresponding name is an atom or a list. 1) For an atom Add "!" To the beginning of the atom.

2) In the case of a list Surround the list with "(NOT)" (however, if the function instruction of the list is "NOT", the "NOT" function is removed).

Also, in this embodiment, when the operand is the input signal name (the first line, the second line,
And the sixth line), this is called an atom, and when the operand is a function (see the third line in FIG. 10 described later), this is called a list. In the input condition part f, an input description line (corresponding line) in which the word memory bit position symbol (hexadecimal value) exists in the corresponding line is extracted, and a corresponding bit collection instruction (A instruction) is extracted based on this line number. The data is read from the bit collection command storage device 443 and stored in a predetermined area of the functional language storage device 501.

The timer setting value creation device 424 searches for an output description line in which the timer value is set in the timer setting value portion c based on the information stored in the output line information storage device 422, and Is stored in a predetermined area of the functional language device 501. At this time, if the & instruction has already been stored in the functional language storage device 501 by the & instruction creation device 433, “)” corresponding to the & instruction is also stored.

The output instruction creation device 425 reads out the output name of the output description line in which the timer setting value set in the functional language storage device 501 by the timer setting value creation device 424 is described from the output line information storage device 422. Are stored in a predetermined area of the functional language storage device 501.

The monitor word generation instruction creation device (F instruction creation device) 451 outputs an output description in which the “F” symbol is described in the output condition part e based on the information stored in the input / output condition storage device 412. A check is performed to determine whether or not there is a row. If such a row exists, a monitoring word generation instruction using the output name of this row as an operand is created, and this instruction is stored in a predetermined area of the functional language storage device 501. I do.

Next, the operation of the program conversion apparatus shown in FIG. 5 will be described with reference to a specific example of a circuit description in a table format. FIG. 6 is a diagram illustrating a specific example of the tabular circuit description of the present embodiment.

In the figure, an output description line 4 consisting of an output name part a, a timer set value part c and an output condition part e is provided at the top.
1, an input description line 42 including an input name part b, a logic part d, and an input condition part f is provided below.
The number of the output description lines 41 and the number of the input description lines 42 are not limited, and increase according to the logic depth.

In the input name section b, the input signal name "I.0
000 "," I.0001 "," I.0002 ",
“I.0003”, “I.0004” and “I.00”
05 "is described.

The input signal “I.000” is input to the logic part d.
0 "to" I.0005 "are described. The inputs of the input signals "I.0002" and "I.0003" are described by arrows 47-0 and 47-1 with black circles, respectively.
The AND circuit to which the signals represented by −0 and 47-1 are added is described by two vertical lines 47-2. An operation result of the AND circuit 47-2 is described by an arrow 47-3, and an OR circuit to which the operation result 47-3 is added is described by one vertical line 47-4.

The input of the input signal "I.0004" is described by an arrow 47-5, and the input 47-5 is described to be input to the OR circuit 47-4. And
The operation result of the OR circuit 47-4 is described by an arrow 47-6, and the arrow 47-6 is input to the input condition part f in the third line of the input description line. That is, when the operation described in the logic part d is performed on the input signals “I.0002” to “I.0004”, the operation result corresponds to the third line of the input description line. It is described as follows.

Columns 48-1, 48-2,... Are provided in common for output condition section f and input condition section f.
Each column corresponds to one operation of the PC. In the first column 48-1 of the input condition part f, a circle is described in the first row, and a cross is described in the second row. This mark indicates that the input signal of the corresponding row or the operation result of the logic unit d is used. Here, a logic circuit that inputs the operation result to the first row of the input condition part f is a logic part d.
, It means that the input signal of the corresponding row, that is, the input signal “I.0000” is used. On the other hand, the crosses indicate that the input signal of the corresponding row or the operation result of the logic unit d is inverted and used. Here, it means that an inverted signal of the input signal “I.0001” is used.

In the third row of the input condition section f, the output of the OR circuit 47-4 is associated with the operation result of the logic circuit described in the logic section d. “0” is described as a bit position symbol (hexadecimal value). In the sixth row of column 48-1, "1" is described as a word memory bit position symbol (hexadecimal value).

These hexadecimal numbers "0" and "1" are used for the name "WM000" described in the output name part a of the output description line where the symbol "A" is described in the output condition part e.
This indicates that the output and the input signal “I.0005” of the OR circuit 47-4 are written into the 0th and 1st bits of the word memory having “0”, respectively.

The output name "a."
SSTIM "," WM0000 "," SI0000 "and" M.RD-F "are described. The address "DIABCD" in which the timer setting value is stored is described in the timer setting value section c of the output description line corresponding to the output signal "T.SSTIM". In the column, a light symbol "W" is described. This means that at the time of processing relating to the output signal “T.SSTIM”, the timer value set at the address “DIABCD” is read, and the actual processing (here, the write processing) is executed when the timer value has elapsed. Things.

The symbol "W" means "write", and designates that the result of the logical operation set in the input description line 42 is substituted for the output signal "T.SSTIM".
Here, as one of the input conditions in the first column 48-1 of the input condition part f, one 印 mark (first row), one X mark (second row),
Since two word memory bit position symbols "0" (third row) and "1" (sixth row) are described, the logical operation result set in the first column 48-1 of the input description row 42 is ,
Input signal "I.0000", input signal "I.0001"
, The logical product of four signals of the operation result 47-6 of the OR circuit 47-4 and the input signal “I.0005”. Note that, similarly to the “W” symbol, even when the “S” symbol or the “R” symbol is described, the ○ mark, the × mark, and the word memory bit described in the column where the symbol is described. The logical product of the signals corresponding to the input description lines in which the position symbols exist is used as the logical operation result.

The output signal "WM00" is output to the output name part a.
00 "is set in the timer description value section c of the output description line
Has no description of the timer setting value, and the word memory allocation symbol "A" is described in the first column of the output condition part e.

The "A" symbol is assigned to each input description line in which a word memory bit position symbol (hexadecimal value) is described in the column (here, column 48-1) in which the "A" symbol is described. The input signal is indicated by the hexadecimal value in the output word memory to which the name described in the output name part a of the output description line (second line) in which the “A” symbol is described is assigned. Is assigned to the bit position to be set. That is, in the case shown in FIG. 6, the name "WM0
000 ”is assigned to the 0th output memory.
The logical operation result 47-6 of the OR circuit 47-4 is substituted for the bit “M.0000”, and the input signal “I.0005” is substituted for the first bit “M.0001” of the output word memory. Become.

Further, the output signal "SI.
In the output description line (third line) in which “0000” is described, there is no description of the timer set value in the timer set value portion c.
The highlighting symbol "F" is described in the first column (48-1) of the output condition part e.

The "F" symbol is determined according to the contents of the output word memory to which the name "SI.0000" described in the output name portion a of the output description line in which the symbol "F" is described is assigned. This specifies that a monitoring word generation instruction for highlighting a predetermined position in the column (48-1) in which the "F" symbol is described is created. This highlighting will be described later in detail.

The output signal "M.RD"
In the output description line (4th line) in which “-F” is described, the timer setting value is not described in the timer setting value portion c, and the light symbol “W” is described in the second column of the output condition portion e. ing.

The write symbol “W” indicates that the input signal “I.0005” described in the input name portion “b” is to be written into the output signal “M.RD-F”. The above-described tabular circuit description is a circuit program to be created by the user, that is, a source program.

The above-described circuit program shown in FIG. 6 is equivalent to the functional language shown in FIG. This functional language is an intermediate language that connects a source program and an object program, and can be easily converted to a machine language.

The instruction “W” in the first, fourth, seventh, and eleventh lines of the functional language shown in FIG. 11 has the same meaning as the output condition symbol “W” in FIG. The command “TON” on the first line is a timer command that instructs output to be performed after a predetermined time (second).

The instruction “&” on the second line is “I.0000” which is the first operand on the second line, “! I.0001” which is the second operand on the third line, and “I.0001” on the sixth line. This is an operation instruction for calculating a logical product of “M.0000” which is the three operand and “M.0001” which is the fourth operand on the seventh line. The instruction “&” on the fourth line is also the same as the first operand “I.0002” and the second operand “!” On the fourth line.
I. 0003 ”is an operation instruction for obtaining a logical product with“ 0003 ”.

Instruction "> = 1" on line 4 to line 5
Is the first operand on the fourth line, "(& I.000
2! I. 0003) "and the second operand" I.0004 "in the fifth row.

The symbol “!” Added immediately before the input signals “I.0001” and “I.0004” on the third and fourth lines indicates that those signals are inverted. .

FIG. 8 shows an input / output condition extracting device 411 which extracts the output condition portion e and the input condition portion f of the tabular circuit description shown in FIG.
FIG. 4 is a storage state diagram of input / output conditions stored in the storage device.

As shown in the figure, in the data structure storing the above input / output conditions, the first line (412-1)
Is an area for storing the symbol “W”, “S” or “R” described in the output condition part e of the above-described tabular circuit description,
Here, the symbol “W” (light symbol) is stored in both the first and second columns. 1 in line 2 (412-2)
The column numbers “1” and “4” of the output description line in which each symbol “W” is described are stored in the second and third columns, respectively.

The third and fourth lines (412-3 and 412)
-4) is an output condition part e of the above-described tabular circuit description.
In this case, when the word memory allocation symbol "A" and the highlighting symbol "F" are described, this is an area for storing the line number of the output description line in which those symbols are described. In the example shown in FIG. 6, a word memory allocation symbol "A" and a highlight symbol "F" are respectively provided on the second and third lines of the output description line.
, The row numbers “2” and “3” are stored here.

The contents of the input condition part f are stored in the fifth and subsequent lines. That is, the fifth to seventh lines (412-5 to 41)
The first column of 2-7) and the first and second columns of the tenth row (412-10) are described in the same row and column of the input condition part f of the tabular circuit description shown in FIG. Input condition symbol "○", "x" or word memory bit position symbol (1
Hexadecimal values “0”, “1”) are stored. And
Output condition part e and input condition part f of the above-described tabular circuit description
In the column corresponding to the matrix position where no input / output condition symbol is described, “absence” is stored.

FIG. 9 is a storage state diagram of the output line information extracted from the output description line by the output line extraction device 421 and stored in the output line information storage device 422. In the example of FIG. 6, the output signal name “T.SSTIM” and the timer setting value described in the output name part “a” and the timer setting value part “c” of the first output description line of the tabular circuit description shown in FIG. "DIA
BCD "is stored in the first row, and 2 in the above-described tabular circuit description.
The output signal name “WM0000” described in the output name part a of the output description line of the second line is stored in the second line. Further, the output signal name “SI0” described in the output name part “a” of the third and fourth output description lines in the tabular circuit description shown in FIG.
000 "and" M.RD-F "are stored in the subsequent third and fourth rows. In FIG. 6, "None" is set for a line in which the timer value is not described in the timer setting value part c.
Is stored.

FIG. 10 shows an input logic storage device 4 which is extracted from the above-described tabular circuit description by the input logic extraction device 431.
FIG. 3 is a diagram illustrating a storage state of an input signal stored in a logic operation circuit and a logical operation circuit (input logic) of a logic unit converted into a functional language;

The input signal name “I.000” for which the logical operation is not described in the logical part “d” of the tabular circuit description shown in FIG.
“0”, “I.0001”, and “I.0005” are stored as they are in the same row as the input name part b of the tabular circuit description. On the other hand, the input signal name in which the logical operation is described by the logical unit d is described in the same line as the line of the input condition unit f to which the result of the logical operation is input, with a functional language description equivalent to the logical operation described above as a parameter. Is stored as That is, the logical operation performed on the input signals “I.0002” to “I.0004” described in the functional language is stored in the third row.

Next, the processing operation of the embodiment having the above configuration will be described with reference to the flowcharts of FIGS. In this processing, under the control of a CPU (Central Processing Unit) (not shown) of the circuit diagram conversion device shown in FIG. 5, each device constituting the circuit diagram conversion device stores the data in the source storage device 401. Tabular circuit description is converted to a functional language. Prior to this conversion processing, the input / output condition storage device 412 and the output line information storage device 42
2. The data contents of the input logical storage device 432, the bit collection command storage device 443 and the bit base address storage device 442 are all cleared.

FIG. 11 is a general flowchart showing the overall flow of this conversion processing. Each process S111 to S120 in this flowchart will be described in detail with reference to FIGS.

First, in step S111, input / output condition extraction processing is performed by the input / output condition extraction device 411 for the first column of the output condition unit e and the input condition unit f of the above-described tabular circuit description. Then, the output line extracting device 421 performs output line information extraction processing. Then, in step S113, the input logic extraction device 4
31 performs input logic extraction processing.

In steps S114 to S120, conversion to a functional language is performed based on the input / output conditions, output line information, and input logic extracted in the above three steps S111 to S113.

That is, in step S114, W,
The S, R instruction creating device 413 creates W, S, R instructions. Next, in step S115, a timer instruction creating device 423 performs a timer instruction creating process, and then in step S116, a bit collection instruction creating device (A
(Instruction creation device) 441, and in step S117, & instruction creation device 433 performs the # instruction creation process. In step S118, the timer setting value creation device 424 performs a timer setting value creation process. In step S119, the output command creation device 425 performs an output command creation process. Then, finally, in step S120, the monitoring word generation instruction generation device (F instruction generation device) 451 performs a monitoring word generation instruction generation process.

Subsequently, the next column (the second column of the output condition section e and the input condition section f) is searched, and there is an instruction (output condition symbol) "W", "S" or "R" in this column. It is determined whether or not. If there is any instruction (output condition symbol), the flow returns to step S114 to return to steps S114 to S114.
Repeat step 120.

The above processing is performed for all the columns of the table-form circuit description, whereby the source storage device 401 shown in FIG.
Is converted into the functional language shown in FIG. 7 and stored in the functional language storage device 501 shown in FIG.

Next, the above steps S114 to S120
Will be described in detail. FIG.
14 is a flowchart of an input / output condition extraction process in 114.

In the figure, the input / output condition extraction device 411
First, the output condition part e of the tabular circuit description shown in FIG. 6 is searched in units of columns, and a) the symbols "W", "R", "S" and the line numbers in which those symbols are described B) The line number in which the symbol "A" is described is extracted, and c) is further extracted.
The line number in which the symbol "F" is described is extracted (step S131). Then, these extraction results are stored in a predetermined area of the input / output condition storage device 412 (step S13).
2).

Subsequently, the input condition part f of the above-described tabular circuit description is searched in units of columns, and the symbols "o" and "x", the word memory bit position symbols (hexadecimal values) and these symbols are described. The line number of the input description line is extracted (step S133). Then, these extraction results are stored in the input / output condition storage device 412 (step S134).

As a result, the data shown in FIG. 8 described above is stored in the input / output condition storage device 412. FIG.
Is a flowchart of the output line information extraction process in step S115.

The output row extraction device 421 searches the output name part a and the timer setting value part c of the table-form circuit description shown in FIG. 6 for each row, and extracts the output name and the timer setting value (step S141). Then, the extracted output name and timer set value are stored in the output line information storage device 422 (step S142).

Thus, the above-described data shown in FIG. 9 is stored in the output row information storage device 422. FIG.
Is a flowchart of the input logic extraction process in step S123.

The input logic extracting device 431 first searches the logical part d of the table-form circuit description shown in FIG. 6 in units of rows (step S151), and the last end of the logical symbol (the result of the logical operation) is found in the search row. It is determined whether or not it exists (step S15)
2). If the last end exists, the logic is traced from this last end, and this logic is converted into a functional language (step S153). Further, the functional language is stored in a predetermined area of the input logic storage device 432 (step S15).
4).

On the other hand, if it is determined in step S152 that the last end of the logical symbol (the result of the logical operation) does not exist in the search row, the input signal name described in the input name section b of the corresponding row is extracted. Then, the input signal name is stored in a predetermined area of the input logical storage device 432 (step S157).

As a result, the storage state shown in FIG. 10 described above is realized in the input logical storage device 432. FIG.
9 is a flowchart of the W, S, R instruction creation processing in step S114.

The W, S, R instruction creation device 413 checks the types of “W”, “S”, and “R” instructions from the first column of data in the input / output condition storage device 412 shown in FIG. In the example, “W” is extracted (step S161), and the extracted instruction “W” is stored in a predetermined area of the functional language storage device 501 (step S162).

Thus, the W instruction “(W)” shown in FIG. 23 is stored in the functional language storage device 501.
9 is a flowchart of the timer instruction creation process in step S115.

The timer instruction creation device 423 stores one of the data stored in the input / output condition storage device 412 shown in FIG.
The output row number in the column (in the example shown in FIG. 8, for example, "1" is stored in the first column) is extracted (step S171). Next, the data stored in the output line information storage device 422 shown in FIG. 9 is read, and it is determined whether or not the timer setting value exists in the line of the extracted output line number (the first line in this case). (Step S172). When the timer setting value is described, the timer setting value (“DIABCD” in the example of FIG. 2) and the output signal name set in the output name part a of the line in which the timer setting value is described (“T.SSTIM” in the example of FIG. 6) is extracted (step S173), and the output signal name “T.SSTIM” is extracted.
The current timer value name “TRSST”
IM ”is created (step S174). In this processing, in the present embodiment, the output signal name and the timer current value name are associated one-to-one in a format as shown in FIG. 24, and the timer current value name is created based on this correspondence. .

Subsequently, the created timer current value name “TRSSTIM” and the timer command “TON” are stored in a predetermined area of the functional language storage device 501 (the address following the previously stored “W” command) ( Step S175).

As a result, the description of the functional language as shown in FIG. 25 is stored in the functional language storage device 501. If the timer set value does not exist in step S172, the process of steps S173 to S175 is not performed, and the timer instruction creation process ends immediately.

FIG. 17 is a flowchart of the bit collection instruction creation process in step S116. In the figure, a bit collection instruction creation device (A instruction creation device)
441 first searches the input / output condition storage device 412,
From the stored data shown in FIG. 8, the number of the output description line (A output line number) which is the output description line in which the "A" symbol exists in the corresponding column of the output condition part e is extracted. Subsequently, the output name described in the output name section a of the A output row is extracted from the output row information storage device 422, and the bit base address of the output word memory is generated based on the output name.
Then, this is stored in the bit base address storage device 442 (step S176).

In the case of the tabular circuit description shown in FIG.
The bit base address “M.0000” of the word memory is generated from the output name “WM0000” described in the output name portion “a” of the second output description line, which is the output line, and the generated bit base address is stored in the bit base address storage device 442. To be stored.

Subsequently, the input / output condition storage device 412
Is checked to see if there is an input description line in which the word memory bit position symbol (hexadecimal value) exists in the corresponding column of the input condition part f (step S177), and if so, the line number of the input description line Is extracted from the input logical storage device 432 (step S17).
8). A bit address of the output word memory is created by adding the hexadecimal value indicated by the word memory bit position symbol to the bit displacement portion of the bit base address of the created output word memory (step S).
179). Then, an instruction to write the extracted name into this bit address is created and stored in the bit collection instruction storage device 443 in FIG. 5 (step S180).

According to the above processing, in the case of the table format circuit description shown in FIG.
The bit collection instruction over two rows as shown in FIG. The bit collection command defines a start condition, an operation condition, and the like. If the hexadecimal value indicated by the word memory bit position symbol is "0", these conditions are stored in the 0th bit of the output word memory.
That is, the condition is stored at an address obtained by adding the hexadecimal value "0" to the bit base address "M.0000" of the output word memory. In the circuit diagram shown in FIG.
Start condition or operation condition (> = 1 (& I.0002! I.000
3) Replace I.0004) with M.0, which is the 0th bit of the output word memory. 0000, a circuit description designating the writing into the output condition part e, the logic part d, and the input condition part f
And the word memory bit position symbol (hexadecimal value).

FIG. 18 and FIG.
17 is a flowchart of & instruction creation processing in 17.
& Instruction creation device 433, first, input / output condition storage device 4
12 (step S181), and it is determined whether or not a plurality of "O", "X", or a plurality of word memory bit position symbols (hexadecimal values) exist for each column of the stored data shown in FIG. 8 (step S181). S182).

In this determination, if there are a plurality of the above symbols,
The "&" instruction is stored in a predetermined area of the functional language storage device 501 (step S183), and the fact that the "&" instruction is stored in the functional language storage device 501 is stored (step S184). Proceed to S185. As a result, the storage state of the functional language storage device 501 is as shown in FIG.
As shown in FIG.

On the other hand, in step S182, if the retrieved column does not include a plurality of “○”, “×”, or a plurality of word memory bit position symbols (hexadecimal values), the processing in steps S183 and S184 is not performed. The process immediately proceeds to step S185.

Subsequently, the data area of the input / output condition storage device 412 is searched (step S185), and the row number having "O" or "X" in the corresponding column is extracted from the storage data shown in FIG. The corresponding name described in the input description line of the extracted line number is extracted from the storage data of the input logical storage device 432 shown in (1), and the extracted corresponding name is stored in a predetermined area of the functional language storage device 501 ( Step S186).

Next, it is determined whether or not the extracted input condition is "x" indicating signal inversion (step S18).
7) If "x", it is determined whether or not the stored name is an atom (step S188).

If it is determined that the corresponding name is an atom, "!" Indicating inversion is added to the head of the corresponding name (step S189), and the flow advances to step S193.
On the other hand, if the stored name is a list in the above determination, it is determined whether or not the function name of the list is “NOT” of the inversion command (step S190). If the function name is "NO
If it is "T", the "NOT" function is removed to further invert the inversion command "NOT" (step S191), and the process proceeds to step S193. If the function name is not "NOT", the list is displayed as "(NOT
)) And inverts the value as a “NOT” function (step S192), and proceeds to step S193.

Subsequently, the input / output storage device 412 shown in FIG.
(Step S193), and extracts the line number of the input description line in which the word memory bit position symbol (hexadecimal value) exists. I do. Then, a bit collection instruction corresponding to the extracted row number is extracted from the data stored in the bit collection storage device 443 shown in FIG. 26, and stored in a predetermined area of the functional language storage device 501 in FIG. 5 (step S194). ). For example, in FIG. 6, the word memory bit position symbol (hexadecimal value) is described in the third and sixth lines of the input description line, and the values described in these lines are “0”, Since it is “1”, the input logic is extracted from the data “0” and “1” shown in FIG. 26 and stored in a predetermined area of the functional language storage device 501.

Thus, the functional language storage device 501 stores the functional language up to the state shown in FIG. As described above, the & instruction indicates “○”,
When a plurality of "x" or word memory bit position symbols (hexadecimal values) are present, this instruction is a logical sum of each signal / logical expression in the input description line in which those symbols are described.

FIG. 20 is a time chart of the timer set value creation processing in step S118. First, the timer setting value creation device 424 searches for data stored in the output row information storage device 422 shown in FIG. 9 (step S19).
5) It is determined whether a timer set value name exists in the corresponding line (step S196). Then, if the timer set value name exists, the timer set value (“DIABCD” in the example of the figure) is stored in a predetermined area of the functional language storage device 501 (step S197). Then, if the creation of the & instruction is stored in the & instruction creation processing described above, the & instruction "(" indicating the end of (&) "is stored subsequently (step S198).

If the & instruction has not been created, the step S198 is skipped and the timer set value creating process is immediately terminated. Also, in the case where the timer set value name does not exist in step S195, the process is immediately terminated.

As described above, steps S195 to S195
When 198 is executed, the functional language storage device 501 stores the functional language up to the state shown in FIG.
FIG. 21 is a flowchart of the output command processing in step S119.

The output command creating device 425 outputs the output signal corresponding to the output description line in which the symbol “W”, “S” or “R” is described from the data stored in the output line information storage device 422 shown in FIG. Name (in this example, "T.
SSTIM ”), and stores the signal name in a predetermined area of the functional language storage device 501 (step S20).
1), end the process.

By this processing, the functional language storage device 50
1 stores a functional language up to the state shown in FIG. FIG. 22 is a flowchart of the monitoring word generation instruction creation processing in step S120.

The monitoring word generation instruction creating device (F instruction creating device) 451 first searches the input / output condition storage device 412 (step S211). Then, the line number of the output description line in which the “F” symbol exists in the corresponding column of the output condition part e is extracted from the stored data shown in FIG. Further, the output name (SI000 in this case) described in the output name part a of the output description line in which the “F” symbol exists is extracted from the output line information storage device 422. Further, the input condition part f
A monitoring word generation for highlighting a word memory bit position symbol (hexadecimal value) designating a bit position set OFF in an output word memory (monitoring word memory) corresponding to the extracted output name. Create instructions. And this instruction (here :: = SI00
00 SI0000) is stored in a predetermined area of the functional language storage device 501 of FIG.

With the above processing, the functional language storage device 5
01 stores the functional languages up to the portion 501-10 shown in FIG. Here, the monitoring word generation instruction “: = SI0000 SI0000” will be described. This instruction represents an operation of substituting the contents of the output word memory SI0000 into the same word memory SI0000. This operation is the substitution of the same memory contents for the same memory, and P
It has no meaning on C. However, on a programming device (circuit diagram creating / translating device), it is necessary to store the address of this memory, so such a pseudo instruction code is created.

The output word memory SI0000 is
On the monitor screen that displays the tabular circuit description shown in FIG.
Data specifying a word memory bit position symbol (hexadecimal value) to be highlighted in the input condition part f is stored. For example, if the content of output word memory SI0000 is hexadecimal "FFFE" during online monitoring, this value is represented by 16 digits in binary notation, and only the least significant bit is "0" (bit position 0 is 0). off). In this case, the portion where "0" is described as the word memory bit position symbol in the input condition part f is highlighted. That is, in the example shown in FIG. 6, the hexadecimal value "0" (input description line in which I.0002 is described) on the column (48-1) in which the "F" symbol is set in the output condition part e. Is highlighted in red, for example.

On the other hand, assuming that the content of the output word memory SI0000 is hexadecimal "FFFD", this value is represented by 16 digits in binary notation, and only the second bit from the least significant bit is "0" ( Bit position 1 is off). In this case, I. The word memory bit position symbol (hexadecimal value) "1" in the row where 0005 is described is highlighted. Also, if the content of the output word memory SI0000 is 16
If it is a hexadecimal number "FFFC", this value is represented by 16 digits in a binary number representation, and the least significant bit and the second bit from the least significant bit become "0" (bit positions 0 and 1).
Is off). In this case, I. 0002 and I. 0005
Is described in the word memory bit position symbol (1
Hexadecimal value) “0” and “1” are both highlighted.

FIG. 31 shows an example of a monitor screen at the time of online monitoring. FIG. 11 shows a monitor screen when the process related to the column 51 is being executed. At this time, column 5
1, the symbol "F" described in the output description line "K"
Accordingly, the word memory bit position symbols (hexadecimal values) described in the input description lines "B" and "G" are highlighted. Here, it is indicated by the mark ●.

As described above, the starting conditions, operating conditions, etc.
On the output word memory, it is stored in the bit corresponding to the hexadecimal value indicated by the word memory bit position symbol. For example, if the hexadecimal value indicated by the word memory bit position symbol is “0”, the above condition and the like are satisfied when the bit M. 00
00 is stored. On the other hand, in the output word memory corresponding to the name “SI0000” of the line in which the symbol “F” is described in the output condition part e, for example, if “FFFE” is set in hexadecimal, the hexadecimal value becomes "0"
Is highlighted.
That is, if "FFFE" is set in the output word memory SI0000 in hexadecimal, the bit M.F. 0000 becomes a failure factor, this bit The word memory bit position symbol “0” of the input condition part f related to 0000 can be highlighted. Here, since the logical expression corresponding to the word memory bit position symbol “0” is described in the logical part d, the bit M.D. If 0000 causes a failure, the input signal “I.0002”, “I.0003”, or “I.00”
04 "can be easily recognized as having a cause, and failure analysis can be performed quickly.

As described above, by the steps S111 to S120 of the overall processing shown in FIG. 11, the functional language based on the description data in the first column of the output condition part e and the input condition part f of the tabular circuit description shown in FIG. Conversion is performed. And
The following steps S114 to S120 are repeated, and the above-described conversion is performed for the second and subsequent columns. The table-form circuit description in FIG. 6 is converted into the functional language shown in FIG. 7 and stored in the functional language storage device 501. You.

As described above, according to this embodiment,
By using the symbol "A" and the word memory bit position symbol (hex value), the bit memory (I.000)
2, I. 0003, I. 0004, I. [0005] It is possible to easily describe, in the output word memory (M.0000, M0001), the start conditions and the exercise conditions of the automatic driving and the like assigned to the above-mentioned “0005”).

Further, it is possible to describe the logic for creating the start condition, the operation condition and the like using the respective bits (M0000, M0001) of the word memory obtained in this way with good readability.

Further, in the condition monitoring word memory, the word memory which causes a failure can be highlighted.

[0146]

As described above, according to the present invention,
The following effects can be obtained. By describing the word memory allocation symbol in the output condition part of the output description line, the bit base address of any word memory can be specified. In addition, by describing the word memory bit position designation symbol in the input condition part of the input description line , Any bit position of the bit base address can be designated. The word memory allocation symbol allows designation of writing of a logical operation result of a logical part or an input signal whose name is described in an input name part in this bit position, so that a start condition and an operation condition such as an automatic operation can be monitored. In this case, the circuit description for collecting the external input contact information to be monitored and the monitoring information such as the internal memory in a one-word memory can be described in a small-sized circuit with good readability in a tabular form. Thus, a circuit for monitoring start-up conditions, operating conditions, and the like using arbitrary bits of the word memory used for collecting monitoring information can be described in a table format with good readability.

Further, by describing the highlighting symbol in the output condition part of the output description line, the word memory corresponding to the output description line in which the highlighting symbol is described is written according to the contents.
Certain word memory bit position symbols can be highlighted. The description related to the highlighting can be made in a small space and has good readability. For this reason, the operating state of the programmable controller can be easily grasped, and if a failure or the like occurs, the switching can be quickly performed.

Further, the bit collection operation to a certain word memory designated by the word memory allocation symbol and the word memory bit position symbol in the circuit description of the above format can be automatically converted into a program instruction executable on a PC. . A description for highlighting a word memory bit position symbol specified using a highlighting symbol is described in P.
It can be automatically converted to a program instruction executable on C.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram for explaining a method of describing a circuit in a table format according to an embodiment of the present invention.

FIG. 3 is a logic circuit diagram equivalent to the tabular circuit description of FIG. 2;

FIG. 4 is a diagram illustrating symbols used for describing a circuit in a table according to the present invention.

FIG. 5 is a block diagram of a circuit diagram translator according to one embodiment of the present invention.

FIG. 6 is a diagram illustrating a specific example of a tabular circuit description.

FIG. 7 is a diagram showing a program equivalent to the tabular circuit description of FIG. 6;

FIG. 8 is a state diagram of the input / output condition storage device.

FIG. 9 is a state diagram of an output line information storage device.

FIG. 10 is a state diagram of the input logical storage device.

FIG. 11 is a flowchart of the entire process.

FIG. 12 is a flowchart of an input / output condition extraction process.

FIG. 13 is a flowchart of an output line information extraction process.

FIG. 14 is a flowchart of an input logic extraction process.

FIG. S. It is a flowchart of an R instruction creation process.

FIG. 16 is a flowchart of a timer instruction creation process.

FIG. 17 is a flowchart of a bit collection instruction creation process.

FIG. 18 is a flowchart of an & instruction creation process (part 1);
It is.

FIG. 19 is a flowchart of an instruction creation process (part 2);
It is.

FIG. 20 is a flowchart of a timer setting value creation process.

FIG. 21 is a flowchart of an output instruction creation process.

FIG. 22 is a flowchart of a monitoring word generation instruction creating process.

FIG. 23 is a diagram (part 1) illustrating a functional language stored in a functional language storage device.

FIG. 24 is a diagram illustrating the correspondence between output signal names and timer current values.

FIG. 25 is a diagram (part 2) for explaining the functional language stored in the functional language storage device.

FIG. 26 is a state diagram of a bit collection instruction storage device.

FIG. 27 is a diagram (part 3) for explaining the functional language stored in the functional language storage device;

FIG. 28 is a diagram (part 4) illustrating the functional language stored in the functional language storage device.

FIG. 29 is a diagram (No. 5) illustrating a functional language stored in the functional language storage device.

FIG. 30 is a diagram (part 6) for explaining the functional language stored in the functional language storage device;

FIG. 31 is a diagram illustrating a display example during online monitoring.

FIG. 32 is a diagram showing an example of a ladder diagram.

FIG. 33 is a diagram showing an example of a conventional condition table.

FIG. 34 is a diagram (No. 1) of a truth table.

FIG. 35 is a truth table (No. 2).

FIG. 36 illustrates an example of a logic circuit.

FIG. 37 is a diagram illustrating an example of a ladder diagram.

FIG. 38 is a diagram illustrating an example of a logic circuit.

FIG. 39 is a diagram showing a condition table.

FIG. 40 illustrates an example of a logic circuit.

FIG. 41 is a diagram illustrating a description of rearrangement in a code memory using a ladder diagram.

FIG. 42 is a diagram for explaining rearrangement to a word memory according to the FB diagram;

FIG. 43 is a diagram illustrating a conventional reordering to a word memory based on a tabular circuit description.

FIG. 44 is a diagram showing an example of creation of a word memory for monitoring a start condition and an operation condition by a ladder diagram.

[Explanation of symbols]

Reference Signs List 10 output description line 11 output name part 12 output condition part 20 input description line 21 input name part 22 input condition part 23 logic part 31 output memory 32 monitoring memory 401 source storage device 411 input / output condition extraction device 412 input / output condition storage device 413 W, S, R instruction creation device 421 Output row extraction device 422 Output row information storage device 423 Timer instruction creation device 424 Timer set value creation device 425 Output instruction creation device 431 Input logic extraction device 432 Input logic storage device 433 & Instruction creation Device 441 Bit collection instruction creation device (A instruction creation device) 442 Bit base address storage device 443 Bit collection instruction storage device 451 Monitoring word generation instruction creation device (F instruction creation device) 501 Functional language storage device

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoki Mitsui 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Satoru Watanabe 1st Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Fuji Electric Co., Ltd. (72) Inventor Tsutogi Tsutomu 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Fuji Electric Co., Ltd. (56) References JP-A-6-149311 (JP, A) JP-A-6-14311 (JP, A) JP-A-2-143301 (JP, A) JP-A-58-142708 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G05B 19 / 04-19/05

Claims (5)

(57) [Claims] 1. A circuit diagram creating apparatus for creating a circuit diagram that describes a program running on a programmable controller, a plurality of output lines described and output to describe the output
Multiple input description lines to describe the corresponding input
Each output description line describes the name of an output signal.
Output name part and output condition part that describes the output condition
Each of the input description lines is an input that describes the name of an input signal.
An input condition part for describing the input name part and the input condition,
The logic unit that describes the logic circuit for multiple input description lines
The input condition part and output condition part
Formats with column structures that correspond to each other
A model storing means for storing the model for describing the circuit diagram, and an output name storing the name of the output signal in the output name section.
Output means and output condition input means for describing output conditions in the output condition section.
When the input name entry that describes the name of the input signal to the input name section
Force means and the name described in the input name section in the logic section
Input symbols that indicate the input of
A logical input that describes the logical operation symbol
In the output means and the output condition part, the name is described in the input name part
Input signal or the logical operation result of the above logic unit
Is written to the output memory corresponding to the output description line.
Allocation code that describes the memory allocation symbol indicating that
In the input means and the input condition section, the name is described in the input name section
Input signal or the logical operation result of the above logic unit
Bits in the output memory when writing to the output memory
Bit that specifies the bit position specification symbol
Position designation symbol input means, and the symbol input by each of the above means, the circuit diagram of the model
Storage means for storing in association with the description area, and corresponding to the output description line in which the memory allocation symbol is set.
Signal is assigned to the column where the memory allocation symbol is set.
The bit position designation symbol is described in the corresponding column.
A circuit diagram creation apparatus characterized by being represented by an input signal of a row or a logical operation result . 2. A logical expression corresponding to the bit position designation symbol is created using a name described in the input name portion based on a logical operation symbol described in the logic portion,
2. The circuit diagram creating apparatus according to claim 1, wherein said logical expression is stored in said storage means in association with said bit position designation symbol. 3. The output condition section according to claim 1, further comprising: a highlighting symbol for designating that a corresponding one of the bit position designation symbols is to be highlighted based on the contents of the monitoring memory corresponding to the output description line. More means to describe
2. The circuit diagram creating apparatus according to claim 1, wherein the storage unit stores the highlighted symbols in association with the circuit diagram description area in the format. 4. The circuit diagram creating apparatus according to claim 1,
A circuit diagram translator for translating a created circuit diagram into a language for a programmable controller, wherein input / output conditions for extracting output conditions from the output condition unit, extracting input conditions from the input condition unit, and storing the input conditions, respectively. Extraction / storage means; output line information extraction / storage means for extracting an output name from the output name section and storing the output name as output line information; and a logic circuit described in the logic section corresponding to a predetermined language. An input logic extracting / storing means for converting the statement into a statement to be stored, and an output description line in which the memory allocation symbol is described with reference to the input / output condition extracting / storing means. A base address of the memory is created and stored in the input / output condition extraction / storage means, the output line information extraction / storage means, and the input logic extraction / storage means. The extracted extraction information is read out, and based on the extracted information and the base address of the output memory, the memory bit position designation symbol is described in a bit in the output memory designated by the memory bit position designation symbol. A bit collection instruction for writing an input signal corresponding to an input description line or a logical operation result of the logic unit, and storing the bit collection instruction in a predetermined area of the storage unit. Circuit diagram translator. 5. A circuit diagram creating apparatus according to claim 3, wherein
A circuit diagram translator for translating a created circuit diagram into a language for a programmable controller, wherein input / output conditions for extracting output conditions from the output condition unit, extracting input conditions from the input condition unit, and storing the input conditions, respectively. Extraction / storage means; output line information extraction / storage means for extracting an output name from the output name section and storing the output name as output line information; input / output condition extraction / storage means; and output line information extraction / storage An output description line in which the above-mentioned highlighting symbol is described is extracted by referring to the means. Based on the contents of the monitoring memory corresponding to the extracted output description line, the corresponding symbol in the above-mentioned bit position designation symbol is extracted. A monitoring word generation instruction generating means for generating a monitoring word generation instruction for highlighting and storing the generated instruction in a predetermined area of the storage means. Diagram translator.