JP3130631B2 - Digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit and an FIR
The present invention relates to a digital signal processing device used for a digital signal processing device such as a filter, and particularly includes a calculating means for a polynomial having symmetric coefficients.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing an essential part of an example of an arithmetic unit as such a conventional digital signal processing apparatus. A multiplier 104, an adder 105, a selector 114,
Shift register 115, ROM (read only memory) 107, and ROM address controller 106
It has.

Next, the operation of this conventional example will be described.

The input data 121 stored in the shift register 115 is supplied to the shift register 1 by the selector 114.
The data is called up sequentially from the address 15, while the ROM 10 is read at the address set by the ROM address controller 106.
The coefficients are called in order from 7, and the called data and the coefficient are multiplied by the multiplier 104, the result is added by the adder 105, and the result is outputted. Then, the data in the shift register 115 is shifted and the oldest data is shifted. Discard the data, import new data, and repeat this.

[0005] For example, calculation × 1 = k1a + k2b + k3c + k4d + k4e + k3f + k2g + k1h ... (1) × 2 = k1b + k2c + k3d + k4e + k4f + k3g + k2h + k1i ... (2) × 3 = k1c + k2d + k3e + k4f + k4g + k3h + k2i + k1j ... (3 )), Data (a, b, c,..., H) stored in the shift register 115 is first read out by the selector 114 as shown in FIG.
RO with the address set by the address controller 106
The coefficient k1 stored in M107 is read, and the read data is multiplied by the multiplier 104 to obtain k1.
× a is executed, and the result is input to the adder 105.

Next, the shift register 1 is
15 is read out from the memory 107, and the coefficient k is read out from the ROM 107.
2 is read, k2 × b is executed by the multiplier 104, and the result is added to the adder 105 to execute k1a + k2b added to the previous data. Thereafter, the selector 114 selects data c, d,..., H in this order, and finally executes k1a + k2b + k3c + k4d + k4e + k3f + k2g + k1h and outputs it as x1.

Next, as shown in FIG. 11B, the data in the shift register 115 is shifted to
Is discarded, new data i is fetched, and the selector 114
, I are sequentially read, and the following are executed: k1b + k2c + k3d + k4e + k4f + k3g + k2h + k1i, and x2 is output.

Next, similarly, as shown in FIG. 11C, the data in the shift register 115 is shifted again, the oldest data b is discarded, new data j is fetched, and the data c, d,. e,..., j are read out in order, and k1c + k2d + k3e + k4f + k4g + k3h + k2i + k1j are executed, and x3 is output.

FIG. 12 is a block diagram showing a main part of an FIR filter circuit as another example of a conventional digital signal processing apparatus.
(1) 201a, RAM (2) 201b, adder 20
3, a multiplier 204, an adder 205, a ROM address controller 206, a ROM 207, an accumulator 214, and a register (TR) 215.

Next, the operation of this conventional example will be described.

The input data 12 is stored in the RAM (1) 201a.
One half of the new data is stored in RAM
(2) Half of old data is stored in 201b. At this time, since the filter coefficients of the FIR filter are arranged symmetrically with respect to the center, the RAM (1) 201a sequentially reads out the newest data, and
As for b, data having the same coefficient can be read by sequentially reading from the oldest data. The sequentially read data is sequentially added by the adder 203. The sequentially read and added data and the filter coefficient corresponding to the same coefficient are sequentially read from the ROM 207 and multiplied by the multiplier 204. The multiplication results sequentially output from the multiplier 204 are sequentially added by the adder 205, and all the data in the RAM (1) 201 a and the RAM (2) 201 b are read out. Is completed, the first filter operation output can be obtained. At this time, the last read data from the RAM (1) 201a storing the new data half is added by the adder 203 and stored in the register (TR) 215 at the same time.

Next, data input to obtain the output of the second FIR filter operation is stored in the RAM (1) 201a.
Of the data of the RAM (2) 201b read from the RAM (2) 201b at the same time as overwriting the address where the oldest data is written in the data of the RAM (2) 201b.
The second oldest data is added by the adder 203. The adder 203 sequentially adds the data read from the RAM (1) 201a in the new data order and the data read from the RAM (2) 201b in the old data order, and outputs the result. The multiplier 204 sequentially multiplies the data output from the adder 203 by filter coefficients read in the same order as when the first output was obtained from the ROM 207. The multiplication results are sequentially added by the adder 205 in the same manner as when the first output data is obtained, and an output is obtained.

However, when the last data is read from the RAM (1) 201a, the RAM (2) 201a
Since b is read from the second oldest data, there is no data to be read. However, when the first output data is obtained, RAM (2) is stored in the register (TR) 215.
Since the data to be read from 201b is stored, this data is read and added by the adder 203. The data read from the register (TR) 215 at the same time
(2) The address in which the oldest data in 201b is written is overwritten. The register (TR) 2
15 is the RAM (1) 2 for when the third output is obtained.
01a is newly stored.

FIGS. 13A, 13B and 13C show the RAM (1) 201a and the RAM (2) 2 in the above-described processing.
01b, ROM 207, and register (TR) 215
7A is an initial state, FIG. 7B is a state when Xn is input, and FIG. 7C is a state when Xn + 1 is input. , And the arrow indicates the movement of the address.

Conventionally, as a method of performing the FIR filter operation at high speed, the above-described means using a register for temporarily storing data has been adopted. However, as the oversampling technique has been widely used recently, it has become necessary to implement a decimation filter for converting data having a high sampling rate into data having a low sampling rate of 1/2 ^N by a digital signal processing device. In many cases, the decimation filter also uses an FIR filter whose coefficient is symmetrical with respect to the center, and it is effective to use means for performing the above-described filter operation at high speed. The decimation filter converts data input at a high sampling rate to 1
The output is obtained as data having a low sampling rate of / N. Therefore, it is not necessary to perform the FIR operation for obtaining the output only once every N times of the input data. In a normal FIR filter in which the input and the output have the same rate, only one piece of data can be rewritten to obtain one output.
However, in a decimation filter capable of obtaining an output rate at a rate of 1 / N of the input rate, N pieces of data are rewritten in order to obtain one output. For this reason, RA
The number of data transferred from the M (1) 201a to the RAM (2) 201b is also N, and N registers (TR) 215 for temporarily storing data are required. For this reason,
If the filter operation is performed by the conventional method, the RAM
(1) A plurality of registers for transferring data from the RAM 201 (2) to the RAM (2) 201b are required, resulting in a large circuit.

[0016]

In the above-mentioned conventional digital signal processing apparatus, for example, in the conventional arithmetic unit, when performing calculations in which coefficients are arranged symmetrically with respect to the center, coefficients having the same value are used. Performing each of the multiplication processes requires an extra step, and has a disadvantage that the operation processing time is wasted and the processing speed is reduced.

In the conventional FIR filter,
Since a register (TR) for temporarily storing data to be transferred from the RAM (1) to the RAM (2) is required, a plurality of registers may be used to implement a decimation filter used in the oversampling technique. However, there is a disadvantage that the register (TR) is required and the circuit scale becomes large.

An object of the present invention is to eliminate the above-mentioned drawbacks and to perform an operation in which coefficients are symmetrically arranged.
It is an object of the present invention to provide a digital signal processing device that eliminates useless calculation processing time with the same value of coefficient, improves processing speed, and can reduce the circuit scale without requiring a register (TR) for FIR filter calculation.

[0019]

According to the present invention, there is provided a ROM for storing a coefficient of each term of an arithmetic expression represented by a polynomial, and a ROM storing the ROM.
A ROM address controller for controlling the address of a coefficient read from M, a multiplier for multiplying input data by a coefficient read from the ROM, and a multiplication result output from the multiplier sequentially added to output data And a first adder for outputting the input data, wherein the arithmetic expression is an arithmetic expression whose coefficients are arranged symmetrically around a center, and the input data is a data having the same coefficient. And input data processing means for adding the data to the multiplier and outputting the result to the multiplier.

In a reference example of the present invention, the input data processing means includes a RAM for storing input data at an address corresponding to each data having the same coefficient, and a RAM address controller for controlling an address of the RAM. ,
And a second adder for reading and adding data at the address set by the RAM address controller and outputting the addition result to the multiplier.

Further, according to a reference example of the present invention, the RAM address controller includes an up counter and a down counter for counting the number of coefficients, and a control for counting the number of coefficients and controlling the up counter and the down counter. It can include a counter and a selector, and an exchange for exchanging the values of the up counter and the down counter under the control of the control counter and outputting the same as a read address of the RAM.

Further, according to the present invention, the ROM stores half of the symmetrically arranged coefficients of the arithmetic expression, and the input data processing means stores first and second input data alternately. A second RAM, a RAM address controller for controlling the addresses of the first and second RAMs, and reading and adding the data of the first and second RAMs at the address set by the RAM address controller; And a second adder for outputting to the multiplier.

Also, in the present invention, the ROM stores half of the symmetrically arranged coefficients of the arithmetic expression, and the input data processing means stores N input data (N
Are alternately stored for each of two or more natural numbers), and the first and second RAMs
And control the addresses of the first and second RAMs
A RAM address controller; and a second adder that reads and adds the data of the first and second RAMs at the address set by the RAM address controller, and outputs the addition result to the multiplier. it can.

Further, according to the present invention, the RAM address controller includes an up counter and a down counter for counting the number of coefficients, and a control counter and a selector for counting the number of coefficients and controlling the up counter and the down counter. And an exchange for exchanging the values of the up counter and the down counter under the control of the control counter and outputting the same as read addresses of the first and second RAMs.

[0025]

The input data processing means adds the input data for each data having the same coefficient and outputs the result to the multiplier.
The multiplier reads the coefficient corresponding to the input data from the ROM and performs multiplication.

Therefore, it is only necessary to perform multiplication once for input data having the same coefficient, and the arithmetic processing speed can be increased.

The input data processing means includes a RAM for storing input data in correspondence with each same coefficient, a RAM address controller for controlling the address, and a RAM.
And an adder for adding input data of the same coefficient read from the adder and outputting the result to the multiplier.

As a RAM, first and second Rs for alternately storing input data one by one or every N pieces of data are stored.
By providing the AM, for example, in a FIR filter operation, a data shift circuit between the first and second RAMs is not required, and the circuit scale can be reduced.

Then, the RAM address controller:
Up-counter and down-counter that counts by the number of coefficients, control counter and selector that controls the up-counter and down-counter, and exchanges the value of the up-counter and the value of the down-counter under control of the control counter to output as an address And a changer.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an essential part of a reference example of the present invention, and shows an arithmetic unit. FIG. 2 is a block diagram showing an example of the RAM address controller.

The present embodiment includes a ROM107 that stores the coefficients of the terms of an arithmetic expression represented by a polynomial, the ROM107
ROM address controller 106 for controlling the address of a coefficient read from
Multiplier 10 that performs multiplication with the coefficient read from 107
4 and a first adder 105 that sequentially adds the multiplication results output from the multiplier 104 and outputs output data 122.
In the digital signal processing device provided with the above, the arithmetic expression, which is a feature of the present invention, is an arithmetic expression whose coefficients are arranged symmetrically with respect to the center, and the input data 1
21 for each data having the same coefficient.
A RAM (random access memory) 102 serving as input data processing means for outputting data to the RAM 04 at an address corresponding to each piece of data having the same coefficient, and a RAM address controller 101 controlling an address of the RAM 102 And a second adder 103 for reading and adding data at an address set by the RAM address controller 101 and outputting the addition result to the multiplier 104.

Then, the RAM address controller 10
1 is an up counter 110 that counts the number of coefficients.
And the down counter 111 counts the number of coefficients, and the up counter 110 and the down counter 1
Control counter 108 and selector 10 for controlling
9 and the values of the up counter 110 and the down counter 111 are exchanged by the control of the control
Exchanger 113 which outputs as a read address of 102
And an adder 112 that adds the output of the down counter 111 and a predetermined constant and inputs the result to the exchanger 103.

Next, the operation of the present embodiment, the case 3 which are applied to the following specific examples discussed in the aforementioned conventional example (a)
, (B) and (c).

[0035] × 1 = k1a + k2b + k3c + k4d + k4e + k3f + k2g + k1h ... (1) × 2 = k1b + k2c + k3d + k4e + k4f + k3g + k2h + k1i ... (2) × 3 = k1c + k2d + k3e + k4f + k4g + k3h + k2i + k1j ... (3):: : RAM 10 when calculating equation (1) in the calculation of
2 is in the state of FIG. 3 (a). At the address 00 containing the oldest data, the newest data h is now written, and at the same time the data h is also input to the adder 103. At the same time, the address 13 is read and the adder 10
3 is input. The data a and h are added and sent to the multiplier 104, while the coefficient k1 stored in the ROM 107 is added.
Is read and input to the multiplier 104. In the multiplier 104, k1 (a + h) is executed, and k1 (a + h) is input and held in the adder 105. Next, R shown in FIG.
Read f at address 01 and c at address 12 in AM 102 (c +
f) is executed, the coefficient k3 is read from the ROM 107, and k3
Execute (c + f), and adder 105 calculates k1 (a + h) + k
Execute 3 (c + f). The RAM address controller 101 changes one address of the RAM 102 from 00 → 01 →
Move 02 → 03 and change the other address to 13 → 12 → 1
By moving from 1 to 10, k1 (a + h) + k3 (c + f) + k4 (d + e) + k2 (b + g) is executed.

Next, as shown in FIG. 3 (b), new data i is written into the RAM 102 at the address 13 where the oldest data a was located, and is sent to the adder 103 at the same time. b is read and added. By performing the same procedure as the previous time, k1 (b + i) + k2 (c + h) + k4 (e + f) + k3 (d + g) is calculated. The address at this time is 13 → 12 on one side
→ 11 → 10, the other moves like 03 → 00 → 01 → 02.

In the state shown in FIG.
→ 00 → 01 → 02 and the other is 12 → 11 → 10 → 13
By operating as follows, k1 (c + j) + k3 (e + h) + k4 (f + g) + k2 (d + i) is calculated.

As described above, one address is changed from 00 to 0
1 → 02 → 03 → 13 → 12 → 11 → 10 → 03 → 00
→ 01 → 02 ... and the other address is 13 → 12 → 1
1 → 10 → 03 → 00 → 01 → 02 → 12 → 11 → 10
→ To move to 13, ..., the address controller 101
Are configured as shown in FIG. The control counter 108 composed of a quaternary counter, the up counter 110 and the down counter 111 are synchronized by a clock, and the selector 109 receives a signal from the control counter 108 every time the control counter 108 makes one rotation, and the up counter 110 and the down counter A signal is alternately applied to one of the signals 111. When receiving a signal from the selector 109, the up counter 110 holds a count value for one clock. on the other hand,
When the down counter 111 receives the signal from the selector 109, it counts down by one. The adder 112 adds 10 as a constant to the count value output from the down counter 111 to distinguish it from the output value from the up counter 110.

The exchanger 113 has inputs in1 and in
2, having outputs out1 and out2, directly transmitting the value of the input in1 to the output out1, and directly transmitting the value of the input in2 to the output out2, and the operation of transmitting the value of the input in1 to the output out2.
And the operation of transmitting the value of the input in2 to the output out2. The exchange 113 then controls the control counter 108.
The output is exchanged every time one round is performed, and the address value to be set is transmitted to the RAM 102. In this reference example, the coefficient is 4
Since the number is four, a quaternary counter is used, but the number of coefficients can be changed by changing the number of bits of the counter.

[0040] As described above, according to the present embodiment,
In the calculation having the coefficients of the left and right objects, the calculation procedure can be reduced by increasing the data for each coefficient, and the calculation speed can be increased.

FIG. 4 is a block diagram showing a main part of an embodiment of the present invention, and shows an FIR filter circuit. FIG. 2 is a block diagram showing an example of the RAM address controller.

In this embodiment , the ROM 207 stores half of the symmetrical filter coefficients used for the FIR filter operation.
A ROM address controller 206 for controlling an address of a coefficient read from the ROM 207, a multiplier 204 for multiplying the input data 221 by the coefficient read from the ROM 207, and a multiplication result output from the multiplier 204 And an accumulator 214 for sequentially adding and accumulating the input data 221 and outputting the same as output data 222. And a first RAM for alternately storing the input data 221 one by one or every N pieces as input data processing means for adding the data to the multiplier 204 and outputting the data to the multiplier 204.
(1) 202a and a second RAM (2) 202b;
The RAM (1) 202a and the RAM (2) 202b
RAM address controller 20 for controlling the address
1a, the RAM (1) 202a and the RAM of the address set by the RAM address controller 201a.
(2) a second adder 203 that reads out the data of 202b, performs addition, and outputs the addition result to the multiplier 204;

Then, the RAM address controller 20
1a is an up counter 21 that counts the number of coefficients.
0 and a down counter 211, and a control counter 208 and a selector 2 that count the number of coefficients and control the up counter 210 and the down counter 211.
09, the values of the up counter 210 and the down counter 211 are exchanged by the control of the control
M (1) 202a and an exchange 213 for outputting as read addresses of the RAM (2) 202b.

Next, the operation of the present embodiment will be specifically described for the case of performing an 8-tap FIR filter operation in which the coefficient is folded back at the center.

The coefficients of the FIR filter are a0 to a7, a0 = a7, a1 = a6, a2 = a5, a3 = a4
And the ROM 207 stores a0 to a3. Further, the RAM (1) 202a and the RAM (2) 202b
Store four words of input data 221 respectively. RAM (1) 202a and RAM at this time
(2) FIG. 6A shows a data map of 202b. A procedure for obtaining output data "Yn" when input data "Xn" is input in this state will be described with reference to a data map shown in FIG.

The input data "Xn" is stored in the RAM (2).
At the same time as overwriting the data of “Xn−8” 202b, the “Xn−7” read from the RAM (1) 202a is overwritten.
Is added by the adder 203. Adder 2
In the multiplier 204, the output “Xn + Xn−7” of the filter coefficient “a
0 ". The output “a0 (xn +
Xn-7) "is added to the data of the accumulator 214 by the adder 205 and stored again in the accumulator 214. However, since the accumulator 214 has been reset in advance, the multiplier 2
The output “a0 (Xn + Xn−7)” of 04 is stored in the accumulator 214 as it is.

Next, the address of the RAM (2) 202b is incremented by one. Here, the RAM (1) 202a and the RAM (2)
Since the address pointer of the ROM 202b and the address pointer of the ROM 207 have a modulo configuration, the RAM (2) 202b
Returns to "0". RAM (1) 202a
Is incremented by one, and the address of the ROM 207 is incremented by one. In this state, the RAM (1) 202a and the RAM (2)
When the data is read from the ROM 202b and the ROM 207 and the processing is performed in the same manner as the arithmetic processing, the content of the accumulator 214 becomes "a0 (Xn + Xn-7) + a2 (Xn-2 + Xn-5)". Similarly, the output data "Yn" is obtained by repeating the address processing and repeating the arithmetic processing until all the data is read.
Is "Yn" = a0 (Xn + Xn-7) + a1 (Xn-1 + Xn-
6) + a2 (Xn-2 + Xn-5) + a3 (Xn-3 + Xn-4
) Can be obtained. When the output data is obtained, the address of the RAM (1) 202a is decremented by one, the address of the ROM 207 is decremented by one, and the accumulator 21 is obtained.
4 is reset.

Next, a procedure for obtaining output data "Yn + 1" when the second input data "Xn + 1" is input will be described with reference to a data map shown in FIG.

The input data "Xn + 1" is stored in the RAM
(1) At the same time as overwriting the data of "Xn-7" in 202a, the "Xn" read from the RAM (2) 202b
n−6 ”and the adder 203. Thereafter, data "a0 (Xn + 1 + Xn-6)" of the first accumulator 214 is obtained in the same procedure as when the output data "Yn" is obtained.
At this time, when the previous output data "Yn" is obtained, the RAM
(1) Address of 202a is −1, RAM (2) 202
The address of the ROM 207 is +
1, RAM (1) 202a, RAM
(2) The data may be read from the ROM 202b and the ROM 207 without performing address processing. Subsequently, the same processing as when the output data "Yn" is obtained can be performed to obtain the output data "Yn + 1". The output data "Y
n ”, the address of the RAM (2) 202b is decremented by 1, and the address of the RAM (1) 202a is incremented by +1.
Then, the address of the ROM 207 is incremented by 1, and the output data “Yn +
1 ”is ended.

As described above, the second output data “Yn + 1”
Is obtained, the input data is written to the RAM (1) 202a different from the one obtained when the first output data "Yn" is obtained, and the address control of the RAM (1) 202a and the RAM (2) 202b is switched. Output data "Yn +
1 "you can get. The third output data "Y
n + 2 "when you get a can obtain output data by the same procedure as when obtaining the first output data" Y _n ".

According to this embodiment , as described above, the RAM (1) 202a and the RAM (2) 202
By writing the input data 221 alternately to b, a small-scale FIR filter circuit that does not require a circuit using a register (TR) as in the related art can be realized.

Next, in this embodiment , 1 / N (N is 2
The operation of decimation to the above (natural number) will be described.

In the case of decimation by 1 / N, it is not necessary to obtain output data for each input data. Input data N
It is only necessary to obtain an output once.

Suppose that N = 4, the number of taps of the FIR filter is 32, the filter coefficient is K0 to K31, and the filter is symmetrical with respect to the center. K0 = K31, K1 = K30, K
2 = K29,..., K15 = K16, and the ROM 207 stores "K
0 to K15 ". Each of the RAM (1) 202a and the RAM (2) 202b stores 16 words of the input data 221. RAM (1) 2 at this time
FIG. 7 shows a data map of the RAM 02a, the RAM (2) 202b, and the ROM 207. A procedure for decimation by 1/4 from this state will be described. 4 as described above
Since it is sufficient to obtain an output for one input data, four data are continuously input. First, "Xn-
A procedure for obtaining output data "Yn" when four pieces of input data of "3 to Xn" are input will be described with reference to a data map shown in FIG.

The input data "Xn-3" is stored in the RAM.
(2) At the same time as overwriting the data of “Xn-35” in 202b, the adder 203 adds the data of “Xn-28” read from the RAM (1) 202a. The output data “Xn−3 + Xn−28” of the adder 203 is the multiplier 2
At 04, the filter coefficient is multiplied by the filter coefficient "K3" read from the ROM 207. The output “K” of the multiplier 204
3 (Xn-3 + Xn-28) is added to the accumulator 214 by the adder 205.
And stored in the accumulator 214 again. However, since the accumulator 214 has been reset in advance, the output "K3 (Xn-3 + Xn-28)" of the multiplier 204 is stored in the accumulator 204 as it is.

Next, the address of the RAM (2) 202b is incremented by one. Further, the address of the RAM (1) 202a is -1.
Then, the address of the ROM 207 is incremented by one. In this state, the next input data “Xn−2” is stored in “Xn−” of the RAM (2) 202b.
When the above operation is similarly performed by overwriting the data of "34", the content of the accumulator 214 becomes "K3 (Xn-3 + Xn-2)".
8) + K2 (Xn-2 + Xn-29) ". Similarly, address processing, input data processing and arithmetic processing are repeated up to input data "Xn". The content of the accumulator 214 at this time is "K3 (Xn-3 + Xn-28) + K2 (Xn-2 + Xn-29)
+ K1 (Xn-1 + Xn-30) + K0 (Xn + Xn-31) ". The address processing is again performed in the same manner, and the RAM (2) 20
2b, the data “Xn-11” is read from the RAM (1) 2
The data "Xn-20" is read from the data 02a, and the calculation process is repeated until all the data is read in the same manner as described above, whereby the output data "Yn", "Yn" = K0 (Xn + Xn-31) + K1 (Xn-1 + Xn) -
30) +... + K15 (Xn-15 + Xn-16) can be obtained. When the output is obtained, the address of the RAM (1) 202a is decremented by 4 to obtain the next output.
The address of 207 is incremented by 1, and the accumulator 214 is reset.

Subsequently, when four input data of "Xn + 1 to XN + 4" are input, the second output data "Yn + 1" is output.
Will be described with reference to a data map shown in FIG.

The input data "Xn + 1" is stored in the RAM
(1) The data is overwritten on the data of “Xn-31” in 202a, and at the same time, the data of “Xn-24” read from the RAM (2) 202b is added by the adder 203. Thereafter, data "K3 (Xn + 1 + Xn-24)" of the first accumulator 214 is obtained in the same procedure as when the "Yn" output is obtained. At this time, when the previous output is obtained, the address of the RAM (1) 202a is set to -4, the address of the RAM (2) 202b is set as it is, and the address of the ROM 207 is set to +1.
RAM (1) 202a, RAM (2) 202b and R
Data may be read from the OM 207 without performing address processing. Subsequently, the address of the RAM (2) 202b is decremented by 1, and the address of the RAM (1) 202a is decremented by +.
1, the output data "Yn + 1" can be obtained by repeating the same process as when the address of the ROM 207 is incremented by 1 and the previous output data "Yn" is obtained. When the output data is obtained, the same as when the output data “Yn” is obtained, R
The address of the AM (2) 202b is decremented by -4 and the ROM 207
Is incremented by 1, and the accumulator 214 is reset.

As described above, the second output data "Yn + 1"
Is obtained, four input data are written into the RAM (1) 202a which is a data storage circuit opposite to the one obtained when the first output data "Yn" is obtained, and at this time, the RAM (1)
The output data "Yn + 1" can be obtained by exchanging the address control between the RAM 202a and the RAM (2) 202b. When the third output data "Yn + 2" is obtained, it can be obtained in the same procedure as when the first output is obtained.

According to this embodiment , the RAM (1) 202a and the RAM (2) 202
By alternately writing data to b, it is possible to realize an FIR filter circuit with a small circuit size that does not require a circuit using a register (TR) as in the related art.

In this embodiment , the above-mentioned RAM (1)
The address control of the RAM 202a and the RAM (2) 202b is performed by the RAM address controller 201a shown in FIG.
It is performed by

In FIG. 5, the control counter 208, the up counter 210 and the down counter 211 are composed of quaternary counters, and operate in synchronization with a clock. The cycle of this clock is the same as the operation cycle of the circuit of this embodiment . The control counter 208 provides a signal to the selector 209 and the exchange 213 every time the control counter 208 makes one rotation. Selector 2
09 receives a signal from the control counter 208 and alternately supplies a signal to either the up counter 210 or the down counter 211. Upon receiving a signal from the selector 209, the up counter 210 holds a count value for one clock. On the other hand, the down counter 211
When the signal from 9 is received, it counts down by one count. The exchange 213 has an input in1 and an input i.
n2, output out1 and output out2, and input i
The value of n1 is output to out1, and the value of input in2 is output to out
Operation to directly transmit to t2 and output of value of input in1 to output out
2, the operation of transmitting the value of the input in2 to the output out1. The exchange 213 exchanges the output each time it receives a signal from the control counter 208 to change the RAM (1) 2
02a and the address of the RAM (2) 202b are exchanged. RAM (1) 202a and RAM at this time
(2) FIG. 6 (a), (b)
And (c) and those shown in FIGS. 7, 8 and 9.

Note that the address control by the RAM address controller can be controlled by a program by a processor.

[0064]

As described above, the present invention has the effect of reducing the number of calculation steps and increasing the calculation speed by forming data for each coefficient in the calculation having symmetric coefficients.

In an FIR filter circuit, for example, by storing input data in two RAMs alternately one by one or every N pieces, a register for transferring data between the two RAMs becomes unnecessary, and the circuit scale is reduced. Has the effect of reducing

Therefore, according to the present invention, a high-speed and small-scale digital signal processing device suitable for a semiconductor integrated circuit that can reduce the chip area and reduce the cost can be obtained, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a reference example of the present invention.

FIG. 2 is a block diagram showing an example of the RAM address controller.

FIG. 3 is an explanatory diagram of the operation of the RAM.

FIG. 4 is a block diagram showing a main part of the embodiment of the present invention.

FIG. 5 is a block diagram showing an example of the RAM address controller.

FIG. 6 shows the RAM (1), RAM (2) and ROM
Data map.

FIG. 7 shows the RAM (1), RAM (2) and ROM
Initial data map of.

FIG. 8 shows the RAM (1), RAM (2) and ROM
Data map of the input state of the data "Xn-3 to Xn".

FIG. 9 shows the RAM (1), RAM (2) and ROM
Data map of the input state of the data "Xn + 1 to Xn + 4".

FIG. 10 is a block diagram showing a main part of a first conventional example.

FIG. 11 is an explanatory diagram of the operation of the RAM.

FIG. 12 is a block diagram showing a second conventional example.

FIG. 13 shows the RAM (1), RAM (2) and RO
M data map.

[Explanation of symbols]

101, 201, 201a RAM address controller 102 RAM 103, 105, 112, 203, 205 Adder 104, 204 Multiplier 106, 206 ROM address controller 107, 207 ROM 108, 208 Control counter 109, 114, 209 Selector 110, 210 Up counter 111, 211 Down counter 113, 213 Switch 115 Shift register 202a RAM (1) 202b RAM (2) 214 Accumulator 215 Shift register (TR) 121, 221 Input data 122, 222 Output data

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yuichi Maruyama 1-403-3, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within NEC Icy Microcomputer Systems Co., Ltd. (56) References JP-A-63-113756 (JP, A) IEICE Technical Report 91 [192] (H3-8-23) p. 49−55

Claims (2)

(57) [Claims] 1. A ROM for storing coefficients of respective terms of an arithmetic expression represented by a polynomial, a ROM address controller for controlling an address of a coefficient read from the ROM, input data and a coefficient read from the ROM. And a first adder for sequentially adding the multiplication results output from the multiplier and outputting output data, wherein the coefficients of the arithmetic expression are centered. And an input data processing means for adding the input data for each data having the same coefficient and outputting the result to the multiplier. The input data processing means comprises a first and a second RAM for alternately storing input data, respectively. A RAM address controller for controlling an address of the first and second RAM, to the multiplier the addition result to perform the addition reading data of said first and second RAM address this RAM address controller sets And a second adder for outputting the number of coefficients.
Control signal is output every time the up counter and down counter that count
Control to control the up counter and down counter
A counter and the above-mentioned object to be controlled by the control of the control counter.
One of the top counter and the down counter alternately
The selector to be selected and the up counter and the previous counter controlled by the control counter.
The values of the down counter are exchanged, and
Exchanger that outputs as read address of second RAM
Digital signal processing apparatus characterized by including and. 2. A ROM for storing coefficients of each term of an arithmetic expression represented by a polynomial, a ROM address controller for controlling an address of a coefficient read from the ROM, input data and a coefficient read from the ROM. And a first adder that sequentially adds the multiplication results output from the multiplier and outputs output data. And an input data processing means for adding the input data for each data having the same coefficient and outputting the result to the multiplier. And the input data processing means stores N pieces of input data (N is 2
A first and a second RAM for alternately storing each of the above natural numbers, a first and a second RAM, and a RAM for controlling addresses of the first and the second RAMs
An address controller and the first and second RAMs for addresses set by the RAM address controller
And a second adder for reading out and adding the data and outputting the addition result to the multiplier, wherein the RAM address controller counts the number of coefficients.
Control signal is output every time the up counter and down counter that count
Control to control the up counter and down counter
A counter and the above-mentioned object to be controlled by the control of the control counter.
One of the top counter and the down counter alternately
The selector to be selected and the up counter and the previous counter controlled by the control counter.
The values of the down counter are exchanged, and
Exchanger that outputs as read address of second RAM
Digital signal processing apparatus characterized by including and.