JP3130764B2 - Variable delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit used in, for example, a phase synchronization circuit applied to a serial signal interface of a communication system.

[0002]

2. Description of the Related Art FIG.
It is a block diagram which shows the structure of the bit phase synchronization circuit described in the 6007 application. This bit phase synchronization circuit includes a variable delay circuit 31 for adjusting the phase of a signal I ₀ input from a terminal 21, and a signal I ₁ output from the variable delay circuit 31 for a clock signal C input from a terminal 22.
In synchronization with the LK configured from the synchronization detection circuit 35 for causing output from the terminal 23 as a signal I _2. Variable delay circuit 3
1 is a delay element 32 ₁ ,..., 32 _m connected in series from the first stage to the m-th stage (m is an integer);
2 _1, ..., 32 switching circuits 33 ₁ connected to the respective output terminals of _m, ..., and 33 _m, these switching circuits 3
3 _1, ..., and an up-down counter circuit 34 which selects any one of 33 _m to the signal output state. The synchronization detection circuit 35 outputs the determination result signal S ₁ to the up / down counter 34 so that the phase of the signal I ₁ from the variable delay circuit 31 and the phase of the clock signal CLK have a predetermined relationship. is output from the terminal 23 in the signal I ₁ timing synchronized with the clock signal CLK.

FIG. 5 is a signal waveform diagram when the delay elements 32 ₁ ,..., 32 _m of the variable delay circuit 31 are constituted by CMOS non-inverting buffers. In general, the hole mobility of carriers is larger than that of electrons, so that the PMOS transistor has a lower current supply capability than the NMOS transistor. In a CMOS circuit, the logic level changes from H level (high level) to L level (low level). Fall time T
The rise time _Tr from the L level to the H level is longer than _f (T _r > T _f ). Therefore, the delay elements 32 ₁ ,
.., 32 _m are constituted by CMOS non-inverting buffers.
As shown by the waveforms A ₁ , A ₂ , and A ₃ , a time difference (T _r −T _f ) between the rise time _Tr and the fall time T _f is accumulated every time the signal passes through the delay element. However, there is a problem that the duty ratio of the signal is deteriorated.

[0004] Figure 6 illustrates in order to prevent the duty deterioration, delay elements 32 _1, ..., 32 _m of each of the two-stage inverting buffers 36 ₁ and 36 _2, ..., an example in which in the 36 _2m-1 and 36 _2m It is a block diagram. 7 is a signal waveform diagram showing an output waveform B _1, B ₂ of the inverting buffer 36 _1, 36 ₂ which is expected in the circuit of FIG. In the case of Figure 6, the odd-numbered inverting buffer 36 _1, 36 _3, ..., the time difference between the 36 _2m-1 of the rise time T _r and fall time T _f (T _r -
The change in duty ratio due to T _f), the even-numbered inverting buffer 36 _2, 36 _4, ..., trying to absorb by passing through 36 _2m.

[0005]

However, in the variable delay circuit 31 shown in FIG. 6, the switch circuits 33 ₁ ,...,..., Are provided only at the output terminals of the even-numbered inversion buffers 36 ₂ , 36 _{4 ,.} 33 _m are connected, and only these even-numbered inversion buffers 36 ₂ , 36 ₄ ,..., 36 _{2 m} are affected by the input load of the switch circuit. Since inverting buffer has a low current supply capability is a CMOS circuit, the rising time when the output load is large T _R and the falling time T _F
Greater than the rise time T _r and fall time T _f of the absence of each of the output load _{(i.e., T R> T r, T} F
> T _f ), the time difference between the rise time and the fall time of the even-numbered inversion buffer is larger than the time difference of the odd-numbered inversion buffer (that is, T _R −T _F > T _r).
−T _f ). Thus, each time the signal passes through the delay element, can not be absorbed delay component _{(T R -T F -T r +} T f> 0)
Therefore, there is a problem that the deterioration of the duty cannot be sufficiently prevented, a sufficient timing margin cannot be secured in the latch circuit of the synchronization detection circuit 35 at the subsequent stage, and a signal error may occur. In addition, FIG.
FIG. 9 is a signal waveform diagram showing a state where duty deterioration is accumulated every time a signal I ₀ passes through inversion buffers 36 ₁ , 36 ₂ ,.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a variable delay circuit with less duty deterioration.

[0007]

A variable delay circuit according to the present invention has a function of delaying a signal, and is connected to respective output terminals of a multi-stage inversion buffer connected in series and an even-numbered inversion buffer. And a selection circuit for selecting any one of the switch circuits and outputting a signal based on the signal of the output terminal of the even-numbered inversion buffer from the selected switch circuit, And a load circuit connected to each output terminal of the inversion buffer and having a load equivalent to the switch circuit.

Further, a variable delay circuit according to a second aspect is characterized in that the load circuit is constituted by a dummy switch circuit which is constantly in a non-conductive state.

According to a third aspect of the present invention, in the variable delay circuit, the switch circuit has a MOS transistor, and the load circuit has the same characteristics as the MOS transistor of the switch circuit.
An output terminal of the even-numbered inversion buffer is connected to the gate of the MOS transistor of the switch circuit, and an output terminal of the odd-numbered inversion buffer is connected to the gate of the MOS transistor of the load circuit; It is characterized by being.

[0010]

In the variable delay circuit according to the first aspect, a load circuit having a load equivalent to the switch circuit connected to each output terminal of the even-numbered inversion buffer is connected to each output terminal of the odd-numbered inversion buffer. And make the output load of all inverting buffers the same.

Further, in the variable delay circuit according to the second aspect, the load circuit is constituted by a dummy switch circuit which is constantly in a non-conductive state, thereby eliminating current consumption.

In the variable delay circuit according to the third aspect, each output terminal of the even-numbered inversion buffer is connected to the gate of the MOS transistor of the switch circuit, and each output terminal of the odd-numbered inversion buffer is loaded. It is connected to the gate of the MOS transistor of the circuit, and the output load of the inverting buffer is the same.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a variable delay device according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a bit phase detection circuit including a variable delay circuit according to a first embodiment of the present invention. The bit phase synchronizing circuit includes a variable delay circuit 1 for performing phase adjustment of the signal I ₀ input from the terminal 21, the clock signal CLK input from the signal I ₁ and the terminal 22 that is output from the variable delay circuit 1 together with phase outputs the judgment result signals S ₁ to the up-down counter 7 so as to have a predetermined relationship,
And a synchronization detection circuit 2 to output a signal I ₁ from the variable delay circuit 1 from the terminal 23 at a timing synchronized with the clock signal CLK.

The variable delay circuit 1 includes a first delay circuit for delaying a signal.
Inverting buffers 3 ₁ ,... From the stage to the n-th stage (n is an even number)
.., 3 _n . Inverting buffer 3 _1, ..., 3 _n, the output terminal b are connected in series so as to be connected to the input terminal a of the next stage, the input terminal a of the inverting buffer 3 ₁ of the first stage input terminal 21 It is connected to the. In addition, the variable delay circuit 1
Numbered inverting buffer 3 _2, 3 _4, ..., the switch circuit 5 ₁ connected to the respective output terminals b of the 3 _n, ..., 5
and _{n / 2,} the odd-numbered inverting buffer _{3 1, 3 3, ...,} 3 n-1 of the load circuit 6 ₁ connected to respective output terminals b, ..., 6
_{n / 2,} and an up-down counter circuit 7 for selecting any one of the switch circuits 4 ₁ ,..., 4 _{n / 2} to output a signal.

The switch circuits 5 ₁ ,..., 5 _{n / 2} have two P
It has MOS transistors P ₁ and P ₂ , two NMOS transistors N ₁ and N _2, and an inverter circuit 8.
The drain of the PMOS transistor P ₁ is connected to a power supply V _CC, the source of the PMOS transistor P ₁ is connected to the drain of the PMOS transistor P _2, the source of PMOS transistor P ₂ is an output end of the drain and the switch circuit of the NMOS transistors N ₁ c. Also,
The source of the NMOS transistor N ₁ is connected to the drain of the NMOS transistor N _2, the source of the NMOS transistor N ₂ is connected to the ground point GND. Also,
The gate of the PMOS transistor P _{1 and} the gate of the NMOS transistor N ₂ are connected to the even-numbered inversion buffer 3 ₂ ,
The output terminals b of 3 ₄ ,..., 3 _n are connected, the output terminal of the inverter circuit 8 is connected to the gate of the PMOS transistor P ₂ , and the gate of the NMOS transistor N ₁ and the input terminal d of the inverter circuit 8 are connected up. _One of the output terminals e ₁ ,..., En _{/ 2} of the down counter circuit 7 is connected.

The load circuits 6 ₁ ,..., 6 _{n / 2} are PMOS transistors having the same characteristics as the PMOS transistor P ₁ of the switch circuit.
It has a transistor P ₃ and an NMOS transistor N ₃ having the same characteristics as the NMOS transistor N ₂ of the switch circuit. The drain of the PMOS transistor P ₃ is a power supply V
Is connected to the _CC, the source of the PMOS transistor P ₃ is N
It is connected to the drain of the MOS transistor N _3, NMO
The source of the S transistor N ₃ is connected to the ground point GND. The output terminals b of the odd-numbered inversion buffers 3 ₁ , 3 ₃ ,..., 3 _n−1 are connected to the gate of the PMOS transistor P _{3 and} the gate of the NMOS transistor N ₃ .

[0018] In this embodiment, the even-numbered inverting buffer 3 _2, 3 _4, ..., 3 respective output terminals b of the _n, the switch circuit 5 _1, ..., 5 _{n / 2} of the gate of the PMOS transistor P ₁ And the gates of the NMOS transistors N ₂ , and similarly, the odd-numbered inversion buffers 3 ₁ , 3 ₃ ,
, 3 _n-1 are connected to the load circuits 6 ₁ ,.
6 _{n / 2} gate of PMOS transistor P ₃ and NMOS
It is connected to the gate of the transistor N _3. Therefore, inverting buffer 3 _1, ..., 3 _n connected thereto the output load to the output terminal b of all inverting buffer 3 _1, ..., and the same for 3 _n. Therefore, the odd-numbered inversion buffers 3 ₁ ,
3 _3, ..., 3 _n-1 of the rise time T _RD and the even-numbered inverting buffer 3 _2, 3 _4, ..., equal to the rise time T _RS of _{3 n (T RD = T R} S), the odd-numbered Inverting buffers 3 ₁ , 3 ₃ ,
..., 3 _n-1 falling time T _FD and the even-numbered inverting buffer _{3 2, 3 4, ...,} 3 n equal to the fall time T _FS of it _{(T FD = T F S)} , the signal is odd Th inversion buffer 3
The change in the duty ratio that occurs when the signal passes through ₁ , 3 ₃ ,..., 3 _n-1 is compared with the inversion buffers 3 ₂ , 3 ₄ ,
, 3 _n can be absorbed. Figure 2 is a signal waveform diagram in the variable delay circuit 1, the signal I _0, passed through the inverting buffer 3 _second waveform and a second stage after the signal I ₀ is passed through the inverting buffer 3 ₁ of the first stage The latter waveform is shown.

Further, the synchronization detecting circuit 2 comprises a variable delay circuit 1
, 5 _{n / 2} , the first delay element 9 which receives the signal I ₁ output from any of the switch circuits 5 ₁ ,..., 5 _{n / 2} and outputs a delayed signal I ₂ ; A second delay element 10 which receives the signal I ₂ from the element 9 and outputs a delayed signal I ₃ . The synchronization detection circuit 2 receives the signal I ₁ output from any of the switch circuits 5 ₁ ,..., 5 _{n / 2} selected in the variable delay circuit ₁ and the clock signal CLK from the terminal 22. 1
DFF circuit (D flip-flop circuit) 11 and the first
The second DFF circuit 12 to which the signal I ₂ and the clock signal CLK output from the delay element 9 are input, and the signal I ₃ and the clock signal C output from the second delay element 10
And a third DFF circuit 13 to which LK is input. D
Each of the FF circuits 11, 12, and 13 can latch the input signals I ₁ , I ₂ , and I ₃ with the clock signal CLK.

The decision circuit 14 includes DFF circuits 11, 12,
The signals f, g, h latched in 13 are compared with each other, and if the signals f, g, h are also at the same logic level (eg, logic level 1), the up-down counter circuit 7
Output a logic level 0 to both the terminals UP and DOWN of the switch, and do not change the selected switch circuit.

Of the signals f, g, h, the DFF circuits 11, 1
If the logic levels of the signals f and g from the DFF 2 are the same (eg, logic level 1) and only the logic level of the signal h from the DFF circuit 13 is different (eg, logic level 0), the up-down counter circuit 7 logic level 1 to the terminal UP of the outputs a logic level 0 to the terminal DOWN, the signal I ₁ from the switch circuit is selected to determine to have a phase delay relative to the clock signal CLK, the Change the selected switch circuit to the up direction.

Of the signals f, g, h, the DFF circuits 12, 1
If the logic levels of the signals g and h from the DFF 3 are the same (eg, logic level 1) and only the logic level of the signal f from the DFF circuit 11 is different (eg, logic level 0), the up-down counter circuit 7 a logic level 1 to the terminal DOWN of, outputs a logic level 0 to the terminal UP, the signal I ₁ from the switch circuit is selected to determine to have a phase lead with respect to the clock signal CLK, the Change the selected switch circuit to the down direction.

[0023] As described above, in this embodiment, the inverting buffer 3 _1, ..., 3 _n connected thereto the output load to the output terminal b of all inverting buffer 3 _1, ..., the same for 3 _n there so, as shown in FIG. 2, signal inverting buffer 3 ₁ of odd is, 3 _3, ..., 3 _n-1 change of the duty ratio which occurs when passing through the signal is an even-numbered inverting buffer 3 Since it can be absorbed by passing through ₂ , 3 ₄ ,..., 3 _n , duty deterioration does not occur. Therefore, a sufficient timing margin for the signal latch of the subsequent synchronization detection circuit can be secured.

[0024] The switch circuit 5 _1, ..., 5 n _{/ 2} and the load circuits 6 _1, ..., a 6 n _{/ 2} configuration is not limited to the configuration described above, inverting buffer 3 _1, ..., a 3 _n Any other circuit may be used as long as the output terminal b has the same output load.

Second Embodiment FIG. 3 is a block diagram showing a bit phase detection circuit including a variable delay circuit according to a second embodiment of the present invention. In FIG. 3, the same or corresponding components as those in FIG. 1 are denoted by the same reference numerals. In the second embodiment shown in FIG. 3, a dummy switch circuit 1 is used instead of the load circuits 6 ₁ ,..., 6 _{n / 2} of the first embodiment.
5 _1, ..., only in that with a 15 n / ₂ is different from the first embodiment.

As shown in FIG. 3, the dummy switch circuits 15 ₁ ,..., 15 _{n / 2} include two PMOS transistors P ₃ and P ₄ and two NMOS transistors N ₃ and N _4.
And The drain of the PMOS transistor P ₃ is connected to the power supply V _CC, the source of the PMOS transistor P ₃ is connected to the drain of the PMOS transistor P _4, P
The source of the MOS transistor P ₄ is connected to the drain of the NMOS transistor N _4. The source of the NMOS transistor N ₄ is connected to the drain of the NMOS transistor N _3, the source of the NMOS transistor N ₃ is connected to the ground point GND. The output terminals b of the odd-numbered inversion buffers 3 ₁ , 3 ₃ ,..., 3 _n-1 are connected to the gate of the PMOS transistor P _{3 and} the gate of the NMOS transistor N ₃ , and the gate of the PMOS transistor P ₄ The power supply V _CC is connected and the NMOS transistor N ₄
Is connected to a ground point GND.

As described above, in this embodiment, the PMOS transistor P ₄ and the NMOS transistor N ₃ are always off, and the dummy switch circuit 1 is turned off.
Since 15 ₁ ,..., 15 _{n / 2} are constantly in a non-conductive state, power consumption can be reduced. The other points in the second embodiment are the same as those in the first embodiment.

[0028]

As described above, according to the present invention,
A load circuit with an input load equivalent to the switch circuit is provided at the output end of the odd-numbered inversion buffer so that the output time difference of the odd-numbered inversion buffer can be absorbed by the output time difference of the even-numbered inversion buffer. Therefore, it is possible to prevent the duty from deteriorating, thereby obtaining an effect that the timing margin of the signal latch of the subsequent synchronization detection circuit can be sufficiently secured.

Further, when a dummy switch circuit which is constantly in a non-conductive state is used as the load circuit, the effect that power consumption can be reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a bit phase synchronization circuit including a variable delay circuit according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram in the variable delay circuit of FIG.

FIG. 3 is a configuration diagram illustrating a bit phase synchronization circuit including a variable delay circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram showing a conventional bit phase synchronization circuit including a variable delay circuit.

FIG. 5 is a signal waveform diagram in the variable delay circuit of FIG.

FIG. 6 is a configuration diagram showing another conventional variable delay circuit.

FIG. 7 is an ideal signal waveform diagram in the variable delay circuit of FIG. 6;

8 is a signal waveform diagram showing a problem in the variable delay circuit of FIG.

[Explanation of Signs] 1 variable delay circuit, 2 synchronization detection circuit, 3 ₁ ,.
3 _n inversion buffers, 5 ₁ ,..., 5 _{n / 2} switch circuits,
6 ₁ ,..., 6 _{n / 2} load circuit, 7 up-down counter circuit, 8 inverter circuit, 15 ₁ ,.
_{n / 2} dummy switch circuit.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Oya 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-4-35408 (JP, A) JP-A-1-117514 (JP, A) JP-A-63-204813 (JP, A) JP-A-2-210909 (JP, A) JP-A-3-29411 (JP, A) JP-A-2-254809 (JP JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 5/13

Claims (3)

(57) [Claims] 1. A multi-stage inverting buffer having a function of delaying a signal and connected in series, a switch circuit connected to each output terminal of an even-numbered inverting buffer, and one of the switch circuits And a selection circuit for outputting a signal based on a signal at the output terminal of the even-numbered inversion buffer from the selected switch circuit. A variable delay circuit comprising: a connection circuit connected to each output terminal of the odd-numbered inversion buffer. And a load circuit having a load equivalent to the switch circuit. 2. The variable delay circuit according to claim 1, wherein said load circuit is constituted by a dummy switch circuit which is constantly in a non-conductive state. 3. The switch circuit includes a MOS transistor, the load circuit includes a MOS transistor having the same characteristics as the MOS transistor of the switch circuit, and each output terminal of an even-numbered inversion buffer is connected to the switch circuit. 3. The variable according to claim 1, wherein the output terminals of the odd-numbered inversion buffers are connected to the gates of the MOS transistors of the load circuit. Delay circuit.