JP3134562B2 - Time axis correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correcting apparatus for correcting a time axis of a reproduced video signal, for example.

[0002]

2. Description of the Related Art Conventionally, in a time axis correction device of a VTR of a beta cam system, for example, a reproduced video signal (luminance signal or color difference signal) reproduced by a rotary magnetic head from an inclined track of a magnetic tape is written and read. Memory is provided. A write line address counter for generating a write line address signal for the memory, a write line address counter for generating a write line address signal, and a write line address increment synchronized with a horizontal synchronization signal separated from the reproduced video signal. And a write clock signal generating circuit for generating a clock signal for writing and a write line address increment clock signal and supplying them to the in-write line address counter and the write line address counter, respectively.

A read line address counter for generating a read line address signal for a memory, a read line address counter for generating a read line address signal, a read line address increment clock signal synchronized with a reference horizontal synchronization signal, and A read clock signal generating circuit is provided for generating a read line address increment clock signal and supplying the generated clock signal to the read line address counter and the read line address counter, respectively. Thus, the jitter (time axis error) of the reproduced video signal is corrected.

Incidentally, the write clock signal and the write line address signal follow the jitter of the reproduced video signal, and the read clock signal and the read line address signal are synchronized with the reference horizontal synchronization signal. Therefore, while the read line address signal changes at a constant speed, the write line address signal depends on the reproduction speed of the VTR. For this reason, at the time of variable-speed reproduction of the VTR (mode for reproducing at a different speed from that of recording)
In some cases, the write and read line address signals for the memory coincide with each other, and in that case, the writing and reading of the reproduced video signal to and from the memory cannot be performed normally.

Therefore, conventionally, a memory capable of storing video signals for 32 lines is prepared, and the cycle of the horizontal synchronizing signal in the reproduced video signal becomes longer than the cycle of the reference horizontal synchronizing signal during FWD (forward) variable speed reproduction. Thus, from a certain address, the address of the write and read line address signals becomes coincident, and the already read line before the (integer) line of the memory is read again,
Avoided address matching.

Also, during REV (reverse direction) variable speed reproduction, the period of the horizontal line synchronization signal in the reproduced video signal is shorter than the period of the reference horizontal line synchronization signal. Since the address of the write and read line address signals coincides after the cycle becomes shorter than a certain period, the line of the memory is read n (integer) lines ahead of the current line to avoid address coincidence. I was trying to do it.

By the way, such a time axis correction device is
Since a video signal advanced by, for example, 16 horizontal synchronizations from the reference horizontal synchronization signal is reproduced, in normal reproduction and FWD and REV variable-speed reproduction at a slightly higher speed than normal, the write and read address signals have the same address. Although the coincidence hardly occurs, when the speed of the FWD and REV variable speed reproduction is considerably increased, the coincidence of the addresses of the write and read address signals occurs. Further, since the video signal to be reproduced is ahead of the reference horizontal synchronizing signal by 16 horizontal periods, in variable speed reproduction, the address signal does not match at the upper part of the screen, but the address signal coincides at the lower part of the screen. Immediately before that, the switching of the read address was performed.

With such control, writing and reading of a video signal to and from the memory can be normally performed even at the time of high-speed variable-speed reproduction, and the video signal of variable-speed reproduction can be reproduced as an image on a monitor. However, in the time axis correction device capable of reproducing the video signal of the variable speed reproduction as an image as described above, the information amount in the head trajectory during the REV speed reproduction> the information amount in the head trajectory during the normal reproduction> FWD variable speed reproduction The amount of information in the head trajectory at the time of reproduction is accordingly increased, whereby the period of the horizontal synchronizing signal of the reproduced video signal at the time of FWD variable speed reproduction becomes longer with respect to the reference synchronizing signal.
On the other hand, in the case of V-speed reproduction, the cycle becomes shorter.

[0009] Such a reproduced video signal is written into a memory in line units according to a write line address signal.
When the data is read from the memory in line units in accordance with the read line address signal, the number of lines read during one synchronization signal (one field period) of the reference vertical synchronization signal is constant. The information from the start to the end of the head trajectory is read out for the signal, but the reproduced video signal included in the head trajectory during the REV variable speed reproduction is not read from the start to the end of the head trajectory. As a result, what becomes a substantially perfect circle in normal reproduction, becomes a horizontally long ellipse during FWD variable speed reproduction, that is, a so-called "image shrinkage" phenomenon, and becomes vertically long ellipse during REV variable speed reproduction and lacks lower data.
So-called "image elongation" occurs.

[0010] As described above, if control is performed to prevent the coincidence of addresses at the lower portion of the screen, image distortion occurs in addition to the "image extension" phenomenon.

Further, at the time of variable speed reproduction, the read address is switched according to the reproduction speed. In order to perform the switching with high accuracy, the reproduction speed may be detected and the switching may be performed according to the detected speed. The detection of the reproduction speed is performed based on the deviation of the average horizontal period from the normal reproduction. In order to detect the reproduction speed with high accuracy, it is necessary to increase the frequency of the clock for counting the average horizontal period.

The change in the horizontal cycle per 1 × speed is determined by NTS
4.5 / 262.5 × 100 = 1.7% in C method, PA
Since 5.5 / 312.5 × 100 = 1.76% in the L system, in order to generate a difference in the count number of “1” per 1 × speed, 59 in the NTSC system and 5 in the PAL system.
It is necessary to count 7.

However, since the reproduction speed cannot be detected accurately with this method, it is necessary to increase the frequency of the clock for counting the average horizontal period and further increase the number of counts. In this case, the circuit scale becomes complicated and large.

Therefore, the applicant of the present invention has previously described that the detecting means first detects the single cycle signal of the other periodic signal within the single cycle period of one periodic signal of the synchronous signals synchronized with the reproduced horizontal synchronizing signal and the reference synchronizing signal, respectively. When it is detected that a cycle period is included, the supply of the line address step-up clock signal related to the horizontal synchronization signal synchronized with the other cycle signal to the line address counter is performed by the detection signal from the tape running speed detection means. (Japanese Patent Application No. 3-079152).

The time axis correcting device will be described below with reference to FIGS.

In FIG. 4, FM reproduced by a rotating magnetic head from an inclined track of a magnetic tape (not shown)
The luminance signal and the FM color difference signal are FM-demodulated, respectively,
Each is supplied to an integrated time axis correction device having the same configuration.

A reproduced video signal (luminance signal or color difference signal) from an input terminal T1 is supplied to a sync separation circuit 1 and an A / D converter 2. Reference numeral 3 denotes a write clock generating circuit which synchronizes with the reproduced horizontal synchronizing signal based on the horizontal and vertical synchronizing signals from the synchronizing / separating circuit and which has a frequency of, for example, 858 times in the NTSC system and 864 times in the PAL system. Synchronous with the address stepping clock pulse W0 and the reproduced horizontal synchronizing signal, a line address stepping clock pulse Wc having the same frequency and a duty of 50% is generated.

The write clock pulse W0 from the write clock generating circuit 3 is supplied to the A / D converter 2 and a write line address counter 4x to be described later, and the clock pulse Wc is supplied to a write line address counter 4x and a write line address to be described later. The signal is supplied to the counter 4y and a frequency dividing circuit 12, which will be described later.

Reference numeral 5 denotes a memory, which can store, for example, digital video signals for 32 lines. The write clock generating circuit 3
, And is reset by the clock pulse Wc to generate an in-line address signal and an in-line address signal, and the write line address counter 4y outputs the clock signal from the write clock generation circuit 3. The pulse Wc is counted, and is reset by a vertical synchronization signal from the synchronization separation circuit 1 to generate a line address signal.

The in-line address signals from the in-line address counter 4x and the in-line address counter 4y are supplied to the memory 5, respectively, and the digital video signals from the A / D converter 2 are supplied to the memory 5 by these address signals. Write.

Reference numeral 14 denotes a read clock generating circuit which synchronizes with the reference horizontal synchronizing signal based on the reference horizontal and vertical synchronizing signals from the input terminals T2 and T3.
858 times in the PAL system and 864 times in the PAL system, that is, 13.
5 MHz in-line address increment clock pulse R
0, synchronized with the reference horizontal synchronization signal, and generates a clock pulse Rc having the same frequency and a duty of 50%.

The read clock pulse R0 from the read clock generating circuit 14 is supplied to the DA converter 16 and a read line address counter 15x to be described later, and the clock pulse Rc is supplied to the read line address counter 15x and a read line address to be described later. The signal is supplied to the counter 15y and a frequency dividing circuit 13 described later. The in-read line address counter 15x reads the read clock R0 from the read clock generation circuit 14.
, And is reset by the clock pulse Rc to generate an in-line address signal. The read line address counter counts the clock pulse Rc from the read clock generation circuit 14, and the reference vertical synchronization signal from the input terminal T3. To generate a line address signal.

The address signals from the read line address counter 15x and the read line address counter 15y are supplied to the memory 5, and these address signals are used to read the digital reproduced video signal (luminance signal or color difference) stored in the memory 5. Signal) is read. The digital reproduction video signal read from the memory 5 is converted into an analog signal reproduction video signal by the DA converter 16 and supplied to the output terminal T4.

The read-side frequency dividing circuit 13 applies the clock pulse Rc from the read clock generating circuit 14 to each one.
/ 、, 及 び and ８, and each divided output R
2, R4, and R8 are supplied as data to the latch circuits 8 and 9 on the write side, and the 1/2 frequency output R2 of the frequency divider 13 and the frequency output R2i of the opposite phase are latched on the read side. The latch pulses are supplied to the circuits 10 and 11, respectively.

Then, the write-side latch circuits 8 and 9
And three divided outputs R from the frequency divider 13 on the read side.
2, R4 and R8 are frequency divider circuits 12 on the write side, which will be described later.
Are latched with the positive-phase and negative-phase frequency-divided outputs W2 and W2i, respectively, and the respective latch outputs Rd and Rdi are supplied to the write-side coincidence detection circuit 6, respectively.

The coincidence detection circuit 6 generates a coincidence detection signal Wp during a period in which the latch output Rd from the latch circuit 8 and the latch output Rdi from the latch circuit 9 coincide with each other. Each is supplied to a double speed detection circuit 100 described later.

During the period when the latch outputs Rd and Rdi from the latch circuits 8 and 9 match, the supply of the line address stepping clock pulse Wc from the write clock generation circuit 3 to the write address counter 4y is prohibited. The writing of the digital reproduction video signal from the A / D converter 2 is performed in the memory 5 for one line.

The write-side frequency dividing circuit 12 divides the clock pulse Wc from the write clock generating circuit 3 by half.
And the divided outputs W2 and W4 are supplied as data to the read-side latch circuits 10 and 11, respectively, and the divided output W2 of 1/2 and the frequency of the opposite phase are outputted. The output W2i is supplied as latch pulses to the write-side latch circuits 8 and 9, respectively.

Then, the read-side latch circuits 10 and 1
1, two frequency-divided outputs W2 and W4 from the write-side frequency divider 12 are latched by positive-phase and negative-phase frequency-divided outputs R2 and R2i from the read-side frequency divider 13, respectively. The outputs Wd and Wdi are supplied to the coincidence detection circuit 7, respectively.

The coincidence detection circuit 7 has a latch output Wd from the latch circuit 10 and a latch output Wd from the latch circuit 11.
During a period in which di coincides with each other, a coincidence detection signal Rp is generated and supplied to the read line address counter 15y and a double speed detection circuit 100 described later via the switch S2.

During the period when the latch outputs Wd and Wdi from the latch circuits 10 and 11 coincide with each other, the supply of the clock pulse Rc from the read clock generation circuit 14 to the read address counter 15y is prohibited, and the memory 5
Is read twice for one line.

The above-described coincidence detection signals Wp and Rp
Depends on the playback direction (FWD / REV). The coincidence detection signal Wp generates a pulse at the time of reproduction lower than the normal reproduction speed and at the time of REV (REVERSE) reproduction,
It does not occur during playback faster than normal playback speed. On the other hand, the coincidence detection signal Rp is the reverse of the above.

The double speed detection circuit 100 counts the number of the coincidence detection signals Wp and Rp from the coincidence detection circuits 6 and 7, detects the running speed of the tape based on the value obtained by the counting, and converts the result to the double speed. Determination signals Bi and C
i is supplied to the switches S1 and S2, respectively, to control the opening and closing of the switches S1 and S2.

For example, in the case of judging that the reproduction speed is equal to or higher than the REV triple speed reproduction, the following is performed. That is, since the REV triple speed reproduction has a difference of 4 times speed from the normal reproduction, the pulse of the coincidence detection signal Wp is NTSC (H alignment 4.5) × 4 = 18, PAL system. In (H
Alignment (5.5) × 5 = 22 occurs.

Therefore, within one vertical cycle, the coincidence detection signal W
When p (NTSC system) or 22 (PAL system) can be counted, RE is determined as a double speed determination signal Bi when the REV is twice or more. On the other hand, for example, when the determination is made at the FWD triple speed or higher, the following is performed.

That is, since the FWD 3 × speed reproduction has a difference of 2 × speed from the normal reproduction, the pulse of the coincidence detection signal Rp is NTSC (H alignment 4.5) × 2 = 9. , PAL method (5.5 for H alignment) × 2 = 11.

Therefore, within one vertical cycle, the coincidence detection signal R
When p can be counted by 9 (NTSC system) or 11 (PAL system), the determination of FWD triple speed or higher is output as a double speed determination signal Ci. Thus, when the speed is 3 times or more the speed of the REV, the double speed determination signal B supplied to the switch S1.
i becomes active, switch S1 is turned on, and F
When the speed is equal to or higher than the WD triple speed, the switch S2 is turned on.

Therefore, the switches S1 and S2 are turned off when the speed is less than the REV triple speed and the FWD triple speed, and the match detection signals Wp and Rp from the match detection circuits 6 and 7 are supplied to the write line address counter 4y and the read line address counter 15y. Is not supplied.

Next, the operation of the time axis correction device shown in FIG. 4 will be described with reference to FIGS.

FIG. 5 is a timing chart showing the thinning out of the writing of the digital reproduced video signal into the memory 5 when the reproduced video signal reproduced at the REV speed is supplied to the input terminal T1.

FIG. 5A shows a clock pulse Rc from the read clock generation circuit 14 supplied to the frequency divider 13 on the read side. FIGS. 5B, C and D show that the clock pulse Rc is 1 / 2, 1/4 and 1/8
The divided outputs R2, R4 and R8 are shown in FIG. FIG. 5E shows a clock pulse Wc from the write clock generating circuit 3, and FIG. 5F shows a frequency-divided output W obtained by dividing the clock pulse Wc by half in the frequency divider 12 on the write side.
FIG. 5G shows a 1/2 divided output W2 and a negative-phase divided output W2i.

か ら from the frequency divider 13 on the read side,
The 1/4 and 1/8 frequency-divided outputs R2, R4 and R8 are supplied to latch circuits 8 and 9, respectively, and the frequency-divided output W2 as a positive-phase and negative-phase latch pulse from the frequency-divider circuit 12 on the write side. , W2i, and are supplied to the coincidence detection circuit 6, respectively.

FIG. 5H shows the 1/2, 1/4 and 1/8 frequency-divided signals R2, R latched by the positive-phase frequency-divided output W2.
FIG. 5I shows the data contents of 3-bit latch outputs Rd of 4 and R8, and FIG. 5I shows 1/2, 1/4 and 1/8 frequency-divided outputs R2, R4 and R8 latched by the inverted-phase frequency-divided signal W2i. Shows the data contents of the 3-bit latch output Rdi.

When the two 3-bit latch outputs Rd and Rdi have the same value in the coincidence detection circuit 6, a coincidence detection signal Wp shown in FIG. 5J is generated, which is transmitted to the write line address counter 4y. Supplied. The write line address counter 4y inhibits the supply of the clock pulse Wc from the write clock generation circuit 3, and when the detection signal Wp from the coincidence detection circuit 6 is "1", the period immediately before the period becomes "1". The count value, that is, the line address is held, and when the detection signal Wp becomes "0", counting of the clock pulse Wc is started from the held count value (line address). Therefore, while the detection signal Wp is "1", the digital reproduction video signal supplied from the A / D converter 2 to the memory 5 is subtracted for one line.

In the example shown in FIG. 5, for example, at the time of REV shift reproduction in which the period τw of the horizontal synchronization signal of the reproduced video signal is τw: τr = 8: 10 with respect to the period τr of the reference horizontal synchronization signal (about -14 × speed) ) Indicates that one of the five lines is read twice during the period when the detection signal Wp is “1”.

Next, the operation at the time of FWD variable speed reproduction will be described with reference to FIG. FIG. 6 is a timing chart showing double reading when the reproduced video signal subjected to FWD reproduction is supplied to the input terminal T1, that is, double reading of the digital reproduced video signal written in the memory 5.

FIG. 6A shows a clock pulse Wc supplied from the write clock generating circuit 3 to be supplied to the frequency dividing circuit 12. FIGS. 6B and 6C show that the clock pulse Wc is １ ／ and 1/2 in the frequency dividing circuit 12 on the writing side. The frequency-divided outputs W2 and W4 obtained by dividing the frequency by 1/4 are shown. FIG. 6D shows a clock pulse Rc from the read clock generation circuit 14, and FIG.
E indicates that the clock pulse Rc is the frequency divider 1 on the read side.
FIG. 6F shows the divided output R2 of 1/2, and the divided output W2i of the opposite phase.

The 出力 and 分 frequency-divided outputs W 2 and W 4 from the write-side frequency divider 12 are supplied to the read-side latch circuits 10 and 11, respectively. The latched signals are latched by frequency-divided outputs R2 and R2i as phase-phase and antiphase latch pulses, respectively, and the latch outputs Wd and Wdi are supplied to the coincidence detection circuit 7, respectively.

FIG. 6G shows the data contents of the 2-bit latched output Wd of 1/2 and 1/4 divided outputs W2 and W4 which are latched by the positive-phase divided output R2, and FIG. 1/2 and 1 latched by the cycle output R2i
/ 2 divided output W2 and W4 2-bit latch output W
Indicates the data content of di.

In the coincidence detection circuit 7, these two
FIG. 6 when two latch outputs Wd and Wdi indicate the same value.
A coincidence detection signal Rp indicated by I is generated and supplied to the read line address counter 15y. The read line address counter 15y inhibits the supply of the read clock pulse Rc from the read clock generation circuit 14, and when the detection signal Rp from the coincidence detection circuit 7 is "1", the period becomes "1". The count value immediately before, that is, the line address is held, and when the detection signal Rp becomes “0”, counting of the clock pulse Rc is started from the held count value (line address). Therefore, the digital reproduction video signal stored in the memory 5 is read twice for one line while the detection signal Rp is "1".

In the example shown in FIG. 65, for example, at the time of FWD variable speed reproduction (about 11 times speed), the period τw of the horizontal synchronization signal of the reproduced video signal becomes τw: τr = 12: 10 with respect to the period τr of the reference horizontal synchronization signal. Indicates that one of the five lines is read twice during the period when the detection signal Rp is “1”.

[0052]

FIGS. 4 to 6 show an embodiment of the present invention.
The above-described time axis correction device described with reference to the above has a problem. Hereinafter, this problem will be described with reference to FIGS.

In describing the problems of the above-described time axis correction device with reference to FIGS. 7 to 9, for convenience, the drum diameter of the VTR to be reproduced is about 10% larger than the drum diameter of the VTR at the time of recording. At the same tape running speed as during recording, the period τ of the horizontal synchronizing signal in the reproduced video signal reproduced from the inclined track of the magnetic tape by the rotating magnetic head.
w = A is 1 compared to the period τr = B of the reference horizontal synchronization signal.
It is assumed that the contraction is 0% (A: B = 9: 10).

FIG. 7 shows that the period τw of the clock pulse Wc from the write clock generation circuit 3 is reduced by 10%, although the reproduction is performed at the same tape running speed as during recording, so that τw: τr = 9 : 10, indicating that one of the 10 lines is thinned out during the period when the detection signal Wp is “1”. The reproduced image at this time is an image contracted by 10% in the vertical direction.

FIG. 8 shows REV at the same tape running speed as in FIG.
This shows a case where variable speed reproduction is performed. In this case, since the period τw of the clock pulse Wc from the write clock generation circuit 3 is reduced by 10%, τw: τr = 7.2: 10. The ratio of Wp is higher than in the case of FIG.

FIG. 9 shows the FWD at the same tape running speed as in FIG.
This shows a case where variable-speed reproduction is being performed. In this case, since the period of the clock pulse Wc from the write clock generation circuit 3 is reduced by 10%, τw: τr = 10.8: 10, which allows double reading. The ratio of the detection signal Rp is smaller than in the case of FIG.

As described above, in the time axis correction circuit described above, when reproduction is performed by the rotating magnetic head having a drum diameter larger than the drum diameter at the time of recording, correct detection signals Wp and Rp for the tape traveling speed cannot be obtained. In addition, the reproduction speed detection result is also shifted to the REV side, and there is a disadvantage that good reproduction cannot be performed.

For example, in a digital VTR of the digital beta cam system developed recently, when a magnetic tape recorded by the analog beta cam system can be reproduced, the time axis correcting device used in the analog beta cam system VTR is used. Betacam VTR
The demand for use in such applications naturally arises.

In this case, since there is a time axis correcting device, the circuit system for the above-mentioned thinning-out section is cut off, and if the vertical synchronizing signal and the horizontal synchronizing signal can be obtained, there is no problem during normal reproduction. The cycle of the horizontal synchronization signal on the reading side and the cycle of the horizontal synchronization signal on the writing side are compared with each other, and the detection of the playback speed is deviated. However, the detection result of the reproduction speed is the REV shift reproduction, and the reproduced image is deteriorated as described above.

The present invention has been made in view of the foregoing, and has been made in consideration of the traveling speed and traveling direction of a magnetic tape on which a reproduced video signal recorded by a rotary magnetic head having a diameter larger than the diameter of the drum at the time of recording is recorded. Regardless, it is an object of the present invention to propose a time axis correction apparatus capable of obtaining an extremely high quality reproduced image with a simple circuit configuration.

[0061]

According to the present invention, a reproduced video signal reproduced by a rotary magnetic head from an inclined track of a magnetic tape running at an arbitrary tape running speed with respect to a tape running speed during recording is stored. The memory 5, an in-line address counter 4 x for generating an in-line address signal for the memory 5, a write line address counter 4 y for generating a write line address signal, and a horizontal synchronization signal separated from the reproduced video signal. A write clock signal generating circuit 3 for generating a write line address stepping clock signal and a write line address stepping clock and supplying them to the write line address counter 4x and the write line address counter 4y, respectively, and reading from the memory 5 In-line ad Read line address counter 15y for generating a read in-line address counter 15x and the read line address signal for generating the scan signals
And a read-out line address counter 15x and a read-out line address counter 15y which generate a read-in-line address increment clock signal and a read-out line address increment clock signal respectively synchronized with the reference horizontal synchronizing signal. A time axis correction device having a clock signal generation circuit and a detection means for detecting that one of the periodic signals synchronized with the reproduced horizontal synchronizing signal and the reference horizontal synchronizing signal includes one single periodic period; 8, 9, 18, 21 and 7, 10, 11, 2
0, 22 and detection means 6, 8, 9, 18, 21 and 7, 10, 11, based on outputs from the write clock signal generation circuit 3 and the read clock signal generation circuit 14.
Pseudo line address increment clock signal generating means 17 and 19 for supplying pseudo line address increment clock signals to 20, 20 and detecting means 6, 8, 9, 18, 21 and 7, 10, 11, 20, And a tape running speed detecting means 100 for detecting a tape running speed based on a detection signal from the detecting means 22. The detecting means 6, 8, 9, 18, 21 and 7, 10, 11, 20, 22 provide a reproduction horizontal speed. When it is detected that a single cycle period of one of the periodic signals is included in a single cycle period of the other of the synchronization signals synchronized with the synchronization signal and the reference synchronization signal, respectively, Line address counter 4 of a line address step-up clock signal related to a horizontal synchronization signal synchronized with the periodic signal
The supply of y and 15y is performed based on a detection signal from the tape running speed detecting means 100.

Further, according to the present invention, the pseudo line address increment clock signal generating means 17 and 19 are provided based on the write line address increment clock signal from the write clock signal generation circuit 3. A pseudo write line address increment clock signal generating means 17 for obtaining a read clock signal, and a pseudo read line address increment clock signal for obtaining a read line address increment clock signal from the read clock signal generation circuit 14. And a read line address increment clock signal generating means 19.

Further, in the present invention, the pseudo line address increment clock signal is expanded or compressed based on the drum diameter ratio at the time of recording and at the time of reproduction.

Further, according to the present invention, the detecting means 6,
8, 9, 18, 21 and 7, 10, 11, 20, 22
Has frequency dividing means 18 and 20 for dividing at least the pseudo line address incremental clock signal from the pseudo line address incremental clock signal generating means 17 and 19.

[0065]

According to the configuration of the present invention described above, the pseudo line address increment clock signal from the pseudo line address increment clock signal generating means 17 and 19 is detected by the detection means 6,
8, 9, 18, 21 and 7, 10, 11, 20, 22
The detection means 6, 8, 9, 18, 21 and 7, 10, 11, 20, 22 provide a single periodic signal of one of the synchronization signals synchronized with the reproduced horizontal synchronization signal and the reference synchronization signal. When it is detected that a single cycle period of the other periodic signal is included in one cycle period, a line address related to a horizontal synchronization signal synchronized with the other periodic signal is a line address of a step-up clock signal. Counter 4y
15y is supplied based on a detection signal from the tape running speed detecting means 100.

Further, according to the configuration of the present invention described above,
A pseudo-write line address step-up clock signal is obtained by the pseudo-write line address step-up clock signal generation means 17 based on the write line address step-up clock signal from the write clock signal generation circuit 3, and the read clock signal generation circuit 14 The pseudo read line address increment clock signal is obtained by the pseudo read line address increment clock signal generating means 19 based on the read line address increment clock signal from the CPU.

Further, according to the configuration of the present invention described above,
The pseudo line address increment clock signal is expanded or compressed based on the drum diameter ratio at the time of recording and at the time of reproduction.

Further, according to the configuration of the present invention described above,
The pseudo line address increment clock signals from at least the pseudo line address increment clock signal generating units 17 and 19 are frequency-divided by the frequency dividing units 18 and 20.

[0069]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the time axis correcting apparatus according to the present invention will be described below in detail with reference to FIG.

In FIG. 1, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, reference numeral 17 denotes a pseudo-write line address step-up clock pulse generation circuit, which is based on the write clock pulse W0 from the write clock generation circuit 3 described in FIG. Wc 'is generated. This clock pulse W
c ′ is generated by the period τ of the horizontal synchronization signal in the reproduced video signal.
w and the horizontal synchronization signal from the clock generation circuit 17, ie,
The ratio of the period τw ′ of the clock pulse Wc is τw: τw ′
= A: B = 9: 10. This clock pulse Wc 'is supplied to the frequency dividing circuit 18.

The frequency dividing circuit 18 divides the frequency of the clock pulse Wc ′ from the pseudo-write line address incrementing clock pulse generating circuit 17 and divides the frequency of the clock pulse Wc ′ by １ ／.
/ 4 divided signals W4 'are obtained and supplied to the latch circuits 10 and 11, respectively.

A pseudo read line address increment clock pulse generator 19 is based on the read clock pulse R0 from the read clock generator 14 described with reference to FIG. Occurs. This clock pulse R
The ratio of the period τr of the reference horizontal synchronization signal and the period τr ′ of the horizontal synchronization signal from the clock generation circuit 19, that is, the period τr ′ of the clock pulse Rc, is calculated as follows: τr: τr ′ = B: A = 1
This is performed using a counter having a count number of 0: 9. This clock pulse Rc ′ is supplied to the frequency dividing circuit 20.

This frequency dividing circuit 20 divides the frequency of the clock pulse Rc ′ from the pseudo read line address incrementing clock pulse generating circuit 19 and divides the frequency of the clock pulse Rc ′ by １ ／.
/ 4 divided signal R4 'and 1/8 divided signal R8' are obtained,
These are supplied to latch circuits 8 and 9, respectively.

A frequency dividing circuit 21 corresponding to the frequency dividing circuit 12 in FIG. 4 divides the write line address stepping clock from the write clock generating circuit 3 by を to generate a frequency divided signal W2. Then, the frequency-divided signal W2 is supplied to the latch circuit 8, and a signal W2i having the opposite phase to the frequency-divided signal W2 is obtained. The signal W2i having the opposite phase is supplied to the latch circuit 9.

Similarly, reference numeral 22 denotes the frequency dividing circuit 13 in FIG.
, A read clock generation circuit 14
Clock for reading line address from memory
To obtain a frequency-divided signal R2, supply the frequency-divided signal R2 to the latch circuit 10, obtain a signal R2i having the opposite phase to the frequency-divided signal R2, and apply the signal R2i having the opposite phase to the latch circuit 11. To supply.

Next, with reference to FIGS. 2 and 3, for example, when the time axis correction apparatus of the present embodiment is applied to a digital beta cam VTR, operations of double reading during FWD shift reproduction and thinning out of writing during REV shift reproduction are performed. Will be described.

In FIGS. 2 and 3, FIGS.
The same reference numerals are given to the portions corresponding to and the detailed description will be omitted.

FIG. 2 shows REV at the same tape running speed as in FIG.
This shows a state in which variable speed reproduction is being performed, and the clock pulse Rc
Instead of the pseudo read line address increment clock pulse Rc ′ (FIG. 2B), the frequency division output R
2 ', R4' and R8 '(see FIGS. 2C, 2D and 2E) are supplied to the latch circuits 8 and 9 to generate the period τw of the clock pulse Wc and the clock pulse for step-up of the pseudo read line address. Rc 'period τr'
Is τw: τr ′ = 7.2: 10 × 9/10 = 8: 10, indicating that the detection signal Wp (see FIG. 2K) is detected at the same ratio as in FIG.

FIG. 3 shows the FWD at the same tape running speed as in FIG.
This shows a state in which variable-speed reproduction is being performed, and the clock pulse Wc
Instead of (FIG. 3A), the frequency-divided output W2 ′ is obtained from the pseudo-write line address increment clock pulse Wc ′ (FIG. 3B).
And W4 '(see FIGS. 3C and 3D) and supply them to the latch circuits 10 and 11, so that the period τw' of the pseudo write line address increment clock pulse Wc 'and the period τr of the clock pulse Rc become τw ': τ
r = 10.8 × 10/9: 10 = 12: 10, indicating that the detection signal Rp (see FIG. 3J) is detected at the same rate as in FIG.

That is, by using the pseudo write line address increment clock pulse Wc ′ and the pseudo read line address increment clock pulse Rc ′,
The detection signal Rp has the same ratio as that described in FIGS.
And Wp occur.

As a result, even if the diameter of the drum is larger than that at the time of recording, correct thinning corresponding to the running speed of the tape can be performed. In addition, accurate detection signals Rp and Wp
This makes it possible to detect the reproduction speed with high accuracy.

As described above, in this example, the pseudo write line address step-up clock pulse expanded by the drum diameter ratio is used, and the pseudo read line address step-up clock pulse compressed by the drum diameter ratio is used. Therefore, when reproduction is performed with a rotating magnetic head having a drum diameter larger than the drum diameter at the time of recording, correct detection signals Wp and Rp for the tape running speed can be obtained, and the reproduction speed detection result is also shifted to the REV side. Instead, extremely high-quality reproduced images can be obtained with a simple circuit configuration.

Further, even when the drum diameter differs between recording and reproduction, such as when a tape on which a signal is recorded by an analog beta cam VTR is reproduced by a digital beta cam VTR, reproduction can be performed very well.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the spirit of the present invention.

[0086]

According to the present invention described above, the pseudo line address stepping clock signal from the pseudo line address stepping clock signal generating means is supplied to the detecting means, and the reproduced horizontal synchronizing signal and the reference When it is detected that a single cycle period of one periodic signal is included in a single cycle period of one of the synchronous signals synchronized with the synchronous signal, the synchronous signal is synchronized with the other periodic signal. The supply of the line address increment clock signal related to the horizontal synchronization signal to the line address counter is performed based on the detection signal from the tape traveling speed detection means, so that a very high quality reproduced image can be easily converted into a simple circuit. It can be obtained in a configuration.

Further, according to the present invention, the pseudo-write line address step-up clock signal is generated based on the write line address step-up clock signal from the write clock signal generation circuit. Means, and a pseudo read line address increment clock signal is obtained by the pseudo read line address increment clock signal generation means based on the read line address increment clock signal from the read clock signal generation circuit. In addition to the above effects,
It can be detected very accurately that a single cycle period of one periodic signal is included in a single cycle period of the other periodic signal among the synchronization signals synchronized with the reproduction horizontal synchronization signal and the reference synchronization signal, respectively. .

Further, in the above, according to the present invention, the pseudo line address stepping clock signal is expanded or compressed based on the drum diameter ratio at the time of recording and at the time of reproduction.
In addition to the effects described above, extremely high-quality reproduction is performed irrespective of the traveling speed and traveling direction of the magnetic tape on which the reproduced video signal recorded by the rotating magnetic head having a drum diameter larger than the drum diameter at the time of recording is recorded. Images can be obtained with a simple circuit configuration.

Further, according to the present invention, at least the pseudo line address increment clock signal from the pseudo line address increment clock signal generating means is divided by the frequency dividing means. In addition, it is possible to upgrade an old circuit to a new circuit without making a significant change in the circuit configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a time axis correction device of the present invention.

FIG. 2 is a timing chart for explaining one embodiment of a time axis correction device of the present invention.

FIG. 3 is a timing chart for explaining one embodiment of a time axis correction device of the present invention.

FIG. 4 is a configuration diagram showing an example of a conventional time axis correction device.

FIG. 5 is a timing chart for explaining an example of a conventional time axis correction device.

FIG. 6 is a timing chart for explaining an example of a conventional time axis correction device.

FIG. 7 is a timing chart for explaining an example of a conventional time axis correction device.

FIG. 8 is a timing chart for explaining an example of a conventional time axis correction device.

FIG. 9 is a timing chart for explaining an example of a conventional time axis correction device.

[Explanation of symbols]

Reference Signs List 3 Write clock generation circuit 4x Write line address counter 4y Write line address counter 5 Memory 6,7 Match detection circuit 8,9,10,11 Latch circuit 17 Pseudo write line address increment clock generation circuit 19 Pseudo read line address step Advance clock generation circuit 18, 20, 21, 22 Divider circuit 15x Readout line address counter 15y Readout line address counter 100 Double speed detection circuit

Claims (4)

(57) [Claims] 1. A memory for storing a reproduced video signal reproduced by a rotary magnetic head from an inclined track of a magnetic tape running at an arbitrary tape running speed with respect to a tape running speed during recording, and a write line for the memory. An in-line address counter for generating an in-line address signal, a write line address counter for generating a write line address signal, and an in-line address stepping clock signal and a write signal synchronized with a horizontal synchronization signal separated from the reproduced video signal. A write clock signal generating circuit for generating a line address stepping clock and supplying them to the write line address counter and the write line address counter, respectively; and a read line for generating a read line address signal for the memory. An address counter and a read line address counter for generating a read line address signal; and a read line address increment clock signal and a read line address increment clock signal synchronized with the reference horizontal synchronizing signal, respectively. A time axis correction device having an in-line address counter and a read clock signal generation circuit for supplying the read line address counter, wherein one of the periodic signals synchronized with the reproduction horizontal synchronization signal and the reference horizontal synchronization signal is used. Detecting means for detecting that one cycle period is included; and a pseudo-supply circuit for supplying a pseudo-line-address stepping clock signal to the detecting means based on an output from the write clock signal generating circuit and an output from the read clock signal generating circuit. Line address increment A clock signal generating unit; and a tape running speed detecting unit that detects the tape running speed based on the detection signal from the detecting unit. The detecting unit outputs the tape horizontal speed signal and the reference synchronizing signal respectively. When it is detected that a single cycle period of one periodic signal of the synchronized synchronization signals includes a single cycle period of the other periodic signal, a horizontal synchronization signal synchronized with the other periodic signal is detected. A time axis correction device for supplying the line address increment clock signal to the line address counter based on a detection signal from the tape running speed detection means. 2. The pseudo-line address step-up clock signal generation means, comprising: a pseudo-write line address step-up clock signal from the write clock signal generation circuit; A line address increment clock signal generating means, and a pseudo read line address increment clock signal for obtaining a pseudo read line address increment clock signal based on the read line address increment clock signal from the read clock signal generation circuit. 2. The time axis correction device according to claim 1, wherein the time axis correction device comprises a generation unit. 3. The time axis correction device according to claim 1, wherein the pseudo line address step-up clock signal is expanded or compressed based on a drum diameter ratio at the time of recording and at the time of reproduction. 4. The apparatus according to claim 1, wherein said detecting means includes frequency dividing means for dividing at least said pseudo line address increment clock signal from said pseudo line address increment clock signal generating means. The time axis correction device as described.