JPS5921113B2 - Video signal recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION As shown in FIG. 1, when a video signal is recorded on a magnetic tape by forming diagonal tracks Tv, an absolute address is given to each frame of the video signal, and this absolute address is code and extend the code signal in the longitudinal direction of the tape.
That is, recording is performed on an auxiliary track TQ parallel to the audio track TA and the control track To.

Note that the figure shows a case where one track Tv is formed for one field of the video signal. A specific example of this is SMPTE time code.

As shown in Figure 2, one frame has 80 bits, so the bit frequency is 2.4kHz, and of these 80 bits, 32 bits are used as a time code, and 32 bits are used for the user. The 16 bits are used as empty bits, and the 16 bits are used as a sync word.

A 32-bit time code consists of a frame code, a second code, a minute code, and an hour code, each of which indicates what hour, minute, second, and frame number. The data is divided into two parts, with four user bits inserted between each part.

The 16-bit sync word indicates whether the tape is running in the forward direction and therefore this SMPTE time code signal is read in the direction indicated by arrow F, or the tape is running in the reverse direction and therefore this SMPTE time code signal is read out in the direction indicated by arrow F. The state is such that it is possible to identify whether the signal is to be read out in the direction indicated by arrow R, and the time code can be read out without error when traveling in any direction.

Note that this code signal is a so-called bi-phase signal in which the information of "1" and "O" is expressed by different inverted phases as shown in the figure.

In this way, the track TQ extending in the longitudinal direction of the tape
It is convenient to record a signal indicating the absolute address of each frame of the video signal when editing the tape.

On the other hand, as shown with diagonal lines in FIG. 3, it is also conceivable to record a signal 50 indicating the absolute address of the track Tv as a digital signal in the track Tv of the video signal.

D In this case, this signal 50 is inserted and recorded in both the odd and even fields of each respective frame, as shown in the figure.

Specifically, as shown with diagonal lines in FIG.
It is inserted into the video section after the burst signal SB in a predetermined horizontal section excluding the vertical synchronizing pulse section 95 Tvp and the equalization pulse section TEp within the vertical retrace period.

This code signal is, for example, 80 bits like the SMPTE time code signal in FIG. 2, and its bit frequency F
For example, B is the color subcarrier frequency F8O (=3.58M11z
), for example, i.

If the horizontal frequency is FH and the vertical frequency is Fv, there is a relationship as follows.Therefore, when , then 80 bits easily fit within the video section of the horizontal section.

Of the 80 bits, 32 bits are time code and 3
2 bits are for the user and 16 bits are for the sync word.

The arrangement relationship between time code and user bits is shown in Figure 2.
It may be the same as that of the MPTE time code signal, and the same time code is inserted in the odd and even fields of the same frame. The sync word also comes at the beginning, that is, immediately after the burst signal SB. The position of the beginning of this sync word, ie, the beginning position of the code signal, is always set at a fixed time T8 from the horizontal synchronizing pulse PH. In addition, in this code signal, “1
”, [0] may be expressed at different levels as shown in the figure. For example, “O” is at the pedestal level, and “1” is at the level of 30 REunits or higher. It can be made such that Track TQ extending in the longitudinal direction of the tape
There is an inconvenience that the SMPTE time code signal recorded in the SMPTE time code signal cannot be read out in the case of slot 1 or still motion playback, but if the above code signal SO recorded in the track Tv of the video signal It has the advantage that it can be read out even during slot or still motion playback.

By the way, when reading this code signal SO, a clock pulse of a constant frequency is formed based on the horizontal synchronizing pulse PH and the sync word.

However, if there is jitter or skew, or if the horizontal frequency changes during slot or still motion reproduction, the bit frequency FB will change.

Therefore, if the period of the clock pulse is constant, the position of the clock pulse with respect to the corresponding bit will gradually shift, and it will no longer be possible to read out all 80 bits accurately. In consideration of this point, it is also possible to construct the clock pulse interval so that it changes in accordance with the variation in the bit interval, but this would result in a significantly more complicated configuration.

In view of this point, the present invention employs a simple structure and devises a code signal to be recorded so that all bits can be read out accurately even if the bit interval changes. In the present invention, as shown in FIG.
A synchronizing signal Ps having a higher level than the code signal is inserted into the code signal at predetermined bit intervals, for example every four bits, and is recorded.

In this case, the sync word occupying the 16 consecutive bits described above is not needed.

The width of the synchronization signal Ps is one time code or user bit.
Make it equal to the width of bits. Therefore, when inserting the synchronization signal Ps every 4 bits, the total number of synchronization signals Ps is 16.
Therefore, the total number of bits of the code signal is 80 bits including the synchronization signal Ps. Note that the position of the first synchronization signal Ps is the horizontal synchronization pulse P.

to a certain time T. In this way, when reading, if the clock pulse generation circuit is controlled by this synchronization signal P8 so that the oscillation phase of the clock pulse is synchronized with this synchronization signal Ps every 5 bits, the interval between bits can be reduced. Even if the bits fluctuate, the deviation between the position of each bit and the position of the clock pulse relative thereto remains within a certain range, and all bits can be read out accurately.

FIG. 6 shows an example of a circuit for forming a code signal including the above-mentioned synchronization signal Ps and inserting it into a video signal for recording.

1 is an input terminal for a video signal to be recorded, and the video signal is supplied to a synthesizer 2.

The video signal is also supplied to a synchronization signal separation circuit 3 to extract a composite synchronization signal including an equalization pulse, which is supplied to a frame pulse formation circuit 4 to form a frame pulse, which is supplied to a time counter 5 to calculate the time. The output of the counter 5 is supplied to the buffer memory 16 as a time code. Further, user bits from the user bit generation circuit 10 are supplied to the buffer memory 16.

On the other hand, the composite synchronization signal from the synchronization signal separation circuit 3 is supplied to the monostable multivibrator 12 to obtain horizontal synchronization pulses excluding the equalization pulse, and the signal from the variable frequency oscillator 13 is supplied to the frequency divider 14. hand? The horizontal synchronizing pulse and the frequency-divided signal from the frequency divider 14 are phase-compared in the phase comparator circuit 15, and the oscillator 13 is outputted by the comparison error voltage, so that the oscillation frequency of the oscillator 13 becomes 4 of FH.
The frequency is set to 55 times, that is, 2fs0, and the frequency of the frequency-divided signal from the frequency divider 14 is set to FH. Then, from another output terminal of the frequency divider 14, a clock pulse having a frequency of FB=ΣFsc synchronized with the horizontal synchronizing pulse is obtained. FIG. 7 shows a specific example of this frequency divider 14, which is composed of a 29-decimal counter 16 and a NAND circuit 17. A pulse with a frequency of 2fs0 from the oscillator 13 is supplied to the counter 16, and the frequency divider 14 is shown in FIG. As shown in the figure, when this is frequency-divided and the outputs of the lower 3 bits and upper 3 bits become "1", that is, when 455 pulses with a frequency of 2 fsc are counted, the output of the NAND circuit 17 becomes "O". The counter 16 is reset.

Therefore, the output of the second bit counting from the lowest bit of the counter 16 becomes a pulse with a frequency of FB=ΣFsc. This FB
A pulse with a frequency of is supplied to the gate circuit 18, while
The composite synchronization signal from the synchronization signal separation circuit 3 is supplied to the vertical synchronization signal separation circuit 20 to extract the vertical synchronization signal, and this and the horizontal synchronization pulse are supplied to the gate pulse forming circuit 21 to obtain the gate pulse. is supplied to the gate circuit 18, and pulses at the frequency of FB are taken out in a video section of a determined horizontal section within the vertical retrace period.

This extracted pulse is further supplied to the gate circuit 22, and on the other hand, the pulse indicating one horizontal interval into which the code signal obtained from the gate pulse forming circuit 21 is inserted and the output of the appropriate bead of the frequency divider 14 are synchronized. The signal is supplied to the formation circuit 23 to form the above-mentioned every 4-bit synchronization signal Ps, which is supplied to the gate circuit 22 and output to the gate circuit 22.
A pulse of the frequency of FB is extracted in a section other than the synchronization signal Ps.

The extracted pulses are then supplied to the buffer memory 16, where the time code and user bits are extracted in the arrangement relationship shown in FIG.
4. On the other hand, the synchronization signal Ps from the synchronization signal forming circuit 23 is supplied to the synthesizer 24, and is synthesized at a level twice the level of "1" of the time code.

Then, the code signal including the synchronization signal Ps as shown in FIG. As shown in the figure, it is recorded as a diagonal track Tv. FIG. 8 shows the inserted code signal SO from the video signal recorded on the track Tv.
This is an example of a circuit that reads out and displays the absolute address. 5
Reference numeral 1 denotes an input terminal for a video signal reproduced from the track T by a rotating magnetic head, and this reproduced video signal is sent to a clamp circuit 5.
2.

The reproduced video signal is also supplied to a synchronization signal separation circuit 53 to extract a composite synchronization signal, which is supplied to a monostable multivibrator 54 to obtain horizontal synchronization pulses excluding equalization pulses, which are sent to a phase synchronization circuit called a PLL 55. A clamp pulse synchronized with the horizontal synchronizing pulse is obtained, and this is supplied to the clamp circuit 52 to pedestally clamp the reproduced video signal. This clamped reproduced video signal is supplied to the gate circuit 58, while the composite synchronization signal from the synchronization signal separation circuit 53 is supplied to the vertical synchronization signal separation circuit 56 to extract the vertical synchronization signal, and the monostable multivibrator 54 The horizontal synchronizing pulse and this vertical synchronizing signal are supplied to the gate pulse forming circuit 57, and the gate pulse obtained from this is supplied to the gate circuit 58, which generates the synchronizing signal inserted in the above-described predetermined horizontal interval. Code signal SO (10th
Figure A) is retrieved.

This code signal Sc is supplied to a level comparison circuit 61 and compared with a voltage V, which is higher than the pedestal level and lower than the "1" level in the above-mentioned time code and user bit. Pulse P becomes “1” when the user bit is “1”
E (FIG. 10E) is obtained and supplied to a shift register 62 consisting of 5 bits. The code signal SO is also supplied to another level comparison circuit 63, where it is compared with a voltage 2 which is higher than the level of "1" in the time code and user bit and lower than the level of the synchronization signal SO, and is compared with the voltage 2 at the synchronization signal Sc. A pulse PB (FIG. 10B) which is "1" is obtained.

This pulse PB is supplied to a monostable multivibrator 64, and a pulse PO (FIG. C) which rises after a certain period of time from the rise of pulse PB is obtained, and this is supplied to a clock pulse generation circuit 65. The clock pulse generation circuit 65 is composed of, for example, an oscillator from which an oscillation signal of the fundamental frequency is obtained and a counter that divides the frequency of the oscillation signal, and the clock pulse PD (FIG. 10D) of the above-mentioned bit frequency FB is obtained from the counter. It was done like this,
Then, the pulse PO is supplied to this counter as a set pulse, and synchronous control is performed so that the rising edge of the pulse PO becomes the rising edge of the clock pulse PD. This clock pulse PD is then supplied to the shift register 62, and at the time of its rising edge, the level comparison circuit 6
1 pulse Pp. is sup-z-ringed and written to the shift register 62. The pulse PB from the level comparison circuit 63 is supplied to a buffer memory 66, and this pulse PB is supplied to a hexadecimal counter 67 which is reset by the horizontal synchronizing pulse from the monostable multivibrator 54.
The output of the counter 67 is supplied to the timing pulse generation circuit 68, and the timing pulse obtained from this is supplied to the memory 66. The 4-bit output excluding the output corresponding to Ps is transferred and written to a different address in the memory 66 for each synchronizing signal Ps, and when all writing is completed, the output is displayed on the display device 69. is supplied to The display device 69 displays the absolute address of the track Tv currently being reproduced by the rotating magnetic head, that is, the hour, minute, second, and number frame of the track Tv.

In this case, even if the width of one bit of the code signal SO varies as described above, the phase of the clock pulse PD is synchronized every 5 bits with the pulse PO based on the synchronization signal Ps. Therefore, the rising edge of the clock pulse PD always falls within the width of the corresponding bit, and no erroneous reading occurs.

As described above, according to the present invention, since a synchronization signal with a level that can be separated from the code signal is inserted into the code signal at predetermined intervals and recorded, this synchronization signal is used for reading. By correcting the phase of the clock at predetermined bit intervals, the bit frequency of the code signal changes due to jitter or skew, or when the horizontal frequency changes in the case of slot or still motion playback. code signals can be read correctly even if The present invention can also be applied to the case of recording on a track TQ extending in the longitudinal direction of a magnetic tape, such as an SMPTE time code signal, and the same effect can be obtained in this case as well.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the recording pattern of a tape on which an SMPTE time code signal is recorded, FIG. 2 is a diagram showing the state of the SMPTE time code signal, and FIG. FIG. 4 is a diagram showing an example of a state in which a signal indicating an absolute address is inserted into a video signal, and FIG. 5 is a diagram showing an example of a recording pattern in which a signal indicating an absolute address is inserted into a video signal. 6 is a diagram showing the state of an example of a signal indicating an address. FIG. 6 is a system diagram of an example of a circuit for forming and inserting a signal indicating an absolute address. FIG. Figure 8 is a system diagram of an example of a circuit for reading a signal indicating an absolute address, Figures 9 and 1
Figure 0 is a waveform diagram for explanation of each.〇TQ is S
Recorded track of MPTE time code signal, Tv
is a recording track of a video signal, Sc is a code signal indicating its absolute address, and P8 is a synchronization signal inserted therein.

Claims (1)

[Claims] 1. A video signal is recorded on a magnetic tape by forming one diagonal track for each field or frame, and a signal indicating the absolute address of this diagonal track is used as a digital signal to record a video signal at a predetermined location in the diagonal track. or at a position corresponding to the diagonal track of a track formed extending in the longitudinal direction of the magnetic tape, and a synchronization signal having a higher level than this signal is inserted into the digital signal at predetermined bit intervals. A recording device for video signals.