JP3134601B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell type semiconductor integrated circuit having a plurality of standard cell rows formed by arranging a plurality of standard cells on a semiconductor chip. The present invention relates to a semiconductor integrated circuit having a cell structure that can be formed in a flexible manner.

[0002]

2. Description of the Related Art FIGS. 5 to 7 are explanatory views showing the configuration of a conventional semiconductor integrated circuit. FIG. 5 is a plan view showing a conventional chip layout. In FIG. 5, a standard cell row in which standard cells having predetermined functions such as a gate circuit and a flip-flop are arranged in an internal region on a semiconductor chip 501 is shown. 502 are arranged in a plurality of columns with the wiring region 503 interposed therebetween.
Reference numeral 504 denotes an I / O peripheral cell.

FIG. 7 is an explanatory view showing the configuration of a standard cell having a predetermined function. In the figure, reference numeral 701 denotes a cell outer frame, which is a reference for the arrangement of the standard cell 702. The internal circuit of the standard cell includes a power line 703, a diffusion layer region 704, a gate electrode 705, a contact 706, an aluminum wiring 707, and the like. Data constituting a circuit element exists outside the cell outer frame 701. do not do.

When such a standard cell 702 is disposed on a chip, the cell outer frame 701 of an adjacent standard cell is disposed online.
A standard cell row is formed. In addition, the power lines 703 are connected between adjacent standard cells, and all the power lines 703 of the standard cells included in one standard cell column are connected.

In the above layout design, usually,
In general, standard cells such as unnecessary gate circuits are designed by automatic placement and routing using a computer so as not to be placed. This is because there is no redundant part in the circuit diagram data on which the automatic placement and routing design is based.

[0006]

However, in the conventional semiconductor integrated circuit as described above, if a circuit change occurs after a layout design or a prototype of a chip, even if the circuit change is slight, the standard is changed. Since cells cannot be added or replaced, automatic placement and routing by a computer had to be restarted from the beginning. Furthermore, in this case, assets such as masks and diffused wafers that have already been developed cannot be used and must be discarded. These assets are wasted, development costs are increased, and new masks and the like are developed. There was a problem that the development period was greatly extended.

[0007] As means for solving the above-mentioned problems in the prior art, for example, a chip layout as shown in FIG. 6 is disclosed in Japanese Patent Laid-Open No. 3-62948.
In the figure, the configuration in which a standard cell row 502 is formed on a semiconductor chip 501 is the same as that shown in FIG. A feature of the semiconductor integrated circuit shown in FIG. 6 is that a circuit changing cell 601 is provided in the wiring region 503 or a dead space portion, and when a circuit is changed, only the wiring layer is corrected.

However, in the above-mentioned method, it is necessary to manually add a circuit change cell after the automatic placement and wiring design by a computer, which requires a new design period, and requires manual design. There is a problem that human intervention is apt to occur due to the intervention. In addition, the automatic layout design using the standard cell method originally aims at eliminating design work manually and improving design accuracy and shortening the development period. It is not a sufficient solution.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and in a standard cell type semiconductor integrated circuit having a plurality of standard cell columns, the number of development steps and the time required for adding a gate for circuit change are increased. It is another object of the present invention to reduce the cost of a chip by eliminating a decrease in accuracy due to the occurrence of an artificial design error.

[0010]

In order to achieve the above object, the present invention provides a standard cell type semiconductor integrated circuit having a plurality of standard cell columns formed by arranging a plurality of standard cells on a semiconductor chip. Wherein a plurality of circuit-changing element regions used for circuit change are provided on both sides in the arrangement direction of the standard cells, and the circuit-changing element regions can be arranged so as to overlap a part of the element regions in the adjacent standard cells. An object of the present invention is to provide a semiconductor integrated circuit having the same pattern.

[0011]

The semiconductor integrated circuit according to the present invention is provided with a circuit changing element region on both sides in the array direction of the standard cells, the circuit changing element region having no effect even if the pattern overlaps with the pattern in the adjacent cell. Has a cell structure automatically formed, thereby eliminating the step of manually adding a cell for circuit change.

[0012]

An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an explanatory diagram showing a configuration of a standard cell according to the present invention. In the figure, a standard cell 101 has the same configuration as a conventional standard cell, and a cell outer frame 102 is also set to a minimum area including an element region constituting a functional block. By arranging the cells in the same manner, it is possible to realize the same cell row configuration as that of the related art.

Reference numerals 103 and 104 denote gate regions for circuit change, which are formed outside the cell outside 102 on both sides of the standard cell 101. The formation positions of the circuit change gate regions 103 and 104 are in the direction in which the adjacent cells are arranged, that is, in the cell column direction. Also,
Element pattern 101a, 1 in standard cell 101
01b has the same pattern as the circuit changing gate regions 103 and 104, and has a configuration in which the overlapping portion is not deformed even if the adjacent cell is placed online with the cell outer frame 102. In addition, the circuit change gate region 103,
Numeral 104 is not connected as a circuit of a functional block, and includes therein a diffusion layer region 105, a gate region 106, and a power line 1 other than the aluminum wiring layer for internal wiring.
07 is formed.

FIG. 2 is an explanatory diagram showing each layout of a semiconductor chip formed by using the cell having the above-described configuration. FIG. 2A shows a case where the cell column is not divided.
Indicates a case with cell column division. In the figure, reference numeral 201 denotes a semiconductor chip; 202, an I / O peripheral cell;

In the above description, the cell forming region 203 in which a cell that can be used for circuit change is formed is always located at the cell end, and when a circuit change occurs, the transistor in this cell forming region 203 is replaced with a wiring layer. Change the connection and use it. Therefore, the circuit change gate region 10
Since the circuits 3 and 104 are independently secured during or after the chip layout, there is no need to add a design by hand. , 104
Can be formed at both ends of the cell row.

Further, by providing the circuit change gate region 103 in the vertical direction, it can be used for layout design by the standard cell laying method (Sea of cells).

FIG. 3 is an explanatory diagram showing a case where a cell row is formed using the standard cells 101. In the figure, 301 is an adjacent cell, 302 is a wiring connecting between cells, and 303 is a power line trunk.

In FIG. 3, when the cell outer frames 102 are arranged without gaps as in the conventional case to form a cell row, a new problem arises because the internal circuit in the cell outer frame 102 has the same configuration as the conventional one. Absent. Standard cell 101
Is formed so as to overlap with the cell outer frame 102 of the adjacent cell 301, but the pattern in the adjacent cell 301 is the same as that of the circuit changing gate region 103. Because of the pattern, no problem occurs due to the overlap.

On the other hand, the standard cell 101 at the end of the cell
Since the adjacent cell does not exist, the circuit changing gate region 104 formed in the above is formed as it is and can be used for circuit changing. This configuration is the same at the end opposite to the cell row.

FIG. 4 shows the standard cell 101.
It is explanatory drawing which shows the example of arrangement | positioning. In the figure, cell outer frame 1
02 and an adjacent cell are arranged online. The element pattern 101a in the standard cell 101 and the circuit change gate region 103 of the adjacent cell or the element pattern 10
1b and the gate region 104 for changing the circuit of the adjacent cell are formed by the diffusion region 105, the gate region 106 and the power line 10.
Since the element patterns 101a and 101b are the same as the basic patterns such as No. 7, the element patterns 101a and 101b are not deformed. In addition, although the element patterns 101a and 101b have a unique pattern such as a contact or an aluminum wiring other than the basic pattern, only the basic pattern is the same pattern, and the pattern in the cell changes even if the unique pattern exists. I will not do it.

Therefore, on both sides in the arrangement direction of the standard cells 101, the gate regions 103, 10 for circuit change which have no effect even if they overlap with the patterns in the adjacent cells.
4, the cells are arranged so as to overlap each other, and the circuit-changing gate regions are automatically formed only on both sides of the cell column. This eliminates the need for a step of manually adding the circuit-changing cells. Design errors can be avoided,
The development period is shortened, and the chip cost can be reduced.

[0022]

As described above, according to the semiconductor integrated circuit of the present invention, a circuit changing element region which is not affected even if it overlaps a pattern in an adjacent cell is provided on both sides in the arrangement direction of the standard cells. A cell structure in which the gate area for circuit change is automatically formed only at the end of the standard cell row eliminates the manual cell addition process for circuit change. It is possible to reduce the cost of the chip by eliminating the decrease in accuracy due to the increase in the number and the occurrence of an artificial design error.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration of a standard cell according to the present invention.

FIG. 2 shows a layout ((a)) of a semiconductor chip formed by using the cell shown in FIG.
(B) is an explanatory diagram showing a case where there is a cell column division.

FIG. 3 is an explanatory diagram showing a cell row constituted by using standard cells according to the present invention.

FIG. 4 is an explanatory diagram showing an example of the arrangement of standard cells according to the present invention.

FIG. 5 is a plan view showing a conventional chip layout.

FIG. 6 is a plan view showing a conventional chip layout.

FIG. 7 is an explanatory diagram showing a configuration of a conventional standard cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Standard cell 102 Cell outer frame 103 Circuit changing gate region 104 Circuit changing gate region 105 Diffusion layer region 106 Gate region 107 Power line 201 Semiconductor chip 202 I / O peripheral cell 203 Cell forming region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82

Claims (1)

(57) [Claims] 1. A standard cell type semiconductor integrated circuit having a plurality of standard cell rows formed by arranging a plurality of standard cells on a semiconductor chip, wherein both ends of each of the standard cells in the arrangement direction are used when a circuit is changed. A plurality of circuit-change element regions are provided, and the pattern of the circuit-change element region is the same as a pattern of a part of an element region arranged in an adjacent standard cell, and overlaps with a part of the element region. A semiconductor integrated circuit characterized in that the semiconductor integrated circuit can be arranged by mounting.