JP3135754B2 - Multilayer capacitor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor having an improved external terminal electrode structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art Multilayer chip capacitors are used as internal electrodes for obtaining capacitance by printing or spraying a metal powder paste on a thin dielectric sheet made by a doctor blade method or a printing method. It is made by stacking several to several tens of sheets, sintering the integrated one by crimping, and further forming external lead terminal electrodes on the end face, and each terminal of adjacent internal electrodes is a capacitor It is connected to one of external terminals formed on both end surfaces of the element and directly solderable.

Therefore, as can be seen in the longitudinal sectional view of FIG.
Is formed by firstly applying a base Ni layer 5 to the end surface of a chip body obtained by cutting the laminated body obtained by laminating and pressing the dielectric layer 2 and the internal electrode 3 and simultaneously sintering the chip.
A Cu plating layer 6 is applied on the i-layer 5 and then an intermediate N
Generally, an i plating layer 8 and a Pb / Sn plating layer 9 are applied.

[0004]

In the conventional structure of the external terminal electrodes, when the Ni plating layer and the Pb / Sn plating layer are applied after the formation of the Cu plating layer, the stress generated is transmitted to the chip element body and applied to the chip end face. There has been a problem that solder heat resistance is reduced, for example, cracks are formed on the surface of the formed external terminal electrode.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multilayer capacitor which reduces stress generated when an external terminal electrode is formed by plating, thereby preventing a decrease in solder heat resistance such as cracks on the surface of the external terminal electrode. It is to provide a manufacturing method thereof.

[0006]

As a result of research to achieve the above object, the present inventor has found that after performing Cu plating, the copper plating surface is oxidized using an oxidizing agent or the like to form an oxide film on the surface. As a result, the copper plating surface and the N
The inventors have found that if the adhesiveness at the interface with the i-plate layer is reduced, distortion due to the stress can be reduced, and as a result, deterioration of heat resistance can be prevented.

Accordingly, the present invention firstly provides an external terminal on both end faces of a chip body in which a plurality of internal electrodes opposed to each other with a dielectric material interposed therebetween and alternately connected to different external electrodes are laminated. As an electrode, a Ni layer, a Cu plating layer, an intermediate Ni plating layer and a Pb /
A multilayer capacitor provided with an Sn plating layer, wherein a copper oxide film is interposed between the Cu plating layer and a metal plating layer outside the Cu plating layer; A chip body is formed by laminating a plurality of internal electrodes in such a manner as to face each other with a dielectric sheet interposed therebetween and alternately connected to different external electrodes, and apply a Ni paste to an end face of the chip body. Then, simultaneous baking is performed to form a Ni layer serving as a base electrode of the external terminal electrode, and a Cu plating layer, an intermediate Ni plating layer, and a Pb / Sn plating layer are sequentially formed on the Ni layer to form an external terminal electrode. In the method for manufacturing a multilayer capacitor, an oxide film is formed on the surface of the Cu plating layer by using or heating an oxidizing agent, and then a metal plating layer on the outside thereof is sequentially formed. There is provided a production method.

[0008]

According to the method of the present invention, when forming the external terminal electrodes, a base Ni layer is applied to the end face of the chip body and then fired simultaneously, and a Cu plating layer is applied on the base Ni layer.
By forming an oxide film on the surface of the u-plated layer, the adhesiveness at the interface with the Ni-plated layer formed thereon is slightly reduced, and this is caused when the Ni-plated layer and the Pb / Sn-plated layer are formed. It is characterized in that it is difficult for the resulting stress to be transmitted to the chip element body, and has the effect of significantly improving the heat resistance of the external terminal electrodes of the completed multilayer capacitor.

It has been confirmed that the formation of the oxide film does not substantially affect the contact resistance between the inner and outer electrodes.

[0010]

FIG. 1 is a schematic vertical sectional view showing the internal structure of a multilayer capacitor produced in this embodiment. This will be described below with reference to this figure.

[0011] It has an F characteristic, a length of 3.2 mm and a width of 1.6 mm.
When a multilayer capacitor is manufactured, first, a laminated body in which opposing internal electrodes 3 are stacked via a dielectric layer 2 is obtained by a conventional method, and then cut into a predetermined size. The paste is applied and baked simultaneously to form a base Ni layer 5 as a base electrode of an external terminal, and then a copper plating layer 6 is applied on the Ni layer. Then, a copper oxide film 7 was formed. (1) The chip is immersed in a 20% hydrogen peroxide solution for 5 minutes to oxidize the surface. (2) The chip is heat-treated at a temperature of 150 ° C. in air to oxidize the surface.

After the oxide film 7 is formed, an electrolytic Ni plating layer 8 having a thickness of 2 μm and an electrolytic Pb / Sn plating layer 9 having a thickness of 4 μm are provided to provide the external terminal electrodes 4 to the chip element, and to laminate the chip element. Capacitor 1 was obtained.

Incidentally, regarding the heat resistance of the external terminal electrode,
The plated chip is immersed in solder at a temperature of 330 ± 5 ° C. for 3 ± 0.5 seconds so that both terminal electrodes of the chip are covered, and then left at room temperature. Was evaluated by observation.

The results for 50 samples are shown in Table 1.

[0015]

Comparative Example A multilayer capacitor was prepared in the same manner as in the example except that the step of forming an oxide film on the Cu plating surface was omitted, and the results of examining the heat resistance of the external terminal electrodes according to the procedure of the example were also used. The results are shown in Table 1.

[0016]

[Table 1]

As can be seen from the results shown in Table 1, the formation of the oxide film on the Cu-plated surface did not show any cracks on the surface and significantly improved the heat resistance.

[0018]

As described above, according to the method of the present invention, when plating for forming external terminal electrodes,
By forming an oxide film on the surface of the plating layer and then performing metal plating on the outside thereof, the stress generated by the conventional plating process can be reduced, and the heat resistance of the terminal electrode can be improved. In the multilayer capacitor of the present invention, the occurrence of cracks indicating deterioration of heat resistance in external terminals has been eliminated.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing an internal structure of a multilayer capacitor produced in an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing the internal structure of a conventional multilayer capacitor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 multilayer chip capacitor 2 dielectric layer 3 internal electrode 4 external terminal electrode 5 base Ni layer 6 Cu plating layer 7 Cu oxide film 8 intermediate Ni plating layer 9 Pb / Sn plating layer

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Yoshio Akimoto 6-16-20 Ueno, Taito-ku, Tokyo Taiyo Yuden Co., Ltd. (56) References JP 4-171912 (JP, A) JP 4-337616 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01G 4/00-4/40 H01G 13/00-13/06

Claims (2)

(57) [Claims] 1. An external terminal electrode is sequentially formed on both end surfaces of a chip body comprising a plurality of laminated internal electrodes facing each other across a dielectric sheet and alternately connected to different external electrodes as external terminal electrodes. A multilayer capacitor having a Ni layer serving as a Ni electrode, a Cu plating layer, an intermediate Ni plating layer, and a Pb / Sn plating layer, wherein copper is oxidized between the Cu plating layer and a metal plating layer outside the Cu plating layer. A multilayer capacitor characterized by having a film interposed. 2. A chip body is formed by laminating a plurality of internal electrodes in such a manner as to face each other across a dielectric sheet and to be alternately connected to different external electrodes, and to form a chip body on an end face of the chip body. The Ni paste is applied and simultaneously fired to form a Ni layer serving as a base electrode of the external terminal electrode, and a Cu plating layer, an intermediate Ni plating layer and a Pb / S
In the method for manufacturing a multilayer capacitor in which an n-plated layer is formed and used as an external terminal electrode, an oxide film is formed on the surface of the Cu-plated layer by using an oxidizing agent or by heating, and then a metal-plated layer on the outer side is sequentially formed. A method of manufacturing a multilayer capacitor.