JP3137082B2 - Apparatus and method for evaluating system performance with hierarchical resource contention - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for evaluating the performance of an information processing system, and more particularly to an apparatus and method suitable for use in evaluating the performance of a system having hierarchical resource contention.

[0002]

2. Description of the Related Art As an example of a conventional method for evaluating the performance of a system having resource contention, for example, Japanese Patent Laid-Open Publication No. Hei 6-274363 discloses that when a performance evaluation of a control computer system is performed, the computer system includes an application unit and an operating system. Section, a hardware section, and a system performance model of the control computer system is obtained by an application model, an operating system model, and a hardware model representing a performance table of each section, and a system simulation is performed using the system performance model. A method has been proposed in which the performance of a control computer system is evaluated by obtaining system performance data.

[0003] These application model, operating model, and hardware model are system performance models for evaluating system performance. A system simulation is performed using this system performance model.

In this simulation, the events that trigger the state transition processing of the execution unit of the application executed by the operating system are limited to some events, and the parallel priority processing of the execution unit is simulated as related to event driving. From this simulation, the operation state of the execution unit, which is system performance data, and the load on resources such as the CPU and disk memory are calculated and evaluated.

[0005] For example, the application model is defined by the distribution of use of resources of a process for realizing the function of the application, the parallel priority, and the activation at a fixed period.

In the operating model, the processing amount is defined for each event for controlling the state of a process.

Further, a hardware model is defined by a process execution time, data transfer time, and memory usage.

[0008] As a publication on a method for evaluating the performance of a system, published in the July, 1995, pages 370-375 and "August", pages 431-436 of the "Journal of the Operations Research Society of Japan". The commentary article titled “Performance evaluation of information processing system” (referred to as “Document 1”) is referred to.

[0009] The performance evaluation method described in the above document 1 is as follows.
The system includes a means for setting the system configuration, a means for inputting basic data called a single profile, a means for calculating a performance evaluation value from the data, and a means for displaying an evaluation result.

The conventional performance evaluation system having such a configuration operates as follows. First, the system configuration is input. Next, the hardware resource usage rate of each transaction when there is no competitive situation called a single profile is input, and the performance evaluation value is calculated based on the input and displayed. This method is called “single profile method”.
The analysis method used for calculating the performance evaluation value is described in K. Kant's "Introduction to ComputerSystem".
Performance Evaluation, 1992, McGraw-Hill In
c. Published) (referred to as “Reference 2”), Chapter 7, section 3, pages 235 to 240, and the like.

An example of an approximate calculation method for a system having hierarchical resource contention is described in Chapter 8 of the above-mentioned Document 2, page 263-
It is shown on page 311.

Further, "Proc. IEEE SMC 96, Beijing,
1996, pp. 3051-3062 "by I. Kino," Queueing networks with hierachical configura.
A paper entitled “tion of active and passive stations” (referred to as “Reference 3”) also describes a method of approximating the service rate of the upper layer from the throughput of the lower layer and performing a performance evaluation value using the service rate.

A method of applying this method and performing an approximate calculation of the upper layer as a Markov chain is described in "Two-Layer Queuing Network Model and Its Application" by Toshiyasu Kurasugi and Makoto Kiichi (New Performance Evaluation of Information and Communication Networks) Comprehensive research on law,
Pp. 222-233, January 1997) (referred to as “Reference 4”).

A method of approximating the upper layer as a product form solution is described in Toshiyasu Kurasugi and Makoto Kiichi, "Product Form Approximation of Two-Layer Queuing Network Model and Its Accuracy Verification" (New Performance Evaluation of Information and Communication Networks) Comprehensive Study on Law, No. 33
2 to 341 (January 1998).

[0015]

Here, hierarchical resource contention will be described using a computer system as an example. Generally, the processing executed by the computer system is called a “transaction”, and each transaction is represented by FIG.
In some cases, hardware resources are directly used as shown in FIG. When a plurality of transactions are executed simultaneously, a hardware resource conflict occurs.

However, there are cases where the number of transactions that can be executed at one time on the computer system is limited. In this case, before the contention of hardware resources, the contention for acquiring the right to execute the transaction (CPU time). , Memory reservation).

Further, as shown in FIG. 8, there is a case where a transaction is not configured to directly use hardware resources. This means that the transaction content is
The process is divided into several small processes, and the process for performing these processes is executed by being called from a transaction and executed.

In this case, if there is a restriction such as the number of processes that can be executed at a time is limited, not only hardware resource contention but also software resource contention for a process in the next higher hierarchy exists. Will do.

Such a system in which resource contention forms a hierarchical structure is called a "system having hierarchical resource contention".

The layer of software resources is called "upper layer", and the layer of hardware resources is called "lower layer". Reasons for limiting software resources are:
There are various factors such as restrictions on the amount of memory allocated and system specifications.

The conventional system performance evaluation technique described above has the following problems.

The first problem is that it is impossible to evaluate the performance of a system having a hierarchical resource conflict.

The reason is that neither the method using simulation nor the method using analysis means such as a single profile can model a hierarchical structure and cannot be applied to evaluation.

Also, Kant and Koki proposed in the literatures 2 and 4, etc., a method of approximating the service rate of the upper layer by the throughput of each process when the lower layer is approximated as an independent system. It does not disclose a specific method of realization.

The second problem is that although performance evaluation can be performed in theory, there is a possibility that the performance cannot be actually evaluated using a computer system.

The reason is that if all the state transitions taken by the system are to be followed, the number of states increases exponentially, so that resources such as memory required for calculation overflow or the amount of calculation is too large to execute. This may be the case.

A third problem is that it may not be possible to construct a model necessary for performing a performance evaluation.

The reason is that the system is too complicated,
This is because it is impossible to model and express it with parameters or the like, and it is often impossible to understand the behavior of the system and modeling is impossible.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a performance evaluation apparatus and method capable of evaluating system performance even when hierarchical resource contention exists. To provide.

It is another object of the present invention to provide a performance evaluation apparatus and method capable of reducing the amount of calculation required for performance evaluation and the required storage capacity to increase the processing speed and efficiency. .

Still another object of the present invention is to provide a performance evaluation apparatus and method capable of performing performance evaluation without strictly defining a model.

[0032]

According to the present invention, there is provided a system for evaluating performance of a system for achieving the above object, comprising basic data input means, and performance evaluation means for analyzing the data to calculate a performance evaluation value. It operates to display the performance evaluation result.

Further, according to the present invention, in the above apparatus, a lower layer performance evaluation calculating means for calculating a conditional performance evaluation result of the lower layer, and a processing speed of the upper layer for calculating a processing speed of the upper layer from the calculation result A calculating unit, an upper layer performance evaluation unit that calculates an upper layer performance evaluation value using the calculated processing speed, and a unit that summarizes the performance evaluation results of the upper layer and the lower layer and performs overall performance evaluation. And operates to display the performance evaluation result.

Further, according to the present invention, in the performance evaluation calculation of the lower layer of the above-mentioned apparatus, the performance evaluation of the lower layer is performed using the queuing theory.

Further, according to the present invention, in the performance evaluation calculation of the upper layer of the above-mentioned apparatus, the performance evaluation of the upper layer is performed by using the queuing theory.

[0036]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention. Referring to FIG. 1, one embodiment of the present invention includes an arithmetic unit 100 operating under program control and a data input unit 110.
, A display unit 120, and a storage medium 130 storing a program.

FIG. 2 is a block diagram showing the configuration of the arithmetic unit 100 according to the first embodiment of the present invention. FIG.
Referring to, the arithmetic device 100 includes a data analysis unit 10
1, a calculation means 102, and a display pre-processing means 103.

Each of these means operates as follows. The data analysis unit 101 includes the data input unit 1
The input data is checked in step 10, the data is converted into a format suitable for processing by the arithmetic means 102, and the data is delivered. The calculation means 102 receives the data provided from the data analysis means 101 and calculates a performance evaluation value. The display pre-processing means 103 comprises the arithmetic means 10
The performance evaluation value calculated in step 2 is edited and processed into a form that is easy for the user to see, such as a table format or a graph, and is output to the display unit 120.

FIG. 4 is a flowchart showing a processing flow according to the first embodiment of the present invention. Next, FIG. 1, FIG. 8 and FIG.
The operation of the first exemplary embodiment of the present invention will be described in detail with reference to FIG.

First, basic data required for analysis is input to the input device 110. First, the hardware configuration of the lower layer is input (step A1).

Next, transaction data of a transaction using the software resources of the upper layer is input (step A2). The transaction data includes data representing the operation of using the process of the transaction, such as the load of each transaction, the name of the process to be used, and the use timing.

Next, process data of a process constituting a software resource of an upper layer is input (step A).
3). The process data includes data indicating an operation of using a hardware resource of a process, such as information on which hardware resource each process uses and at what timing.

Next, process constraints are input (step A4).

Next, what kind of performance evaluation value is to be displayed in what format is set (step A5).

Next, it is checked whether or not the given data is sufficient for calculating the performance evaluation value, and if the data is insufficient or incorrect, the user is requested to re-input (step A6). If it is determined that it is sufficient, a performance evaluation value is calculated (step A7). As an example of the performance evaluation value to be calculated, the throughput based on the load condition,
There are usage rates of each hardware resource and software resource, response time of each transaction, and the like.

The obtained performance evaluation value is processed (step A).
8) Display the performance evaluation value on the display means (Step A)
9).

Then, it is determined whether or not the performance evaluation is to be re-executed (step A10).
On the other hand, when the performance evaluation is re-executed, and when the hardware configuration is changed and the performance evaluation is re-executed, Step A in FIG.
Returning to step 1, the condition of the performance evaluation value to be displayed is changed to step A2 in FIG. 4 when the performance evaluation is performed by changing the transaction data, and to step A3 when the performance evaluation is performed by changing the process data. Step A4 in case
Return to and repeat the evaluation.

Next, the operation and effect of the first embodiment of the present invention will be described.

In the first embodiment of the present invention, since the constraints of the process are taken into account when calculating the performance evaluation, it is possible to appropriately evaluate resource conflicts having a hierarchical structure,
Software resource contention and hardware resources can be evaluated simultaneously.

[Embodiment 1] Next, the first embodiment will be described with reference to a specific embodiment. As shown in FIG. 8, a case in which performance evaluation is performed on an information processing system having a hardware configuration of a CPU (central processing unit), a DISK (disk device) 1, and a DISK 2 will be described. First, these hardware configurations are input.

Next, in this system, there are two types of transactions, TA and TB. Loading of TA, TB
Enter the load. The process that TA uses is P1,
In P2, the processes used by the TB are P1 and P3.
Data representing the operation of using the process of the transaction, such as the names of these processes and their use timing, is input.

Further, data indicating an operation of using the hardware resources of the process, such as which hardware resources are used by the processes P1, P2, and P3, and at what timing are input.

Here, the process P1 is executed by the CPU and the DIS.
The processes P2 and P3 use the hardware resources of K1 as CP.
U and the input of using the hardware resources of DISK2 are input, and furthermore, each process inputs data representing a hardware usage operation such as a timing of using the hardware resources.

Next, process constraints are input. Here, the process P1 has a maximum load value of 4, the process P2 has a used memory amount of 5 MB, and the process P3 has a restriction that the number of concurrently executing processes is "2".

Next, conditions for the performance evaluation result are set. For example, the throughput of the transaction TA when the load of the transaction TA changes from 0 to N, and
What is necessary is just to specify such a graph.

It is checked whether there is any error or lack in the input data, and if there is, the user is requested to input the data. The setting input, correction, etc. of the above data,
Continue until there are no errors or data shortages.

When there is no error or shortage in the input data, the set data is used to perform a performance evaluation operation under process constraints, and display is performed under the input display conditions.

[Second Embodiment] Next, a second embodiment of the present invention will be described. FIG. 3 is a diagram illustrating a configuration of the second exemplary embodiment of the present invention, and is a diagram illustrating a configuration of the arithmetic unit 102 in the arithmetic device 100 illustrated in FIG.
Referring to FIG. 3, in the second embodiment of the present invention, the arithmetic unit 102 includes a load condition generating unit 1 of an upper layer.
021, a lower layer performance evaluation unit 1022, an upper layer process speed calculation unit 1023, an upper layer performance evaluation unit 1024, and an overall performance evaluation unit 1025.

FIG. 5 is a flowchart showing a processing flow according to the second embodiment of the present invention. The operation of the second exemplary embodiment of the present invention will be described with reference to FIG. The second embodiment of the present invention is different from the above-described embodiment described with reference to FIG. 4 in step A7 of the performance evaluation value calculation processing. FIG. 5 shows details of step A7 in FIG.

In the processing up to step A6 shown in FIG. 4, the load condition generation unit 1021 of the upper layer calculates the range in which the loads of various processes change based on the given data (step A71).

If a process constraint is not given in the form of a load, a load value that can be taken by the process is calculated and replaced when operating under the process constraint. Then, for the loading of the processes belonging to the range,
The processing of 72 is executed. That is, when various loads of the process are given, the performance evaluation unit 1022 of the lower layer
A performance evaluation value of the lower layer under the condition of the process load is performed.

The process of step A72 is executed for all possible process loads under the given data conditions.

Next, based on this calculation result, the processing speed of each process under each process load condition is calculated by the process processing speed calculating means 1023 of the upper layer (step A7).
3). Using this processing speed, the performance evaluation of the upper layer is performed by the performance evaluation means 1024 of the upper layer (step A74).

Finally, the overall performance evaluation means 1025 summarizes the performance evaluations of the lower layer and the upper layer, and calculates an overall performance evaluation value (step A75).

Next, the operation and effect of the second embodiment of the present invention will be described.

Originally, the processing speed of the upper layer process depends on the situation of the lower layer. Therefore, the performance of the system cannot be evaluated unless changes in the state of all the lower layers and the upper layers are tracked. However, the processing speed of the process is calculated by giving the lower layer the load of the process of the upper layer as a condition, and by setting this value as the processing speed, the performance can be evaluated separately from the upper layer and the lower layer.

For this reason, the number of states to be handled is drastically reduced, and the amount of memory and calculation required for calculation can be saved.

Although the performance evaluation is performed by separating the upper layer and the lower layer, the load of the process of the upper layer is given as a condition during the performance evaluation of the lower layer, and the lower level is obtained at the time of calculating the performance evaluation of the upper layer. By calculating the processing speed of the process from the performance evaluation value of the layer, the performance evaluation can be performed without impairing the accuracy because the hierarchical structure of the system is adopted.

[Embodiment 2] Next, the second embodiment will be described with reference to a specific embodiment. Hereinafter, description will be given using the system having the configuration shown in FIG. The load values of processes P1, P2, and P3 are c1, c2, and c, respectively.
Suppose it is given by 3. From the given process constraint data, 0 ≦ c1 ≦ 4 may be set for the process P1, but the process P2 uses a memory with a maximum memory usage of 5
Up to MB, since the process P3 has a restriction that the number of executed processes is up to 2, these are converted into load values, and c
2. Calculate the range of possible values for c3.

The performance of the lower layer is evaluated for all combinations of loads c1, c2, and c3. The performance evaluation method of the lower layer will be specifically described.

As shown in FIG. 6, the lower layer is separated from the upper layer, and the process of the given load condition c is circulated to replace the system using the hardware resources.

The replaced system is referred to as a “lower-layer approximation system for load condition c”. The performance evaluation of the lower layer approximation system under the load condition c is performed for all possible values c under the constraint data of the process, and this performance evaluation value is compared with the performance evaluation value under the load condition c in the original system. I do.

Next, the processing speed of each process of the upper layer under the load condition c is calculated based on the performance evaluation value of the lower layer approximation system under the load condition c. At this time, the throughput or the average stay time is preferably used as the performance evaluation value of the lower layer used for calculating the processing speed of the process. The reason is that these values reflect the processing speed in the lower layer.

As shown in FIG. 7, the upper layer is separated from the lower layer, and the performance of the upper layer is evaluated by replacing it with a system having a processing speed dependent on the load condition. These calculation results are put together by the overall performance evaluation means to calculate the overall performance evaluation value.

[Embodiment 3] Next, a third embodiment of the present invention will be described. In the third embodiment of the present invention, the operation of the performance evaluation means in the lower layer is replaced with an operation using a queuing network model of a plurality of chains.

Next, the operation of the present embodiment will be described in detail with reference to FIG. 4 and FIG. The third embodiment of the present invention is a modification of the second embodiment, and the first change is the content of the process data to be input. In the second embodiment, as the input of the process data in step A3 shown in FIG. 4, data representing the operation such as the timing at which the process uses the hardware resources is input. However, in the third embodiment of the present invention, In the form, the process data includes, for each type of process, the hardware resources of the lower layer used by the process and the usage time, and the constraints of the process (for example, the number that can be started simultaneously, the total memory usage, and other specifications, etc.). give.

That is, in the third embodiment of the present invention, it is not necessary to input data representing operations such as timing.

The second modification is the configuration of the means for evaluating the performance of the lower layer. In the third embodiment of the present invention, queuing theory is used as the performance evaluation value calculation means of the lower layer in step A72 of FIG. 5 which is a flowchart for explaining the second embodiment. Examples of more specific means include:
Reference 1 (1995, July 370-375 and 8 in the Journal of the Operations Research Society of Japan)
The single profile method described in the commentary article entitled "Evaluation of Information Processing System Performance" published in the monthly issue, pp. 431-436, or the above-mentioned reference 3 (by K. Kant, published by McGraw-Hill Inc. in 1992) “Introduction to Computer”
Chapter 7, Section 3 (235
Queuing theory such as the performance evaluation method of the queuing network of a plurality of chains shown in the section -240).

Next, the operation and effect of the third embodiment of the present invention will be described.

In the third embodiment of the present invention, the performance evaluation of the lower layer is calculated by using the single profile method using queuing theory or the performance evaluation method of a multi-chain queuing network. And other detailed information becomes unnecessary.

Therefore, the information to be examined is reduced, and the data to be input is reduced. Further, since the number of states to be followed in the performance evaluation value calculation in the lower layer is reduced, the amount of memory and the amount of calculation are dramatically reduced.

[Embodiment 3] A third embodiment of the present invention will be described with reference to a specific embodiment. This embodiment is almost the same as the second embodiment, except that the process data of each of the processes P1 and P2 includes: a hardware resource of a lower layer to be used and its use time; (Total memory usage, other specifications, etc.) may be given, and there is no need to input data representing operations such as timing.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. In the fourth embodiment of the present invention, the calculation of the performance evaluation of the upper layer is performed by a Markov chain.

Next, the operation of the fourth embodiment of the present invention will be described with reference to FIGS. The fourth embodiment of the present invention is a modification of the second embodiment or a part of the second embodiment, and the first changed point is the contents of transaction data to be input. In the second and third embodiments, FIG.
In step A2, the transaction data is input.
Data representing an operation such as a timing at which a transaction uses a process has been input.

In the fourth embodiment of the present invention, as transaction data for each type of transaction, data necessary for calculating a transaction load at an arbitrary point in time; a process name used by the transaction; Gives the transition rate to other processes. In the fourth embodiment of the present invention, there is no need to input data representing operations such as timing.

The second change is the performance evaluation means of the upper layer. In the performance evaluation of the upper layer in step A74 of FIG. 5, the upper layer is analyzed as a Markov chain, and the performance is evaluated. For example, the above document (4) (Toshiyasu Kurasugi, Makoto Kiichi,
"Two-tiered queuing network model and its application", Comprehensive research on new performance evaluation methods for information and communication networks, 19
(Jan. 1997), an approximation method to Markov chains can be used.

Next, the operation and effect of the fourth embodiment of the present invention will be described.

In the present embodiment, in the performance evaluation calculation of the upper layer, the use of the Markov chain for the evaluation of the upper layer eliminates the need for detailed information such as the operation timing of the use of the process by the transaction. Therefore, the information to be examined is reduced, and the data to be input is also reduced. Further, since the number of states to be followed in the performance evaluation value calculation in the upper layer is reduced, the amount of memory and the amount of calculation are dramatically reduced.

[Embodiment 4] A fourth embodiment of the present invention will be described with reference to a specific embodiment. This example is almost the same as the example of the second embodiment, except that the transaction data includes the TA of the transaction,
For each TB, ・ Data required for load calculation at an arbitrary point in time ・ Process name to be used and a transition rate to another process at the end of the process only need to be given, and data representing operation such as timing needs to be input There is no.

[Fifth Embodiment] Next, a fifth embodiment of the present invention will be described. In the fifth embodiment of the present invention, the performance evaluation value calculation by the performance evaluation means of the upper layer is performed using a product form solution.

For the product form solution, see the above reference (3) (I.
Kino, “Queueing networks with hierachical configu
ration of active and passive stations ”, Proc. IEE
E SMC 96, Beijing, 1996, pp. 3051-3062).

Next, the operation of the fifth embodiment of the present invention will be described with reference to FIGS. This embodiment is a modification of the second, third, and fourth embodiments.

The first change is the contents of the transaction data to be input. Step A3 in FIG. 4 which is a flowchart for explaining the second, third and fourth embodiments.
In the Japanese Patent Application Laid-Open No. H08-27139, data representing an operation such as a timing at which a transaction uses a process or a transition rate to the next process at the end of the process is input. In the fourth embodiment of the present invention, as transaction data, for each type of transaction, data necessary for calculating a transaction load at an arbitrary point in time, a process name used by the transaction and its use frequency are given. Input of data representing operations such as timing,
There is no need to enter the transition rate to the next process at the end of the process.

The second change is that the performance evaluation value calculation by the performance evaluation means of the upper layer is performed using the product form solution.

An example of the performance evaluation means of the upper layer will be described. First, the above document (5) (Toshiyasu Kurasugi, Makoto Kiichi, "2
Product-form approximation of layered queuing network model and its accuracy verification ",
Comprehensive research on a new performance evaluation method for information communication networks, January 1998) calculates the service rate function defined by equation (6). After calculating the service rate function for all the load conditions, it is used to calculate the equation of the above reference (5).
Solve the upper layer as a product form solution using (7).

Next, the function and effect of the fifth embodiment of the present invention will be described.

In the fifth embodiment of the present invention, there is no need to input a transition rate to the next process at the end of a process. Therefore, the information to be examined is reduced, and the required data input can be further reduced.

Further, by using the product form approximation in the performance evaluation calculation of the upper layer, the number of states to be followed in the performance evaluation value calculation of the upper layer is further reduced, so that the memory amount and the calculation amount are further drastically reduced. .

[Embodiment 5] A description will be given of a specific embodiment of the fifth embodiment of the present invention. The transaction data is the same as that described in the example of the second embodiment, except that the transaction data of each of the transactions TA and TB includes: data necessary for calculating the load at any time; The use frequency may be given, and there is no need to input data representing the operation such as timing, and the transition rate to the next process at the end of the process.

[0101]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention is that the performance of the system can be evaluated even when there is hierarchical resource contention.

The reason for this is that, in the present invention, when the performance is evaluated, the restrictions of the process of the upper layer are taken into consideration.

A second effect of the present invention is to reduce the amount of calculation and memory required for performance evaluation.

The reason is that, in the present invention, the calculation is performed by separating the upper layer and the lower layer.

A third effect of the present invention is that performance can be evaluated without strictly defining a model.

The reason is that, in the present invention, it is not necessary to strictly model the system structure by using the queuing theory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an arithmetic unit according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a calculation unit according to the embodiment of the present invention.

FIG. 4 is a flowchart showing an overall operation of the embodiment of the present invention.

FIG. 5 is a flowchart showing a performance evaluation value calculation operation in one embodiment of the present invention.

FIG. 6 is a diagram schematically showing replacement of a lower layer in the embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of replacing an upper layer in the embodiment of the present invention.

FIG. 8 is a diagram schematically illustrating a configuration of a system in which a transaction uses hardware resources via a process.

FIG. 9 is a diagram schematically illustrating a configuration of a system in which a transaction directly uses hardware resources.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 arithmetic unit 101 data analysis unit 102 arithmetic unit 1021 upper layer load condition generation unit 1022 lower layer performance evaluation unit 1023 upper layer process speed calculation unit 1024 upper layer performance evaluation unit 1025 overall performance evaluation unit 103 before display Processing means 110 Data input means 120 Display means 130 Storage medium

Claims (8)

(57) [Claims] Claims: 1. Competition of lower layer hardware resources, and
Beauty, an apparatus for performance evaluation of <br/> system contention is performed in software resources in the upper layer, means for inputting the basic data of the system load, from said basic data of the system load and the input System
Means for performing a hardware performance evaluation of the lower layers of the arm, the upper with hardware performance evaluation results of the lower layer
Means for calculating the processing speed of the software of the layer, and using the processing speed of the software of the upper layer,
Means for performing software performance evaluation; and means for displaying the calculation result, wherein the performance evaluation is performed by separating the upper layer and the lower layer.
Perform, further, the performance evaluation of the upper layer and the lower layer together
A system performance evaluation device comprising means for performing overall performance evaluation . 2. The apparatus according to claim 1, wherein said means for calculating the performance evaluation value performs performance evaluation by a queuing method.
The system performance evaluation device according to the above. 3. Competition of hardware resources constituting a lower layer, and
And competing for software resources in an upper layer of the system. In the method, a basic data of a system load is input, and a hardware of a lower layer is input from the basic data of the system load.
Performance evaluation of the hardware, and using the performance evaluation result of the hardware of the lower layer,
Calculating a processing rate of the layer, of the software and the lower layer of the upper layer by evaluating the performance of the software of the upper layer by using the processing speed
The performance is evaluated by separating the hardware , and the upper layer
A system performance evaluation method comprising: performing a total performance evaluation by combining software performance evaluations of the software and the lower layer hardware; 4. The performance evaluation method of claim 3, wherein system and calculates the value using the queue the performance evaluation. Wherein (a) the process for analyzing the basic data of the input system load, the lower layer from (b-1) Basic system load data Ha
Processing the performance evaluation of adware, (b-2) a process of calculating a processing speed of the software of the upper layer using the hardware performance evaluation results of the lower layer, (b-3) the software of the upper layer processing the performance evaluation software of the upper layer by using a processing speed, (b-4) Ha software and the lower layer of the upper layer
A program for causing a computer to execute the above-described respective processes (a) to (c) of: (a) a process of performing a performance evaluation of the entire hardware by combining the performance evaluations of the hardware ; and (c) a process of displaying the calculated performance evaluation. Recording medium on which is recorded. 6. A process for inputting a hardware configuration of a lower layer, and a transaction using a software resource of an upper layer.
Operation of transaction process use
Process of inputting transaction data including data representative of, the process of configuring software resources of (c) the upper layer
The operation of using the hardware resources of the process.
Process for inputting the process data including to data, the maximum load value for the (d) process, amount of memory, the simultaneous
If there are restrictions such as the number of execution processes, these restrictions
Process of inputting, to set the type and display form of performance evaluation (e) analyzed
That process, to calculate the performance evaluation value data the input (f)
Check if it is sufficient for
If there is a request, the process requires the user to re-input . (G) The analysis target under the constraints of the upper layer process
And (h) displaying the performance evaluation value from the display device to the user.
Sense, of the (a) ~ a recording medium recording a program for executing each processing in a computer (h). 7. A step of: (a) inputting a hardware configuration of a lower layer; (b) inputting transaction data including data representing an operation of using a transaction for a transaction using a software resource of an upper layer; (C) inputting process data including data representing an operation of using the hardware resource of the process for the process constituting the software resource of the upper layer; (d) maximum load value, memory amount, and concurrently executing process for the process If there are restrictions such as the number, enter these constraint conditions; (e) set the type and display format of the performance evaluation to be analyzed; (f) calculate the performance evaluation value based on the input data Check if it is enough, and if it is missing or incorrect (G) calculating a performance evaluation value to be analyzed under the constraints of the upper layer process, and (h) displaying the performance evaluation value to the user. A system performance evaluation method comprising: 8. (g-1) a step of calculating a range in which the load of the process changes based on the data given in the steps up to the step (f) and generating a load condition of an upper layer; -2) performing a lower layer performance evaluation value under process load conditions in a process load range; (g-3) calculating a lower layer performance evaluation calculation result for each process load condition Calculating the processing speed of the process; (g-4) evaluating the performance of the upper layer using the processing speed; and (g-5) evaluating the performance of the lower layer and the upper layer. The system performance evaluation method according to claim 7 , further comprising: calculating a performance evaluation value.