JP3137489B2 - Write access contention adjustment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write access contention adjusting circuit, and more particularly to a write access contention adjusting circuit for a plurality of devices having priority.

[0002]

2. Description of the Related Art When data is transmitted between a plurality of devices, for example, two devices, a data holding means 200 such as a register or a dual port RAM is interposed as shown in FIG.

That is, data to be transmitted is once written in the data holding means 200 from the device A (or B), and the data is read from the device B (or A).

In this case, since data cannot be simultaneously written from the device A and the device B to the data holding means 200, a priority is provided between the devices A and B, and a priority device, for example, a device A write access conflict circuit 100 that adjusts the conflict between the write enable signals Wea and Web so that the write from the non-priority device B cannot be performed when the write from A is being performed is provided.

FIG. 6 shows a conventional write access contention adjusting circuit 100 when data transmission is performed between a plurality of (two in this case) devices. When the write enable signal Wea from the priority-side device A becomes "0" (when a write request is issued from the priority-side device A to the data holding means 200), the output of the AND gate 114 becomes "0" and this " The 0 ″ signal is input to the ck terminal of the flip-flop 200f included in the data holding unit 200. On the other hand, when the write enable signal Wea becomes "0", the gate 105 provided at the preceding stage of the D terminal of the flip-flop 200f constituting the data holding means 200 is turned on. Input data Din
a will be input. When the ck terminal input of the flip-flop 200f rises in this state, the input data Dina is latched by the flip-flop 200f.

As described above, when the priority-side device A is performing the write operation, the write enable signal Web output from the non-priority-side device B is masked by the AND gate 114 to affect the latch contents of the flip-flop 200f. Not to give. When the write enable signal Wea on the priority side is "1", the OR gate 113 can output a change in the write enable signal Web on the non-priority side.
When the write enable signal Wea is "0", the write enable signal Web is masked.

When the priority side device A is in the non-writing state (write enable signal "1"), the AND gate 1
In 14, a change in the state of the write enable signal Web of the non-priority device B is input to the ck terminal of the flip-flop 200 f. Since the mask of the OR gate 113 is removed, the non-priority device B
Is latched in the flip-flop 200f.

In Japanese Patent Application Laid-Open No. 61-262850, priorities are set for a plurality of processing requests, and among the processing requests written in a table provided in the interface, a processing request having a higher priority is set. From the start to the end.

[0009]

In the above conventional circuit, as shown in FIGS. 7A and 7B, the write enable signals Wea and Web of the priority side device A and the non-priority side device B temporally overlap. Consider a case where the rise of the write enable signal of the non-priority device B is later than the write enable signal of the priority device A.

The write enable signal Wea of the priority side device A
Once becomes “0” at time t ₁ , and even if it rises at time t ₃ , the output of the AND gate 114 does not
7 becomes "0" while the write enable signal Web is "0", and becomes "1" at the subsequent rise of the write enable signal Web of the non-priority device B (FIG. 7A,
(B), (f)).

The gate 10 through which the priority side data Dina passes
While 5 is ON at time t ₁ ~t ₃ (FIG. 7 (g)), thereafter is turned OFF, the gate 106 at time t ₃ ~t ₄
Is ON: Since (FIG 7 (e) time t ₂ ~t ₃ rests are masked by the OR gate 113), shown in FIG. 7 (j) at time t ₄ when the rising edge of ck pin input to the flip-flop 200f Thus, the data B1 of the non-priority device B
Will be latched.

Therefore, the data of the priority-side device A, which should be latched preferentially, cannot be latched by the data holding means 200, which is inconvenient. Therefore, for example, a program for checking whether the data written in the data holding means 200 is the data written by the user is provided in each of the devices A and B, but the amount of software is increased.

Further, the technique described in Japanese Patent Application Laid-Open No. 61-262850 can surely perform processing in the order of priority. However, this technique is originally applied to a large system, and there is a disadvantage that a small system has a large cost disadvantage.

The present invention has been proposed in view of the above-mentioned conventional circumstances, and provides a write access conflict adjusting circuit which can reliably write data from a high-priority external device in a small-scale system. It is intended for.

[0015]

The present invention employs the following means to achieve the above object. That is, FIG.
As shown in, when the priority-side device A and the non-priority-side device B mutually transmit data via the data holding means 200,
In the write access contention adjustment circuit used to avoid contention between write requests from the priority side device A and the non-priority side device B to the data holding means 200, the priority side device A
Is in a write request state, the write enable signal Wea of the priority side device A is output with priority, and is input to the data holding means 200, and the non-priority side device A is only output when the priority side device A is in the write non-request state. B, and outputs the write enable signal Web from B to the data holding means 200.
Is in a write request state, the write enable signal W
a gate 105 that is opened by ea to pass data Dina from the priority side device A, and is opened and disabled when the non-priority side device B is in a write request state and the priority side device A is in a write non-request state. Data D from priority side device B
The gate 106 is configured to pass inb.

Prior to the priority state holding means 100, a priority order selection means 40a is provided, and the priority order selection means 40a selects the write enable signals Wea, Web to be input to the priority state holding means 100. . Prior to the two gates 105 and 106, a priority order selecting means 40b is also provided.
In order to control the opening and closing of the gate 6, each gate 105, 106
Write enable signals Wea, W input to the control terminals of
eb is selected.

The priority state holding means 100 sets its output to "1" preferentially based on the write enable signal Wea of the priority side device A, and "0" based on the write enable signal Web of the non-priority side device B. a flip-flop 200f for outputting a state, the output of the flip-flop 200f as one input I _1, the write enable signal Web
The OR gate 103 to the other input I _2, the write enable signal Wea as one input I _1, and become more configuration and AND gate 104 to the output of the OR gate 103 as the other input I _2.

[0018]

When the write enable signal Wea output from the priority side apparatus A becomes "0" (write request), the priority state holding means 100 holds the state and outputs the write enable signal Web output from the non-priority side apparatus B. Do not pass. Only when the write enable signal Wea on the priority side becomes “1” (non-write request), the write enable signal Web of the device B on the non-priority side can be passed.

The priority state holding means 100 includes a flip-flop 100f with a set, and is set when the write enable signal Wea becomes "0", and outputs a signal "1". This signal “1” is the other input I ₂ of the AND gate 104 via the OR gate 103 described later. Accordingly, the output of the AND gate 104 outputs the state of the priority side write enable signal Wea, which is _one input I1 of the AND gate 104, as it is.

[0020] When the write enable signal Wea becomes "1", one input I ₁ of the AND gate 104 also becomes "1". At this time, when the falling edge of the non-priority-side write enable signal Web is input to the ck terminal of the flip-flop 100f, the Q output thereof becomes “0”,
The outputs of the OR gate 103 and AND gate 104 are governed by the state of the write enable signal Web.

The output of the priority state holding means 100 as described above becomes a write enable signal of the data holding means 200 and is input to the ck terminal of the flip-flop 200f constituting the data holding means 200. The data Dina of the priority-side device A is input to the D terminal of the flip-flop 200f through the gate 105, and the data Dinb of the non-priority device B is input to the D terminal through the gate 106.
Since these two gates 105 and 106 are opened based on the write enable signal Wea (or Web) passing through the priority state holding means 100, the data holding means 200 always holds proper data. .

[0022]

FIG. 2 is a block diagram showing an embodiment of the present invention. Write enable signal We on device A and device B side
a and Web are input to selectors 401 and 402 constituting the priority order selecting means 40a, where the select signal Sel is inputted.
Determines the priority. That is, the selector 4
When the selector 402 selects the write enable signal Wea on the device A side (selects the “0” terminal) and the selector 401 selects the write enable signal Web, Therefore, the case where the device A has priority is described.

The output of the selector 402, that is, the priority side write enable signal Wea is input to the set terminal of the flip-flop 100f with the set which constitutes the priority state holding means 100, and the write enable signal Wea falls (time t ₁ : device). B issues a write request to the data holding means 200) and causes the output Q of the flip-flop 100f to rise (FIGS. 3A and 3H). Thus, the output of the OR gate 103 provided on the output Q side of the flip-flop 100f changes to "1", the other input I ₂ of the next stage of the AND gate 104 to "1" (FIG. 3 (i )). The output of the time t ₁ until even the non-priority side of the write enable signal "1" (write unsolicited) by OR gate 103 is "1".

[0024] The preferential write enable signal Wea is a one input I ₁ of the AND gate 104, thereby, the output of AND gate 104 will be governed by the state of the write enable signal Wea of preferential .

The output of the selector 402 is connected to the "0" terminal of the selector 403 constituting the priority order selecting means 40b.
The output of the OR gate 103 is input to the “1” terminal of the selector 403 and the “0” terminal of the selector 404, while being input to the “1” terminal of the selector 404.
In this example, the “0” terminal of each of the selectors 403 and 404 is selected, whereby the selector 403 passes the output of the selector 402 (write enable signal Wea), and the selector 404 passes the output of the OR gate 103. Will be.

[0026] Thus, gate 105 is closed when the write enable signal Wea becomes "0" at time t _1, as described above, the gate 106 is open, the apparatus A side data Dina
(Data D ₁ ) is input to the D terminal of a flip-flop 200f as the data holding means 200 (FIG. 3A,
(L), (m)).

In this state, the priority side write enable signal W
When ea rises (time t ₂ ), the flip-flop 20
0f latches the priority side data Dina (data D ₁ ) (FIG. 3 (n)).

In this state, when the read enable signal Reb becomes the read request state “0” from the non-priority device B (time t ₂ ′), the gate 107 opens and the data D ₁ is output to the device B side. (FIGS. 3 (o), (q)).

When the priority device A has not issued a write request (when the write enable signal Wea is "1")
, When the non-preferential device B issues a write request (time t ₃ ~t _4: when the write enable signal Web has become "0") is as follows.

The write enable signal Web is supplied to the selector 40
1 and is inverted and input to the ck terminal of the flip-flop 100f. Therefore, the flip-flop 100f causes the fall of the write enable signal Web (time t ₃ ).
In latches the value "0" being input to the D terminal, and the Q output "0" of the flip-flop 100f, the I ₁ input of the OR gate 103 to "0" and (FIG. 3 (b), the
(H)). As a result, the output of the OR gate 103 is governed by the state of the write enable signal Web (FIG. 3).
(I)). Also, one input I ₁ of the AND gate 104
Is "1" (because the write enable signal Wea is "1"), the output of the AND gate 104 is also governed by the state of the write enable signal Web (FIG. 3).
(K)).

As a result, the output of the AND gate 104 is input to the flip-flop 20
0f can latch the input of the D terminal when the write enable signal Web rises from the state of “0”.

On the other hand, when the write enable signal Web is "0" (time t ₃ ~t _4), (the output of the OR gate 103) the output of the selector 404 is "0", the output of the selector 403 (selector 402 Output) is “1”, so that the gate 105 is turned on and the gate 106 is turned off. Therefore, the data Dinb of the non-priority device B is input to the D terminal of the flip-flop 200f. In this state, the write enable signal Web rises (time t).
₄ ) At the same time, the data Dinb (data C1) is latched by the flip-flop 200f (FIG. 3).
(N)).

Therefore, after that (time t ₄ ′), the priority-side device A goes into the read state (the read enable signal Rea is “0”), and the gate 108 is opened, so that the priority-side device A is connected to the bus on the priority side with respect to the flip-flop 200f. The data C1 is read (FIG. 3 (p),
(R)).

In the above example, the priority side write enable signal Wea
And the write enable signal Web on the non-priority side are not generated at the same time. Next, an example in which the two write enable signals Wea and Web are generated simultaneously will be described with reference to FIG.

When the priority side write enable signal Wea input to the set terminal of the flip-flop 100f falls (time t ₁ ), the flip-flop 100f is turned off.
The output of f rises (FIG. 4 (a),
(H)). Thus, the output of the OR gate 103 becomes possible to continue the "1" (since until the time t ₁ is also non-preferential write enable signal Web is "1", the output of the OR gate 103 is "1"), the following Step andgate 10
The other input I2 of ₄ is "1". As a result, the output of the AND gate 104 is governed by the state of the priority side write enable signal Wea (input I ₁ ).

On the other hand, the output of the selector 403 from which the output "0" of the selector 402 is output as it is
06 is opened, and the output of the selector 404 from which the output “1” of the OR gate 103 is output as it is is output to the gate 10.
5 is closed. Thereby, the data D from the device A is obtained.
The ina (data d1) is input to the D terminal of the flip-flop 200f (FIGS. 4A, 4E, and 4M).

In this state, when the write enable signal Wea rises (time t ₃ ), the flip-flop 200f latches and outputs the data Dina (data d1) from the device A (FIG. 4 (n)).

[0038] Consider the case where the write enable signal Wea as described above non-preferential write enable signal Web has become the write request state "0" while a write request state "0" (time t ₁ ~t ₃₎ I do.

Firstly, the output of the selector 401 while (time t ₂ ~ of the non-preferential write enable signal Web is "0"
t ₅ ) “0” (FIG. 4F). The flip-flop 100f whose output from the selector 401 is inverted and input to the ck terminal is the write enable signal W
When eb falls (time t ₂ ), the value of the D terminal is “0”
However, since “0” of the priority side write enable signal Wea is input to the set terminal,
BR> The Q terminal of the flip-flop 100f keeps the output "1" (FIG. 4 (h)). Therefore, while the write enable signal Wea is "0", the output of the OR gate 103 keeps "1", the non-priority side write enable signal Web is masked by the OR gate 103, and the influence of the write enable signal Web. Is the flip-flop 200
It will not appear in f.

[0040] Accordingly, after the rise of the write enable signal Wea, the non-priority side of the read enable signal Reb time t ₄ becomes "0", the data d ₁ gate 107 is open to the non-preferential device B It will be read out (FIG. 4 (q)). The non since preferential write enable signal when the Web rises (time t ₅₎ even flip-flop 100f is not hexa state change, the data d ₁ by the read enable signal Rea of preferential output at time t ₆ Is read out to the device A (FIG. 4).
(P), (r)).

[0041]

As described above, according to the present invention, when the priority side device issues a write request to the data holding means, the state is held, so that the write request of the priority side is not Even if the write requests on the priority side overlap, the data on the non-priority side can be reliably prevented from being written. Therefore, no check software is required, and the cost merit increases.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a time chart of the present invention.

FIG. 4 is a time chart of the present invention.

FIG. 5 is a conceptual diagram of a system to which the present invention is applied.

FIG. 6 is a block diagram of a conventional example.

FIG. 7 is a time chart of a conventional example.

[Explanation of symbols]

40a, 40b priority selection unit 100 preferentially status holding unit 103 OR gate 104 AND gate 105, 106 gates 200f flip-flop A preferential device B non preferential apparatus Dina, Dinb data I _1, I ₂ input Wea, Web write enable signal

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-47-45145 (JP, A) JP-A-57-41755 (JP, A) JP-A-1-116742 (JP, A) JP-A-3- 167652 (JP, A) JP-A-62-293457 (JP, A) JP-A-63-268061 (JP, A) JP-A-61-262850 (JP, A) JP-A-59-114659 (JP, A) JP-A-62-173560 (JP, A) JP-A-4-54543 (JP, A) JP-A-62-196744 (JP, A) JP-A-4-17053 (JP, A) JP-A-64-99142 (JP, a) JP Akira 60-159959 (JP, a) JP Akira 59-226920 (JP, a) JitsuHiraku Akira 61-51549 (JP, U) (58 ) investigated the field (Int.Cl. ⁷ G06F 12/00-12/06 G06F 13/16-13/18

Claims (2)

(57) [Claims] 1. A priority device (A) and a non-priority device (B)
Avoids contention between write requests to the data holding means (200) from the priority side device (A) and the non-priority side device (B) when transmitting data to each other via the data holding means (200). In the write access conflict adjusting circuit used for this purpose, when the priority side device (A) is in a write request state, the write enable signal (Wea) of the priority side device (A) is preferentially output, and the data holding means ( 200), and outputs a write enable signal (Web) from the non-priority side device (B) only when the priority side device (A) is in the non-write request state, and inputs the write enable signal (Web) to the data holding means (200). A priority state holding means (100) for opening the data by the write enable signal (Wea) when the priority side device (A) is in a write request state; Data and gate to pass (Dina) (105), the non-preferential device (B) is a write request state,
In addition, the gate (106) that opens when the priority side device (A) is in the write non-request state and allows the data (Dina) from the non-priority side device (B) to pass through, and the priority state holding means (100) has priority. The output is preferentially set to “1” based on the write enable signal (Wea) of the side device (A), and the state of “0” is output based on the write enable signal (Web) of the non-priority device (B). A flip-flop (100f) to perform the operation, an OR gate (103) using the output of the flip-flop (100f) as one input (I1) and the write enable signal (Web) as the other input (I2), and the write enable signal (Wea) to one input (I
1) and an AND gate (104) that uses the output of the OR gate (103) as the other input (I2). 2. A priority order selecting means (40a) is provided in front of the priority state holding means (100), and the priority order selecting means (40a) writes the data to be input to the priority state holding means (100). Enable signals (Wea), (W
eb) and the two gates (10
5), the priority selection means (40) before (106).
b) to control the opening and closing of the gates (105) and (106) in order to control the opening and closing of the gates (105) and (106).
2. The write access conflict adjusting circuit according to claim 1, wherein a) or (Web) is selected.