JPS5846725B2 - Interrupt input control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt input control method when one interrupt input device 7 is shared by a plurality of data processing devices.

When increasing reliability by making data processing equipment redundant, etc.
It is necessary to commonly apply an interrupt input signal to a plurality of redundantly connected data processing devices.

In this case, it is uneconomical to provide an interrupt input device for each data processing device, and it is also troublesome that the conductor from the interrupt signal source must be branched and connected to each interrupt input device.

On the other hand, if one interrupt input device is shared by multiple data processing devices, this problem will disappear, but since the interrupt input signal is cleared when it is read by one data processing device, Other data processing devices are not aware of the interrupt input signal.

This always occurs when redundant data processing devices operate asynchronously and at their own timing.

After one data processing device reads an interrupt input signal, in order for other data processing devices to be able to learn about the interrupt input signal, the device interrupt input signal must be output from the data processing device that read the interrupt input signal. It may be possible to transmit the information to other data processing devices, but this requires tight coupling between the data processing devices and also requires special connection lines.

It is preferable that the coupling between data processing devices be as coarse as possible as long as the intended purpose is achieved.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt input control method that allows an interrupt input device whose contents are cleared after reading to be shared by a plurality of asynchronously operated and relatively loosely interconnected data processing devices.

The present invention provides a storage device for copying an interrupt input signal for each of a plurality of data processing devices, and each time one data processing device reads an interrupt input device, a copy is made to the storage device for another data processing device, and the other data processing devices When the data processing device subsequently reads the interrupt input device, it reads the logical sum of the contents of the interrupt input device and the value stored in its own storage device.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a conceptual block diagram of an embodiment of the present invention.

In Figure 1, CPUA and CPUB are data processing devices, INT is an interrupt input device, and PC is an interrupt input control ζ
It is a place.

The human interrupt device INT holds a plurality of words of an interrupt input signal, that is, a digital signal in which each bit is associated with an interrupt cause.

The data processing devices CPUA and CPUB read these interrupt input signals through the interrupt input control device IPC.

The interrupt input control device IPC includes a control circuit CNT, a selector SEL, a register RG, memory devices (random access memory, etc.) RAMA, RAMB, AND gates GAI, GA2, GB, GB2, and an OR gate GAa. GA4. GB3. I have a GB4.

The memories RAMA and RAMB are for data processing units CPUA and CPUB, respectively.

The control circuit CNT includes data processing devices CPUA and CPUB.
to the read request signal REQA of the interrupt input device INT.

REQB is given to each.

The control circuit CNT generates selection signals 5LCTA and 5LCTB for granting reading rights to either one on a first-come, first-served basis.

Selection signals 5LCTA and 5LCTB control opening and closing of AND gates GAI t G A2 and GB1, GB2, respectively.

Selection signal 5LCTA is applied to selector SEL to control its switching.

The selector SEL has data processing devices CPUA and CPUB.
Then, address signals ADR8(A) and ADR8(B) for reading from the interrupt input device INT are applied, and one of them is selected and applied to the register RG.

An address is set in register RG by read request signal REQ issued by control circuit CNT.

This read request signal REQ is applied to the interrupt input device INT.

The address set in the register RG is the address AD in the interrupt input device INT and the memories RAMA and RAMB.
Given as R8.

According to interrupt request signal REQ and read address ADR8, read response signal A is output from interrupt input device INT.
CK and interrupt input signal DI are output.

The read response signal ACK is given to the control circuit CNT, and the read response signal AC is sent to the data processing device having the read right through the AND gate GA1 or GBt.
Given as KA or ACKB.

Interrupt input signal DI is stored in memory RAMA, RAMB O)
Given to the data input terminal.

The interrupt input signal DI is also an OR gate G, A4 t
Memory RAMA by GI34 respectively.

They are logically summed with the output signals D 0 (A) and D 0 (B) of RAMB and sent to the data processing devices CPUA and CP, respectively.
The input data is given to UB as input data DI(A) and DI(B).

Data processing device CPUA or CP with read permission
UB reads input data according to read response signal ACKA or ACKB.

Read response signals ACKA and ACKB are applied to memory R through OR gates GB3 and GA3, respectively.
Provided to the write enable terminals of AMB and RAMA.

As a result, when input data is read into a data processing device that has read authority, the interrupt input signal is written, that is, copied, to the memory of the data processing device that does not have read authority.

When the reading is completed, a clear signal PW is sent from the control circuit CNT.
R is output, and AND gate GA2 and OR gate GA3 or AND gate GB2 and OR gate GB
3, write/write memory RAMA or RAMB.
Given to the enable terminal.

Since the AND gates GA2 and GB2 are opened on the side to which the read right is granted, the clear signal PWR is applied to the memory device on the side to which the read right is granted.

Since the interrupt input signal has already been cleared when the clear signal PWR is applied to the memory, the stored value is cleared by writing it.

The operation of the device configured in this way is as follows.

An explanatory diagram of the operation is shown in FIG. The data processing device CPUA specifies address $10 (in hexadecimal) and sends a read request signal R.
Suppose that the data processing device CPUB issues a read request signal REQB specifying address #20 after issuing EQA, then the request from the first arriving data processing device CPUA is accepted by the control circuit CNT, and the request is sent to the data processing device CPUA. A selection signal 5LCTA is generated which gives read permission.

As a result, AND game 1' GAI and GA2 are opened, and data processing unit CPUA is opened by selector SEL.

is selected.

Then, a read request signal REQ is outputted from the control circuit CNT, and is applied to the register RG and the interrupt input device INT.

As a result, address #10 is set in register RG, which is used by interrupt input device INT and memory RAMA.
, RAMB as address ADR8.

The interrupt input device INT is activated by the read request signal REQ and receives the interrupt input signal $ held at address #10.
It outputs AAAA and issues a read response signal ACK.

Interrupt input signal #AAAA is sent to memory devices RAMA and RAMB
Or Gate GA, 4. GB4
By memory RAMA.

They are logically summed with the contents of address #10 of RAMB and provided to data processing devices CPUA and CPUB.

The contents of address #10 in memory RAMA are #5555
If so, the input data DI(A) of the data processing device CPUA becomes #FF by the logical sum of this and #AAAA.
Becomes FF.

Data processing device CPUA reads input data #FFFF in accordance with read response signal ACKA applied through open AND gate GA1 and drops read request signal REQA.

On the other hand, since the AND gate GB1 is closed, the read response signal ACKB is not applied to the data processing unit CPUB, and therefore the input data D■(B) is not read.

Read response signal A given to data processing device CPUA
CKA is applied to the write enable terminal of memory RAMH through OR gate GB3.

As a result, interrupt input signal #AAAA is written to address #10 of memory RAMB.

That is, the interrupt input signal is copied to the memory on the side that does not have read authority.

When the reading and copying of the interrupt input signal is completed, the read response signal ACK of the interrupt input device INT is dropped, and the interrupt input signal at address #10 is cleared.

When the read response signal ACK falls, the control circuit CNT issues a clear signal PWR at an appropriate timing.

This signal is applied to the write enable terminal of the memory RAMA through the open AND gate GA2 and OR gate GA3, and writing to the memory RAMA is performed.

At this time, the interrupt input signal DI is cleared, so
By writing this, the contents of address #10 of the memory RAMA are cleared.

This completes the operation of one read request by the data processing device CPUA.

Next, since the data processing device CPUB has issued the read request signal REQB, the control circuit CNT generates a selection signal 5LCTB that gives read authority to the data processing device CPUB.
-3, opens the AND gate 1''GBttGB2, closes the AND gates GA1...GA2, and causes the selector SEL to select the data processing device CPU B.

As a result, the positions of the data processing devices CPUA and CPUB are swapped, and in that state, the same operation as described above is performed.
The interrupt input signal is read by the data processing unit CPUB and copied by the memory RAMA.

Thus, the present invention provides a memory for copying the interrupt input signal for each of a plurality of data processing devices, and each time one data processing device reads the interrupt input device, the memory for the other data processing devices is copied. When another data processing device subsequently reads the side input device, it reads the logical sum of the contents of the interrupt input device and the value stored in its own storage device.

Therefore, a plurality of data processing devices that operate asynchronously can share one interrupt input device while remaining relatively loosely coupled.

Also, the shared side legs can be realized by relatively simple means.

[Brief explanation of the drawing]

FIG. 1 is a conceptual block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the apparatus shown in FIG. CPUA, CPUB... Data processing device, ■N
T...Interrupt input device, ■PC...Interrupt input control device, CNT...Control circuit, SE
L...Selector, RG...Register,
RAMA, RAMB... Memory device.

Claims (1)

[Claims] 1 A control method for inputting interrupt signals from a common interrupt manual device whose contents are cleared after reading the interrupt signal to multiple data processing devices that operate asynchronously and are relatively loosely interconnected. A plurality of storage means provided corresponding to each of the data processing devices, and a logical sum of the interrupt signal read from the interrupt input device and the interrupt signal read from the storage means, are stored in the respective data processing devices. means for adjusting the contention for reading the interrupt input device by a plurality of data processing devices to allow one data processing device to read; An interrupt input control method comprising means for storing an interrupt signal in a storage means for another data processing device.