JP3138160B2 - Video output device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video output device,
In particular, for example, the present invention relates to a video output device that outputs N types of video signals to N display units as in a time-lapse VCR.

[0002]

2. Description of the Related Art FIG. 12 shows an example of a video output device in a time-lapse VCR which divides a screen into four and outputs four types of video signals to one monitor. FIG.
In the conventional video output device 1, the video signals Y1 and Y3 output from the A / D converter 2a are written into the VRAM 4a by a write control signal from the microcomputer 3, and are output from the A / D converter 2b. The output video signals Y2 and Y4 are supplied to the VRA by a write control signal from the microcomputer 3.
Written to M4b. That is, the video signals Y1 and Y3 respectively correspond to the area A1 of the VRAM 4a shown in FIG.
And A3, and the video signals Y2 and Y4 are written to the areas A2 and A4 of the VRAM 4b, respectively. The video signals Y1 to Y4 are read out by scanning the addresses of the VRAMs 4a and 4b from above as shown in FIG.
And output via the D / A converter 6. As a result, the monitor 7 displays the video signals Y1 to Y as shown in FIG.
4 is output.

[0006] In another conventional video output device 1 shown in FIG. 16, video signals Y1 to Y4 sequentially output from an A / D converter 2a are applied to regions A1 to VRAM4a and 4b shown in FIG. A / D converter 2b
Are sequentially output from the VRAM 4c.
And 4d in areas B1 to B4. Since the microcomputer 3 switches between the write signals for the VRAMs 4a and 4b and the write signals for the VRAMs 4c and 4d for each field, as shown in FIG.
AM4a and 4b have the previous video signals Y1-1 to Y4.
-1 is written, and the current video signals Y1-2 to Y4-2 are written to the VRAMs 4c and 4d. further,
The next video signal Y1- output from the A / D converter 2a
3 is written to the area A1 of the VRAM 4a as shown in FIG.

[0004] Of the video signals written in the VRAMs 4a to 4d in this manner, the monitor 7 is supplied with the latest video signal. Therefore, the VRAMs 4a to 4d are shown in FIG.
When the video signal is written as shown in FIG. 7B, the video signals Y1-2 to Y1-2 in the VRAMs 4c and 4d are output.
The image based on 4-2 is displayed on the monitor 7 as shown in FIG. While the video signal Y1-3 is being written as shown in FIG. 17C, the video shown in FIG. 18A is output from the monitor 7, and the video signal Y1 is output.
When the writing of -3 is completed, the video signals Y1-3, Y2-2, Y3-2 and Y4 are output as shown in FIG.
-2 is displayed.

[0005]

However, in the prior art shown in FIG. 12, the writing speed and the reading speed of the video signal are different as shown in FIG. Therefore, for example, as shown in FIG. 20, when the reading is started while the video signal Y3-2 is being written to the area A3, the monitor 7 displays the previous video signals Y3-1 and Y3-1 as shown in FIG. The current video signal Y3-2 will be displayed,
There was a problem that the image was shifted up and down.

Further, the conventional technique shown in FIG. 16 solves the problem that a vertically displaced image is displayed on the monitor 7 as described above, but the VRAM is twice as large as the conventional technique shown in FIG. However, there is a problem that the number of parts increases and the cost increases. Hence,
A main object of the present invention is to provide a video output device capable of displaying a clear video on a monitor while minimizing the number of VRAMs.

[0007]

According to a first aspect of the present invention, in a video output device for outputting N types of video signals to N display units, one type of video signal is selected from the N types of video signals in a predetermined order. Selection means, N + 1 memory means to which the video signal selected by the selection means is written, and memory means to which the previously written memory means of the two memory means to which the same kind of video signal is written is selected by the selection means. A video output device comprising: a writing unit that writes a video signal, and a reading unit that reads a video signal from N memory units to which writing has not been performed at present and supplies the video signal to N display units.

According to a second invention, a first number of A / D converters is provided.
Input video data and store it in the second number field memory
Video data having a screen divided into a second number
In a video output device for outputting to a computer, a first number is converted to a second number
Less and more first memory
Video data input from the first number of A / D converters.
Data to the first number of field memories,
Stored in a second number of field memories that have not been
A video output device for outputting the video data to a monitor .

[0009]

According to the first aspect, for example, two types of video signals Y1-1 and Y3- sequentially output from a multiplexer are provided.
Is written into the areas C1, C3 and C3 of the areas C1, C3 and C5 of the VRAM by the microcomputer, for example, and the video based on the video signals Y1-1 and Y3-1 is stored in the first and second areas of the monitor, for example. It is projected. Next, the video signal Y1-2 is output from the A / D converter.
And Y3-2 are sequentially output and written to the areas C5 and C1 of the VRAM, respectively. Note that the video signal Y
The reason why 3-2 is written in the area C1 is that, of the areas C1 and C5 in which the video signals Y1-1 and Y1-2 of the same type have been written, the area C1 has been written first. Then, the video signal Y1-2 is displayed on the monitor.
When the writing of video signals is completed, video signals Y1-2 and Y1-2
3-1 is displayed, and then the video signal Y3-
When the writing of No. 2 is completed, an image based on the image signals Y1-2 and Y3-2 is displayed.

In the second invention, for example, four types of video signals Y1 to Y4 are supplied to a multiplexer, for example, and two predetermined video signals are output for each field from the multiplexer. The output video signal is supplied to, for example, a microcomputer via the first and second A / D converters, for example, by a microcomputer.
Is written in a predetermined area of the VRAM having Then, the video signals Y1 to Y
4 is read and output to the first to fourth areas of the monitor. The video signals Y1-1 and Y
When 2-1 and the video signals Y3-1 and Y4-1 are output, they are respectively written into the areas C1 to C4 of the VRAM. Thereafter, the video signals Y1-1 to Y1-1 to C1 to C4 are output from the regions C1 to C4.
Y4-1 is read and output to the first to fourth areas of the monitor. Subsequently, the video signal Y1 is sequentially output from the multiplexer.
-2 and Y2-2 and video signals Y3-2 and Y4-2
Is output, the video signals Y1-2 and Y2-2 are written to the areas C5 and C6, and the video signals Y3-2 and Y4-2 are written to the areas C1 and C2. When writing to the areas C5 and C6 is completed, the microcomputer outputs the video signals Y from the areas C5, C6, C1 and C2.
1-2, Y2-2, Y3-1 and Y4-1 are read out and output to the first to fourth areas of the monitor. When the writing to the areas C1 and C2 is completed, the video signals Y1-2 to Y4-2 are read from the areas C1 to C4 and output to the first to fourth areas of the monitor.

[0011]

According to these inventions, the video signal is read from the memory means when the writing of the video signal is completed, so that the video displayed on the display unit or the monitor does not shift vertically. . Further, it is only necessary to provide an extra memory means or add the same number as the number of A / D converters, so that the number of memory means can be reduced.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a video output device 10 of this embodiment includes input terminals P1 to P4, and has input terminals P1 to P4.
Video signals Y1 to Y4 for one to four fields are supplied to the multiplexer 12. Video signals Y1 and Y3 are provided from the output terminal P5 of the multiplexer 12 to the A / D converter 14a every other field, and these video signals Y1 and Y3 are converted into digital signals.
The video signal Y2 is output from the output terminal P6 of the multiplexer 12 to the A / D converter 14b every other field.
And Y4, whereby the video signals Y2 and Y4 are converted into digital signals. Further, from the multiplexer 12 to the microcomputer 16, which video signal is output from the output terminals P5 and P6 to the A / D converters 14a and 1
4b is provided with output terminal information indicating whether the output has been made. The output terminal information is “0” for the video signal Y1.
0 ", the video signal Y2 is" 01 ",
The value is "10" for the video signal Y3 and "11" for the video signal Y4.

The video signals Y1 and Y3 output from the A / D converter 14a and the video signals Y2 and Y4 output from the A / D converter 14b are combined with the VRAMs 18a to 18c.
2 according to the write enable signal and the address signal from the microcomputer 16 shown in FIG.
Is written to any of Then, the video signals Y1 to Y4 are read from any of the areas C1 to C6 according to the read enable signal and the address signal from the microcomputer 16, and are provided to the monitor 24 via the multiplexer 20 and the D / A converter 22. As a result, an image based on the image signals Y1 to Y4 is displayed on the MON1 block to the MON4 block of the monitor 24 shown in FIG. As shown in FIG. 4, the RAM 16a in the microcomputer 16 stores areas C1 to C5 of VRAMs 18a to 18c.
Output terminal information and flag information relating to the video signal written in 6 are written.

Next, the processing operation of the microcomputer 16 when writing the video signals Y1 to Y4 in the areas C1 to C6 will be described with reference to FIG. First, in step S1, it is determined whether or not the video signal Y1 or Y3 has been output from the multiplexer 12 based on the output terminal information. And
If “YES”, the area C is referred to by referring to the RAM 16a.
A search is made for areas where the output terminal information is the same among 1, 3, and 5 and the process proceeds to step S5. On the other hand, if “NO” in the step S1, it is determined whether or not the video signal Y2 or Y4 is output from the multiplexer 12 based on the output terminal information in a step S7. If "NO", the process returns to the step S1, but the "YE
If "S", in step S9, a search is made for the same area of the output terminal information among the areas C2, C4, and C6, and the process proceeds to step S5. In step S5, the two areas searched by referring to the RAM 16a are searched. Next, in step S11, a column address and a row address of the selected area are initialized, and a write enable signal is output.

Subsequently, in step S13, it is determined whether or not the column address has been counted 270 dots.
If "O", the column address is incremented in step S15 and the process returns to step S13.
If S ", it is determined in step S17 whether or not the row address has been counted for 120 lines.
If "NO", the row address is incremented in step S19 and the process returns to step S13.
If S ", a write disable signal is output to the selected area in step S21, and a flag of the selected area is set and the input terminal information of the written video signal is written in step S23. In step S25, among the areas searched in step S3 or S9, the flag of the area in which writing has not been performed is reset, and the process returns to step S1.

Subsequently, referring to FIG. 6 to FIG.
The processing operation of the microcomputer 16 when reading the video signals Y1 to Y4 from C6 to C6 will be described. First, step S
In step 27, the area where the output terminal information is "00" is searched with reference to the RAM 16a, and in step S29, the area in which the flag is set among the searched areas is set as the MON1 block area. Next, in step S31, an area where the output terminal information is "01" is searched, and among the searched areas in step S33, an area where a flag is set is set as a MON2 block area. continue,
In step S35, the area whose output terminal information is "10" is searched, and among the searched areas in step S37, the area in which the flag is set is set as the MON3 block area. Then, in step S39, a block whose output terminal information is "11" is searched, and among the searched areas in step S41, the area in which the flag is set is set as the MON4 block area.

Subsequently, in step S43, MON1
The column address and row address of the block area are initialized, and a read enable signal is output. Thereafter, it is determined in step S45 whether or not the column address has been counted to 270 dots. If "NO", the column address is incremented in step S47 and the process returns to step S45. If "YES", the process proceeds to step S45.
At 49, a read disable signal is output to the MON1 block area. Subsequently, step S51
, The column address and the row address of the MON2 block area are initialized, and a read enable signal is output. Next, in step S53, it is determined whether or not the column address has been counted 270 dots. If "NO", the column address is incremented in step S55 and the process returns to step S53. If "YES", the process proceeds to step S57. A read disable signal is output to the MON2 block area. Next, in step S59, it is determined whether the row address has been counted for 120 lines, and if "NO", the process proceeds to step S6.
In step 1, the row address is incremented, and step S
Returning to step S45, if "YES", the process proceeds to step S63.

In step S63, a column address and a row address of the MON3 block area are initialized, and a read enable signal is output. Next, in step S65, it is determined whether or not the column address has been counted 270 dots. If "NO", the column address is incremented in step S67 and step S6 is performed.
Returning to step 5, if "YES", a read disable signal is output to the MON3 block area in step S69. Subsequently, at step S71, M
The column address and the row address of the ON4 block area are initialized, and a read enable signal is output. Thereafter, it is determined whether or not the column address has been counted 270 dots in step S73. If "NO", the column address is incremented in step S75 and the process returns to step S73. If "YES", MON4 is determined in step S77. A read disable signal is output to the block area. Then, it is determined in step S79 whether or not the row address has counted 120 lines. If "NO", the row address is incremented in step S81 and the process returns to step S65, but if "YES", the process returns to step S27.

By processing by the microcomputer 16 in this manner, first, as shown in FIG. 9A, the video signals Y1-1 to Y4-1 input first are converted into VRAMs 18a and 1
8b are written to the areas C1 to C4 of 8b, and based on this, video based on the video signals Y1-1 to Y4-1 is output to the MON1 to MON4 blocks of the monitor 24.
Next, the video signals Y1-2 and Y2-2 output from the A / D converters 14a and 14b are written into the areas C5 and C6 of the VRAM 18c as shown in FIG. While the video signals Y1-2 and Y2-2 are being written, a video based on the video signal shown in FIG. 9B is output to the monitor 24, but the video signal Y1-2,
When the writing of Y2-2 is completed, the microcomputer 16 sets the video signals Y1-2 and Y2 in the order of the areas C5, C6, C3 and C4.
-2, Y3-1 and Y4-1 are read out. Thus, an image based on the image signals Y1-2, Y2-2, Y3-1 and Y4-1 is displayed on the monitor 24 as shown in FIG. 10B. That is, the video in the MON1 block and the MON2 block is updated.

Subsequently, A / D converters 14a and 14b
Output Y3-2 and Y4-2 from the microcomputer 16, the microcomputer 16 outputs these video signals Y3-2 and Y4-2.
Is written to the areas C1 and C2 as shown in FIG. While the writing is being performed, the video based on the video signal shown in FIG. 10B is output to the monitor 24, but when the writing is completed, the monitor 24 outputs the video signal shown in FIG. A video based on the output is output. That is, the video signals Y1-
2, Y2-2, Y3-2 and Y4-2 are output, whereby the images in MON3 and MON4 are updated.

According to this embodiment, when the writing of the video signal is completed, the video signal is read from the VRAM and displayed on the monitor, so that the video on the monitor does not shift vertically. Also, since only one extra VRAM needs to be provided, the number of memories can be minimized. Although this embodiment has been described using a monitor divided into four parts, the present invention is not limited to this case, and it is needless to say that the present invention can be applied to a case where each kind of video signal is output to four monitors.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a part of the embodiment in FIG. 1;

FIG. 3 is an illustrative view showing another portion of the embodiment of FIG. 1;

FIG. 4 is an illustrative view showing another portion of the embodiment of FIG. 1;

FIG. 5 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 6 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 7 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 8 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

9A is an illustrative view showing a video signal written in a VRAM, and FIG. 9B is an illustrative view showing an image displayed on a monitor; FIG.

FIG. 10A is an illustrative view showing a video signal written to a VRAM, and FIG. 10B is an illustrative view showing an image projected on a monitor;

11A is an illustrative view showing a video signal written in a VRAM, and FIG. 11B is an illustrative view showing an image displayed on a monitor; FIG.

FIG. 12 is a block diagram showing a conventional technique.

FIG. 13 is an illustrative view showing a part of the prior art shown in FIG. 12;

FIG. 14 is an illustrative view showing a part of the prior art shown in FIG. 12;

FIG. 15 is an illustrative view showing a part of the related art shown in FIG. 12;

FIG. 16 is a block diagram showing another conventional technique.

FIG. 17A is an illustrative view showing a VRAM,
FIGS. 3B and 3C are illustrative views showing video signals written to a VRAM.

FIGS. 18A and 18B are illustrative views showing an image displayed on a monitor. FIGS.

FIG. 19 is a graph showing a reading speed and a writing speed.

FIG. 20 is an illustrative view showing a part of the related art shown in FIG. 12;

FIG. 21 is an illustrative view showing a part of the prior art shown in FIG. 12;

[Explanation of symbols]

 10 Video output device 16 Microcomputer 18a, 18b, 18c VRAM

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-30491 (JP, A) JP-A-6-149985 (JP, A) JP-A-6-261263 (JP, A) JP-A-6-261263 86187 (JP, A) JP-A-2-186885 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/00-5/00 555 G06T 1/60 H04N 5/44 -5/45 H04N 5/907

Claims (4)

(57) [Claims] 1. A video output device that outputs N types of video signals to N display units, wherein: a selection unit that selects one type of the video signals in a predetermined order from the N types of video signals; N + 1 memory means to which the selected video signal is written, and the memory means which is selected by the selecting means to the memory means which has been written first among the two memory means to which the same kind of video signal is written. A video output device comprising: a writing unit that writes a video signal; and a reading unit that reads out the video signal from the N memory units that have not been written at the present time and supplies the video signal to the N display units. 2. The writing means includes: a search means for searching the two memory means; and a signal writing means for writing the video signal inputted this time to the memory means having a flag reset among the two memory means. 2. The apparatus according to claim 1, further comprising: a flag control unit configured to set the flag for the memory unit that has been written this time among the two memory units and to reset the flag for the memory unit that has not been written this time. Video output device. 3. The video output device according to claim 1, wherein said read means includes signal read means for reading said video signal from said N memory means in which said flag is set. 4. An image data input from a first number of A / D converters.
The image stored in a second number of field memories
Data to a monitor having a screen divided into the second number
In the video output device for outputting, the first number is smaller than the second number, and the first number is
The field memory is further added, and the image input from the first number of A / D converters is added.
Write data to the first number of the field memories
Only, the second number of the files that have not been written.
The video data stored in the
A video output device, characterized in that the image is output to a video output device.