JP3244390B2 - Video output device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video output device,
In particular, for example, the present invention relates to a video output device that outputs N types of video signals to N display units as in a time-lapse VCR.

[0002]

2. Description of the Related Art FIG. 18 shows an example of a video output device in a time-lapse VCR for outputting 16 types of video signals to a monitor obtained by dividing a screen into 16 portions. Referring to FIG. 18, in the conventional video output device 1, one field of video signals Y1 to Y8 and video signals Y9 to Y16 output from the multiplexer 2 in a predetermined order are A /
The conversion is performed by the D converters 3a and 3b. Then, a part of the video signals Y1 to Y8 output from the A / D converter 3a is extracted by the vertical filter block 4a and written in a predetermined area of the VRAM 5a. Further, a part of the video signals Y9 to Y16 output from the A / D converter 3b is extracted by the vertical filter block 4b, and the extracted signals are extracted by VRA.
Write to M5b. Specifically, the VRAM shown in FIG.
The video signals Y1 to Y8 are written in the Y1 to Y8 areas of the VRAM 5a, and the video signals Y9 to Y8 are written in the Y9 to Y16 areas of the VRAM 5b.
Write Y16. As a result, V
The video signal is updated in any one area of the RAM 5a and any one area of the VRAM 5b. V
Video signals Y1 to Y written in RAMs 5a and 5b
16 is read out by the multiplexer 6, whereby the monitor 7 is divided into 16 screens as shown in FIG.
Are output as video signals Y1 to Y16. Therefore, on the monitor 7, the video signals Y1 to Y
8 and one of the video signals Y9 to Y16 have been updated.

[0003]

However, in such a conventional technique, the video signals supplied to the A / D converters 3a and 3b are of different types, and
1 to Y8 are applied only to the VRAM 5a, and the video signals Y9 to Y16 are applied only to the VRAM 5b. Therefore, the images that can be updated within one field period are limited to one of the images based on the image signals Y1 to Y8 and one of the images based on the image signals Y9 to Y16, and the image based on the image signals Y1 to Y8. From the video signals Y9 to Y16. A /
Since the D converters 3a and 3b and the VRAMs 5a and 5b have a one-to-one correspondence, to increase the number of images to be updated within one field period, both of them must be increased.

[0004] Therefore, the main object of the present invention is to provide:
It is an object of the present invention to provide a video output device capable of freely selecting a video to be updated during a field period. Another object of the present invention is to provide a video output device capable of increasing the number of videos to be updated within one field period without adding a VRAM.

[0005]

According to the present invention, there are provided an input terminal for inputting N kinds of first video signals, and M ( 2 ≦ M <N) kinds of first video signals among N kinds of first video signals. Selecting means for selecting from among the M types of first video signals each having N inputs
Input identifying whether the signal input from any of the terminal
Generating means for generating a force terminal information, M kinds of the first video signal of each subjected to reduction processing generating means for generating a second video signal of M kinds, N pieces of divided video memory area is formed, an input A writing unit that writes each of the M types of second video signals into a predetermined divided area based on the terminal information; and a reading unit that reads out the N types of second video signals from the video memory and outputs the same to a monitor. An image output device characterized in that N images based on a second image signal are divided and displayed on a monitor.

[0006]

The multiplexer, for example, 1
For example, two types of video signals to be updated in the next field are selected from the six types of video signals in a predetermined order or combination. The selected two types of video signals are respectively applied to, for example, first and second filters, and the two types of video signals extracted by the first and second filters are applied to, for example, 16 regions by a microcomputer. Is written to a predetermined area of the VRAM. That is, the video signal written in the VRAM is updated by two types for each field. 1 written to VRAM
The six types of video signals are read, for example, by a multiplexer, and a video based on the read video signals is displayed on a predetermined area of a monitor, for example, where the screen is divided into 16 parts. As a result, two types of images are updated on the monitor for each field. Incidentally, if the number of video signals selected by the multiplexer is increased and the number of filters is also increased, the VRAM in one field period is correspondingly increased.
, The number of video signals updated on the monitor increases, and accordingly, the number of video signals updated on the monitor also increases.

[0007]

According to the present invention, any one of the M images displayed on the N display means is updated in accordance with the M kinds of video signals selected by the selection means. The video to be updated can be freely selected, and the number of videos to be updated within one field period can be increased according to the number of video signals selected by the selection means.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0009]

Referring to FIG. 1, a video output device 10 of this embodiment has input terminals P1 to P1 for receiving video signals Y1 to Y16.
P16 includes the multiplexer 12 provided. The multiplexer 12 controls 1
In a predetermined order and a predetermined combination for each field,
Any two types of video signals are selected and output from output terminals P17 and P18. The multiplexer 12 selects a video signal every second, for example, as follows. That is,
The video signals Y1 and Y2 are output from the output terminals P17 and P18 during the first 53 field periods, and then two of the video signals Y3 to Y16 are selected in ascending order of coefficient and output for each field. Multiplexer 12
Also, the input terminal information of the video signal output from the output terminal P17 is provided to the microcomputer 14 from the output terminal P19, and the input terminal information of the video signal output from the output terminal P18 is provided to the microcomputer 14 from the output terminal P20. The input terminal information is 4-bit information indicating from which input terminal a video signal given from the multiplexer 12 is output, and includes input terminals P1 to P16 to video signals Y1 to Y1.
6, "1" is incremented by "1" from "0000" to "1111". The multiplexer 12
Can output video signals Y1 to Y16 from both output terminals P17 and P18.

The video signal output from the output terminal P17 is converted into a digital signal by the A / D converter 16a, and then supplied to the vertical filter block 18a and the microcomputer 14, and the video signals Y1 to Y1 output from the terminal P18.
Y16 is converted into a digital signal by the A / D converter 16b, and then converted to a vertical filter block 18b and the microcomputer 1
4 given. Vertical filter blocks 18a and 1
8b is controlled by the microcomputer 14, and extracts a part of the input video signal. Each of the extracted video signals is provided to VRAMs 20a and 20b,
Is written in a predetermined area in accordance with a write signal from. Note that the write signal includes a write enable signal, a write disable signal, and an address signal to be described later. As shown in FIG. 2, the VRAMs 20a and 20b include Y1 to Y8 areas where the video signals Y1 to Y8 are written and Y9 to Y8 where the video signals Y9 to Y16 are written.
A video signal for one frame of the monitor 26 described later is written therein, including 16 areas. Each area of the VRAMs 20a and 20b has a “column, row” =
It has addresses (0,0) to (180,120), and the address can be initialized only in a specific area by a control signal from the microcomputer 14.

The video signals written in the VRAMs 20a and 20b are read in an interlaced manner by a read signal from a multiplexer 22, and the read video signals pass through a D / A converter 24 as shown in FIG. 720
It is given to the monitor 26 composed of dots × 480 lines. As a result, an image based on the image signals Y1 to Y16 divided into 16 is displayed on the monitor 26. Note that the read signal includes a read enable signal, a read disable signal, and an address signal described later.

FIG. 4 shows the structure of the vertical filter block 18a.
Shown in The video signal output from the A / D converter 16a is supplied to a D / D conversion circuit 28a whose horizontal sampling number is 1/4, whereby the input video signal per line is thinned out to 1/4. . The video signal output from the D / D conversion circuit 28 is provided to the multiplexer 30a and the adder 32a. In the adder 32a, it is added to the previous one-line video signal output from the line memory 34a and halved, and the output of the adder 32a is supplied to the multiplexer 30a. Multiplexer 30
“a” selects one of the output of the DD conversion circuit 28a and the output of the adder 32a in accordance with a control signal from the microcomputer 14. Then, the video signal output from the multiplexer 30a is written into the line memory 34a by a control signal from the microcomputer 14, and is read with a delay of 1H period. Note that the vertical filter block 18b shown in FIG. 5 has the same configuration as the vertical filter block 18a, and thus redundant description will be omitted by substituting a for reference numerals with b.

A table shown in FIG. 6 is written in a RAM 14a included in the microcomputer 14. That is, V
The input terminal information of the video signal to be written in each of the Y1 to Y16 areas of the RAMs 20a and 20b is written, and the VRAM 20a and the current VRAM 20a and 20b correspond to the Y1 to Y8 areas and the Y9 to Y16 areas. A write flag indicating whether or not the video signal is being written is set in the VRAM 20a.
And a field flag indicating whether the video signal written in 20b is an even field or an odd field. As for the write flag, a flag is set when a video signal is currently being written, and as for a field flag, a flag is set when a video signal of an odd field is written.

Referring to FIGS. 7 to 12, a process when the microcomputer 14 controls the vertical filter block 18a and the VRAM 20a will be described. First, step S1
When the input terminal information of the video signal provided to the A / D converter 16a is input at step S3 and the vertical synchronization signal of the video signal is input at step S3,
At 5, the horizontal synchronization signal included in the vertical blanking period of the video signal is detected. Next, in step S7, the line counter 14b included in the microcomputer 14 is reset, and in step S9, it is determined whether the detected vertical synchronization signal and horizontal synchronization signal are in phase. If they are in phase, it is determined that the video signal is of an even field, and the field flag is reset in step S11. If they are not in phase, it is determined that the video signal is of an odd field, and the field flag is determined in step S13. Set a flag. When the processing in step S11 or S13 is completed, the multiplexer 30a is controlled in step S15 to select the output of the D-D conversion circuit 28a, and in step S17, the detection of the horizontal synchronization signal is waited. Increment. The horizontal synchronization signal detected in step S17 is a signal added before the video signal to be written to the line memory 34a.

Subsequently, a write enable signal is output to the line memory 34a in step S21, and the data counter 14c is reset in step S23. Thereafter, in step S25, the data counter 1
4c is determined to be 180 or not, and “N
If O ", the data counter 14c is incremented in step S27 and the process returns to step S25.
If "YES", a write disable signal is output to the line memory 34 in step S29. Thereafter, it is determined whether or not the field flag is set in step S31. If "NO", it is determined in step S33 whether or not the most significant bit of the input terminal information is "0". If "YES", A
The video signal supplied to the / D converter 16a is determined to be one of Y1 to Y8, and the process proceeds to FIG. 9, and if "NO", the video signal is determined to be one of Y9 to Y16 in FIG. Transition. On the other hand, if "YES" in the step S31, the multiplexer 30a is controlled to select the output of the adder 32a in a step S35, and after waiting for the detection of the horizontal synchronizing signal in a step S37, the line counter 14 is determined in a step S39.
b is reset once and incremented. Note that also in step S37, the horizontal synchronization signal to be detected is added before the video signal to be written to the line memory 34a.

Subsequently, in step S41, a read enable signal is output to the line memory 34a, and immediately after that, a write enable signal is output.
Therefore, in the line memory 34a, the video signal output from the DD conversion circuit 28a and written in the line memory 34a is read, and immediately thereafter, the adder 32a
The video signal output from is written. However, at this time, since neither the VRAMs 20a and 20b are write-enabled, the video signal read from the line memory 34a is not written to the VRAM 20a or 20b. After the processing in step S41 is completed, the data counter 14c is next processed in step S43.
Is reset, and it is determined in step S45 whether or not the count value of the data counter 14c is 180. If "NO", the data counter 14c is incremented in step S47 and the process returns to step S45. If "YES", the process proceeds to step S49.
1 outputs a read disable signal and a write disable signal to the line memory 34a.
Move to 1.

Next, in step S51 of FIG.
It is determined whether the write flag for the VRAM 20a has been reset, and if “YES”, the process proceeds to a step S51.
Sets this write flag. Subsequently, in step S55, a write enable signal is output to the VRAM 20a, and a read enable signal is output to the line memory 34a. Thereafter, in step S57, the area corresponding to the input terminal information is searched by comparing the input terminal information given to the microcomputer 14 from the output terminal P19 of the multiplexer 12 with the input terminal information written in the RAM 14a. Initialize the address. Subsequently, in step S59, the data counter 14c is reset, and in step S61, it is determined whether or not the count value of the data counter 14c is 180. If "NO", in step S63, the column address and the data counter of the area searched in step S57 are incremented, and step S6 is executed.
Returning to step 1, if "YES", a write disable signal is output to the VRAM 20a and a read disable signal is output to the line memory 34a in step S65. Thus, the writing of the video signal read from the line memory 34a into the VRAM 20a ends.

Subsequently, in step S67, the row address of the area searched in step S57 is incremented, and in step S69, the detection of the horizontal synchronizing signal is waited, and in step S71, the line counter 14b is incremented. Thereafter, in step S73, it is determined whether or not the count value of the line counter 14b is 240. If "NO", the process returns to step S15.
If "YES", in step S75 the VRAM
The write flag for 20a is reset, and step S
Return to 1. Therefore, the video signal following the horizontal synchronization signal detected in step S69 is not written in the line memory 34a. If "NO" in the step S33, steps S77 to S101 in FIG.
The processing shifts to steps S77 and S79.
Since the write flag in steps S101 and S101 is for the VRAM 20b, and steps S81 and S91 are the same as steps S51 to S75 shown in FIG. 8 except that the processing is performed on the VRAM 20b, duplicate descriptions are omitted. I do.

Upon completion of the process in step S49,
In step S103 shown in FIG. 11, it is determined whether or not the most significant bit of the input terminal information provided from the output terminal P19 of the multiplexer 12 is “0”. And
If "NO", it is determined that the video signal given to the A / D converter 16a is any of Y9 to Y16, and the process proceeds to FIG. On the other hand, if “YES”, the A / D converter 16
Assuming that the video signal given to a is any of Y1 to Y8, the process waits until the write flag for VRAM 20a is reset in step S105, and then sets this write flag in step S107. Next, in step S109, a write enable signal is output to the VRAM 20a and the line memory 34a
And outputs a read enable signal to
In step 11, by comparing the input terminal information given to the microcomputer 14 with the input terminal information written in the RAM 14a, an area corresponding to the input terminal information is searched, and the address of this area is initialized.

Subsequently, in step S113, the data counter 14c is reset, and in step S115, it is determined whether or not the count value of the data counter 14c is 180. If "NO" here, a step S1 is performed.
In step 17, the column address of the area searched in step S111 and the data counter 14c are incremented, and the process returns to step S115. If "YES", a write disable signal is output to the VRAM 20a in step S119, and the line memory 34a is output. Outputs a read disable signal. Thus, the writing of the video signal read from the line memory 34a into the VRAM 20a ends. afterwards,
In step S121, the row address of the area searched in step S111 is incremented, and in step S123, it is determined whether or not the count value of the line counter 14b is 240. If "NO", the process returns to the step S15, but if "YES",
In step S125, the write flag for the VRAM 20a is reset, and the process returns to step S1. If “NO” in the step S103, the processes in the steps S127 to S147 shown in FIG. 12 are performed, which is performed in the steps S127, S129, and S1.
The write flag in 47 is for the VRAM 20b, and is the same as steps S105 to S125 except that processing is performed on the VRAM 20b in steps S131 and S141, and duplicate description is omitted.

7 to 12 described above correspond to the vertical filter block 18a and the VRAMs 20a and 2a.
0b, and the vertical filter block 18b
And VRAMs 20a and 20b are processed according to different flows. However, the vertical filter block 18b and V
The processing for the RAMs 20a and 20b is shown in FIGS.
Since it is almost the same, only the differences are explained,
A duplicate description of the same points will be omitted. The difference is that the input terminal information and the vertical synchronizing signal of the video signal supplied to the A / D converter 16b are detected in steps S1 and S3, and steps S7, S19, S3
9, line counter 14d in S71 and S97
And steps S23, S27, S43,
S47, S59, S63, S85, S89, S113,
In S117, S135 and S139, processing is performed on the data counter 14b.

By processing by the microcomputer 14 in this manner, for example, the video signal Y3 of the even field and the video signal Y5 of the odd field sequentially applied to the vertical filter block 18a are processed as shown in FIG. Written. That is, when the even field of the video signal supplied from the A / D converter 16a to the vertical filter block 18a is represented by ○ and the odd field is represented by ×, the interlacing relationship is represented as (A). First of all, the video signal Y3 of the even field
Is applied to the vertical filter block 18a, (B)
The video signal Y3 is processed as shown in FIG. That is, the multiplexer 30a selects the output from the DD conversion circuit 28a, and the line memory 34a writes and reads the output of the multiplexer 30a every other line. Then, the VRAM 20a writes the video signal Y3 read from the line memory 34a into the Y3 area. Therefore, the video signal Y3 for 120 lines is written in the Y3 area.

The video signal Y3 thus written
Is read out by scanning the VRAM 20a in an interlaced manner, whereby a signal represented by ◎ becomes an even field signal of the monitor 26, and a signal represented by △ becomes an odd field signal. Thus, an image for one frame on the monitor 26 is created based on the image signal for one field output from the multiplexer 12. The reason why the video signals for 120 lines are written in the respective areas of the video RAMs 20a and 20b in this manner is that the microcomputer 14 uses the VRAMs 20a and 20b.
0b and VRAM by multiplexer 22
This is because reading from 20a and 20b is independent of each other, and synchronization between the two cannot be achieved.

Subsequently, when the video signal Y5 of the odd field is supplied to the vertical filter block 18a, the video signal Y5 is processed as shown in FIG. That is, the output (X) of the DD conversion circuit 28a and the output (◇) of the adder 32 are given to the multiplexer 30a, and one of them is alternately selected by the multiplexer 30a. The output of the multiplexer 30a is temporarily stored in the line memory 3
4 and then read. However, VRAM2
Since the write enable signal is given to 0a only when the output of the adder 32a is read from the line memory 34, the output of the adder 32a is written in the Y5 area of the VRAM 20a. Also at this time, the video signal Y5 for 120 lines is written in the Y5 area in the same manner as described above.

FIGS. 14 to 16 show video signals read from the line memories 34a and 34b included in the vertical filter blocks 18a and 18b, both of which have the same VRA.
It is a timing chart at the time of writing to M20a or 20b. (A) is a timing chart in the line memory 34a, and (B) is a timing chart in the line memory 34b.

Referring to FIG. 14, video signals of even fields are simultaneously written to line memories 34a and 34b, and then a write flag is set to write the video signals written to line memory 34a to VRAM 20a. Then, the video signal written in the line memory 34a is read out and written in a predetermined area of the VRAM 20a. Subsequently, the video signal written in the line memory 34b is read out after the write flag is reset, and written into a predetermined area of the VRAM 20a. Therefore, after the video signal is written to the line memories 34a and 34b,
The processing until the data is written to 20a is completed within the 1H period. Subsequently, at intervals of 1H, a video signal is again written to the line memories 34a and 34b at the same time. Thereafter, when a write flag is set for writing the video signal written in the line memory 34a to the VRAM 20a in the same manner as the previous time, the line memory 34a is set.
The video signal written in a is first written in a predetermined area. Then, after resetting the write flag, the video signal of the line memory 34b is written to a predetermined area of the VRAM 20a.

The difference between the write time and the read time is that the write data is data that is thinned out to 1/4 and has a fixed interval, whereas the read data has no interval. Because it is dense data. Therefore, if the clock rates for reading and writing are the same, the reading time is な る of the writing time. Referring to FIG. 15, line memories 34a and 34b have DD conversion circuits 28a and 28
When the video signals of the odd fields output from 8b are simultaneously written, both signals are simultaneously read from the line memories 34a and 34b with a delay of 1H period. Almost simultaneously with the reading, the video signals output from the adders 32a and 32b are written to the line memories 34a and 34b. Since this video signal needs to be written to a predetermined area of the VRAM 20a or 20b, the video signal is read from one line memory and written to the VRAM 20a or 20b in the same manner as described above, and then the video signal is read from the other line memory. And read VRA
Write to M20a. Thereby, the line memory 34a of the video signal output from the adders 32a and 32b
And reading from the line memories 34a and 34b, that is, writing to the VRAM 20a or 20b is completed within the 1H period.

Referring to FIG. 16, an odd field video signal is applied to line memory 34a, and
The operation when the video signal of the even field is supplied to 4b will be described. If the writing of the video signal output from the adder 32a to the line memory 34a and the writing of the video signal of the even field output from the D-D conversion circuit 28b to the line memory 34b are performed simultaneously,
VRAM for writing video signal of odd field
When the write flag for 20a is set, the video signal of the odd field is first read from the line memory 34a and written to a predetermined area of the VRAM 20a. Then, after waiting for the reset of the write flag, the video signal of the even field is read out from the line
The data is written in a predetermined area of M20a. Then, the next 1
When an odd field video signal output from the DD conversion circuit 28a is written to the line memory 34a during the H period, nothing is written to the line memory 34b. Then, immediately before the video signal output from the adder 32a is written to the line memory 34a, the video signal of the odd field written to the line memory 34a is read. Thus, the vertical filter blocks 18a and 1
8b are the same VRAM
When writing to 20a or 20b, one is written prior to the other.

In operation, video signals Y1 and Y2 are output from the output terminals P17 and P18 of the multiplexer 12 in the first 53 field periods, and are passed through the vertical filter blocks 18a and 18b to the VRAM 20a.
Are written in the Y1 area and the Y2 area. From the output terminals P17 and P18 of the multiplexer 12,
Video signals Y3 and Y4, Y5 and Y6,..., Y15 and Y16 are output for each field,
The data is written in a predetermined area of the AM 20a or 20b.
Therefore, the Y1 area and the Y2 area are updated continuously 53 times every seven fields, and the Y3 area to the Y16 area are updated once every 60 fields. The VRAMs 20a and 20b are scanned in an interlaced manner by the multiplexer 22, and the video signals Y
1 to Y16 are output to the monitor 26. Therefore, the images in the Y1 area and the Y2 area of the monitor 26 are almost normal moving images, but the images in the Y3 to Y16 areas are strobe images.

According to this embodiment, the multiplexer 12
From the terminals P17 and P18 of the video signal Y1
To Y16 and the video signals output from the vertical filter blocks 18a and 18b are all VRAM2.
0a and 20b. Therefore, it is possible to freely select a video to be updated on the monitor 26 according to a method of selecting a video signal in the multiplexer 12.

In this embodiment, the multiplexer 1
Video signals Y1 and Y2 continuously from 2 to 53 fields
, And the video signals Y3 to Y1 in the subsequent seven fields
6 are output two by two, but it is needless to say that the present invention can be applied to a case where the video signals Y1 to Y16 are output in any combination or order. Also,
As shown in FIG. 17, A / D converters 16c and 16d, vertical filter blocks 18c and 18d, and microcomputer 3
6 are newly provided, the video signals Y1 to Y8 are output from the terminals P17 and P18 of the multiplexer, the video signals Y9 to Y16 are output from the terminals P21 and P22, and the outputs of the vertical filter blocks 18a and 18b are output only to the VRAM 20a. And outputs from the vertical filter blocks 18c and 18d to the VRAM 20b.
, Only two images in the Y1 to Y8 regions and two images in the Y9 to Y16 regions of the monitor 26 can be updated within one field period.

Furthermore, in the embodiment shown in FIG. 1, the case where two A / D converters and two vertical filter blocks are provided has been described. However, the number of A / D converters and vertical filter blocks is increased, If the filter block and the VRAM are controlled by one microcomputer, the number of images that can be updated within one field period can be increased according to the number of A / D converters and vertical filter blocks. However, in this case, it is necessary to increase the reading speed of the line memory and the writing speed to the VRAM according to the number of A / D converters and vertical filter blocks.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a VRAM;

FIG. 3 is an illustrative view showing a monitor;

FIG. 4 is a block diagram showing a vertical filter block.

FIG. 5 is a block diagram showing a vertical filter block.

FIG. 6 is an illustrative view showing contents of a RAM;

FIG. 7 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 8 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 9 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 10 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 11 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 12 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 13 is an illustrative view showing one portion of an operation of the embodiment in FIG. 1;

14A is a timing chart showing writing and reading of the line memory 34a, and FIG. 14B is a timing chart showing writing and reading of the line memory 34b.

FIG. 15A is a timing chart showing writing and reading of the line memory 34a, and FIG. 15B is a timing chart showing writing and reading of the line memory 34b.

FIG. 16A is a timing chart showing writing and reading of the line memory 34a, and FIG. 16B is a timing chart showing writing and reading of the line memory 34b.

FIG. 17 is a block diagram showing another embodiment of the present invention.

FIG. 18 is a block diagram showing a conventional technique.

FIG. 19 is an illustrative view showing a part of a conventional technique;

FIG. 20 is an illustrative view showing a part of the related art;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Video output device 12, 22, 30a, 30b ... Multiplexer 18a-18d ... Vertical filter block 20a-20c ... VRAM 28a, 28b ... DD conversion circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/262-5/268 H04N 5/91-5/93 H04N 5/45 H04N 7/18

Claims (2)

(57) [Claims] 1. N input terminals for inputting N types of first video signals, wherein M ( 2 ≦ M <N) types of first video signals are selected from the N types of first video signals. Selecting means, wherein each of the M types of first video signals is the N input terminals
Input terminal to identify which signal is input from
Generating means for generating child information, performing reduction processing on each of the M types of first video signals to obtain M
Generating means for generating a second video signal of a type; a video memory in which N divided areas are formed; and writing and writing each of the M types of second video signals to the predetermined divided area based on the input terminal information means,
And reading means for reading N kinds of the second video signals from the video memory and outputting them to a monitor, wherein N images based on the N kinds of the second video signals are divided and displayed on the monitor. A video output device, characterized by the following. 2. The video memory comprises a plurality of memories having less than N divided areas, each of which is assigned a flag which is set during a writing period of the second video signal. A writing unit that specifies a writing destination of the second video signal based on the input terminal information; and a signal writing unit that writes the second video signal when the flag assigned to the writing destination is in a reset state. 2. The video output device according to claim 1, comprising means.