JP3145292B2 - Digital signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital signal processing circuit in which the digital signal processing circuit itself has reduced adverse effects such as noise on peripheral circuits.

[0002]

2. Description of the Related Art When a digital signal processing circuit performs a predetermined amount of signal processing within a predetermined time, the processing is usually started with a certain reference signal as a trigger. Here, as an example of the digital signal processing circuit, a case will be described in which processing is started with both edges of the reference signal as a trigger,
The same applies when one edge is used as a trigger.

[0003] As shown in FIG. 4, when five processes of processing units a1 to a5 are performed within a trigger input period T of a reference signal, the conventional circuit uses the rising edge of the reference signal,
Alternatively, the processing of the processing unit a1 is started with the falling edge as a trigger (at time t0 in FIG. 4). When the processing unit a1 ends, the processing units a2 to a5 are successively processed. When all processing is completed, the digital signal processing circuit stops the execution of the instruction code by stopping the system clock or the like, or repeats the non-operation processing, and the period until the next trigger is the stop period. (Period from t1 to t2 in FIG. 4). Note that the time required to execute the processing units a1 to a5 differs depending on various factors such as, for example, a value to be calculated and a state of an internal operation unit. Therefore, the maximum required time is guaranteed, but the actual required time cannot be specified in many cases.

[0004] Similarly, in the next cycle, the digital signal processing circuit continuously performs the processing of the processing units b1 to b5. After the operation period, a stop period is set until the next trigger is input. The digital signal processing circuit
Such a cycle is repeated by using the reference signal as a trigger.

Incidentally, in the digital signal processing circuit, a larger current consumption is required in the operation period than in the stop period, and the current consumption fluctuates with the start and stop of the operation. In particular, when the digital signal processing circuit has an internal operation unit such as a multiplier having a large circuit scale, and these operation units simultaneously operate or stop,
There is a large current consumption difference between the operation period and the stop period of the digital signal processing circuit. As a result, as shown in FIG. 4C, the current consumption of the digital signal processing circuit changes, and the cycle of the change is the trigger input cycle T of the reference signal.

[0006]

However, in the above-mentioned conventional digital signal processing circuit, a power supply circuit for supplying a constant voltage to the digital signal processing circuit due to fluctuations in current consumption and noise caused by the fluctuations, etc. There has been a problem that peripheral circuits such as an analog circuit which receives power supply from a power supply are not adversely affected.

Generally, a peripheral circuit has a specific frequency band that is more susceptible to noise than other frequency bands. Therefore, if the fluctuation period of the current consumption falls within this frequency band, there is a possibility that the peripheral circuits will be seriously affected.

For example, audio circuits are susceptible to noise in the audible band. Therefore, in the audio circuit, when the fluctuation period is in the audible band, it adversely affects peripheral circuits as audible noise, causing a serious problem.

In addition, in order to operate peripheral circuits stably even when the current consumption of the digital signal processing circuit fluctuates,
Peripheral circuits need to be strengthened. Therefore, the power supply circuit is strengthened to suppress and stabilize the power supply voltage fluctuation,
The analog circuit section has been strengthened so as to be less susceptible to noise. As a result, there is also a problem that the cost of a device including the digital signal processing circuit is increased.

The present invention has been made in view of the above problems, and an object of the present invention is to reduce adverse effects on peripheral circuits such as noise in a digital signal processing circuit.

[0011]

According to a first aspect of the present invention, a digital signal processing circuit executes a plurality of small unit processes one after another when a reference signal is input. After that, in the digital signal processing circuit having the arithmetic processing means which waits until the next reference signal input, the control means for causing the arithmetic processing means to temporarily suspend the processing of the small unit processing at least once every input cycle of the reference signal. It is characterized by having.

The arithmetic processing means includes, for example, a program ROM (Read-Only Memory) storing an instruction code.
y), data ROM, working RAM (Random acce
ss Memory), an arithmetic unit, various registers, and the like, and the current consumption during operation is larger than that during stop.

In the above configuration, when the reference signal is input, the arithmetic processing means starts operation and executes a plurality of small unit processes one after another. Further, the control means may stop the clock supplied to the arithmetic processing means at least once every input cycle of the reference signal, for example, or instruct the arithmetic processing means to repeat the non-operation instruction, thereby performing the arithmetic processing. Stop the means.

Thereafter, the control means starts the operation of the arithmetic processing means by, for example, restarting the supply of the clock. When all the small unit processes have been completed, the arithmetic processing means waits until the next reference signal is input.

Thus, in one input cycle of the reference signal, the number of times the arithmetic processing means starts or stops operating increases as compared with the conventional case. Therefore, the digital signal processing circuit can change the fluctuation frequency of the current consumption due to the start and stop of the operation of the arithmetic processing means to a higher frequency side as compared with the conventional digital signal processing circuit.

Therefore, the digital signal processing circuit can remove the fluctuation frequency of the current consumption from a specific frequency band that easily affects peripheral circuits, such as an audible band in an audio circuit. Therefore, for example, adverse effects of the digital signal processing circuit itself on peripheral circuits, such as audible noise in an audio circuit, can be reduced.

Further, since the influence on the peripheral circuit is reduced, the resistance to noise can be set lower than in the conventional circuit, for example, in a peripheral circuit such as a power supply circuit or an analog circuit. As a result, the configuration of the peripheral circuit can be simplified, and the cost required for manufacturing can be reduced.

According to a second aspect of the present invention, there is provided a digital signal processing circuit according to the first aspect of the present invention, wherein the arithmetic processing means starts the next small unit processing. And a next processing start time designation means for designating the control means. Further, the control means causes the arithmetic processing means to wait on standby from the end of each small-unit processing to the next processing start time designated by the next processing start designation means.

In the above arrangement, the next processing start time designation means instructs the next processing start time to the control means before the arithmetic processing means ends each small unit processing. Further, the control means stops the arithmetic processing means at the time when each small unit processing is completed. When the next processing start time is reached with the arithmetic processing means stopped, the control means causes the arithmetic processing means to start the next small unit processing.

Therefore, the arithmetic processing means temporarily stops after the completion of each small unit processing. Thereby, in the input cycle of the reference signal, the arithmetic processing means repeats the operation start / stop more frequently than the digital signal processing circuit according to the first aspect. The operation is stopped at the end of each small unit process. Therefore, the control means can surely temporarily stop the arithmetic processing means.

Thus, the digital signal processing circuit can reliably change the fluctuation frequency of the current consumption to a higher frequency. Therefore, the digital signal processing circuit can more reliably change the fluctuation frequency of the current consumption to outside the specific frequency band, and can surely reduce the adverse effect on the peripheral circuits.

According to a third aspect of the present invention, in the digital signal processing circuit according to the second aspect of the present invention, in the configuration of the second aspect, the next processing start time setting means is configured such that the arithmetic processing means has a small capacity. The next processing start time calculated based on the time when the unit processing is started is designated to the control means.

Therefore, even when the time required to execute each small unit process changes, the time when the arithmetic processing unit starts the next small unit process does not change. As a result, it is possible to manage the point in time when the arithmetic processing unit starts each small unit process. In particular, since the start point of the last small unit process can be determined regardless of the time required for each small unit process, it is easily and reliably assured that all the small unit processes are completed within one input cycle of the reference signal. it can.

If the time interval from the start of each small unit process to the start of the next small unit process is set to be the same as the maximum required time of each small unit process, the processing speed of the digital signal processing circuit is reduced. Therefore, adverse effects on peripheral circuits can be reduced.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
The following is a description based on FIG. The digital signal processing circuit according to the present embodiment is provided to, for example, an audio circuit and is realized as a part of a digital signal processing processor (hereinafter, referred to as a DSP).

As shown in FIG. 1, the DS according to this embodiment
P is DS based on a reference signal received from the outside via the interface 1, such as system clocks S1 and S2 (hereinafter simply referred to as clocks S1 and S2).
A clock generator (control means) 2 for generating a system clock used inside P, and an arithmetic processing unit (arithmetic processing means) 3 for sequentially executing a series of small unit processes while the clock S1 is supplied. ing.

The arithmetic processing unit 3 includes, for example, a multiplier and an A
Operation units such as LU (Arithmetic and Logical Unit), ROM (Read-Only Memory) and RA
M (Random Access Memory) and the like, and are controlled by a program counter 4, a program ROM 5, and a decoder (next processing start specifying means) 6 which operate in synchronization with the clock S1.

More specifically, the above-described small unit processes are stored in the program ROM 5 as instruction codes in advance. When the program counter 4 indicates the storage address of the instruction code to be executed next to the program ROM 5,
The decoder 6 decodes the instruction code and sends a control signal to the arithmetic processing unit 3. Thereby, the arithmetic processing unit 3 can execute the small-unit processing corresponding to the instruction code according to the clock S1. When the processing is completed, the program counter 4 increases the count value.

Note that each small unit process and instruction code are 1
It may correspond to one-to-one, or one small unit process may be constituted by a plurality of instruction codes. Also,
Hereinafter, for convenience of explanation, a case will be described in which the arithmetic processing unit 3 executes five small-unit processes for each input cycle of the reference signal. However, the present invention is not limited to this, and the number of small-unit processes can be freely set. .

The program counter 4 is initialized by the clock generator 2 every time a reference signal is input. Therefore, the arithmetic processing unit 3 can execute a series of small unit processes based on the instruction code stored in the program ROM 5 every time a reference signal is input.

The clock generator 2 controls oscillation / stop of the clocks S1 and S2. Thus, other circuits operating in synchronization with the clocks S1 and S2 can be operated or stopped. For example, when the arithmetic processing unit 3 completes all processing, the clock generator 2
Stops generating the clock S1. As a result, the circuits 3, 4, 5, and 6 are stopped, and current consumption can be reduced.

Further, the DSP according to the present embodiment is provided with a step counter 7, a register 8, and a comparator 9 in order to control the timing at which the arithmetic processing unit 3 starts each small unit process. These step counter 7, register 8 and comparator 9 correspond to the control means described in the claims.

The step counter 7 operates at the clock S2
Can be counted. The step counter 7 is cleared to 0 each time the reference signal is input by the clock generator 2. Thus, the time elapsed since the input of the reference signal can be measured. Assuming that the trigger input cycle in the reference signal is T and the cycle of the clock S2 is c, T / c pulses are generated in the clock S2 for each cycle T. Therefore, the step counter 7 determines that the maximum count value Nmax is T / c,
It has a bit number that can count max.

The register 8 is provided from the decoder 6
The next processing start step value sent in synchronization with the clock S1 can be held. The next processing start step value is calculated by the arithmetic processing unit 3
Indicates the time point at which the next small unit process starts, and is represented by the count value indicated by the step counter 7 at the time point when the next process starts.

Further, the comparator 9 compares the count value indicated by the step counter 7 with the next processing start step value held by the register 8 in synchronization with the clock S2. If they match, the comparator 9 determines that the next processing start time has come, and causes the clock generator 2 to start supplying the clock S1. Thereby, the arithmetic processing unit 3 starts the next small unit processing.

On the other hand, the next processing start step value is set in the register 8 by the decoder 6. That is, the program ROM 5 is provided with an area for storing each next processing start step value, and in this area, the next processing start step value corresponding to each small unit processing is stored in advance. The decoder 6 according to the present embodiment can read the next process start step value corresponding to each small unit process from the area of the program ROM 5 and set it in the register 8 every time the arithmetic processing unit 3 starts the small unit process.

In the present embodiment, the starting point of the next process of each small unit process is set based on the case where the arithmetic processing unit 3 takes the longest time to execute the small unit process. Therefore, the next process start step value of each of the above small unit processes is:
This is the sum of the maximum number of steps of the small-unit processing and the maximum number of steps of the small-unit processing executed so far.

For example, if the maximum number of steps of the small unit processes a1 to a5 is M1 to M5, and the next process start step value is N1 to N5, the next process start step value N1 of the small unit process a1 is M1. Is set. N2 = M1 + M2, N3 = M1 + M2 + M
3, and N4 = M1 + M2 + M3 + M4. Note that the clock generator 2 according to the present embodiment stops the clocks S1 and S2 when the arithmetic processing unit 3 completes the last small unit processing a5. Therefore, N5 is set to a value that the step counter 7 does not indicate after the setting of N5, such as Nmax or 0.

Further, the decoder 6 according to the present embodiment
Can instruct the clock generator 2 to stop supplying the clock S1 when the arithmetic processing unit 3 completes each small unit process. As a result, the arithmetic processing unit 3 stops until the next clock S1 is supplied each time each small unit process is completed.

In the DSP having the above configuration, the operation of each unit at the time of arithmetic processing will be described with reference to the timing chart shown in FIG. 3 and the flowchart shown in FIG.
The following is a description of each step.

That is, the first step 1 (hereinafter, referred to as
Interface 1 is abbreviated as S1).
It determines whether there is a reference signal input, and waits until a reference signal serving as a trigger, such as rising or falling, is input.

When the interface 1 detects the input of the reference signal, the clock generator 2 initializes the program counter 4 and the step counter 7 (S
2). As a result, the count values of the program counter 4 and the step counter 7 are initialized to 0 (see FIG. 3).
At time t0 shown in FIG.

The clock generator 2 oscillates the clock S1 and the clock S2 (S3). As a result, the clock S2 is supplied to the step counter 7 and the comparator 9. Thus, as shown in FIG. 3B, the count value of the step counter 7 increases with the passage of time while the clock S2 is supplied.
On the other hand, a clock S1 is supplied to the arithmetic processing unit 3, the program counter 4, the program ROM 5, the decoder 6, and the register 8. As a result, as shown in FIG. 3C, the arithmetic processing unit 3 starts operating in synchronization with the clock S1.

In S4, the program counter 4, the program ROM 5, and the decoder 6 identify a small unit process to be processed next by the arithmetic processing unit 3 according to the clock S1, and instruct the arithmetic processing unit 3. That is, the address indicated by the program counter 4 is supplied to the program ROM 5 every time the clock S1 is counted. The program ROM 5 reads out the instruction code stored at the given address and sends it to the decoder 6. The decoder 6 decodes the instruction code and sends out a control signal to a multiplier, an ALU, a ROM, a RAM, and the like that constitute the arithmetic processing unit 3. In S5, the decoder 6 reads the next processing start step value from the program ROM 5 and stores it in the register 8.

For example, at time t0 shown in FIG. 3, the program counter 4 indicates the storage address of the instruction code corresponding to the small unit processing a1. Therefore, the arithmetic processing unit 3 starts the execution of the small unit processing a1 based on the control signal sent from the decoder 6. Further, the decoder 6 sets the next processing start step value N1 corresponding to the small unit processing a1 in the register 8.

On the other hand, the arithmetic processing section 3 performs small unit processing based on the control signal received from the decoder 6 in S4. Further, the decoder 6 determines whether or not the small unit processing of the arithmetic processing unit 3 has been completed, and waits until the execution is completed (S6). Since the clock S2 is supplied during this time, the count value of the step counter 7 is increasing (period from t0 to t1).

When the processing is completed, the decoder 6 determines whether or not there is another small unit processing that needs to be executed within the cycle T of the reference signal, depending on whether or not new data is given from the program ROM 5. Is determined (S7).
If there is next small unit processing, clock generator 2
Stops the clock S1 (S8). This allows
The arithmetic processing unit 3 and the program counter 4 stop operating (at time t1 shown in FIG. 3).

On the other hand, the clock generator 2 continues to supply the clock S2. Therefore, the count value of the step counter 7 increases with time.
In S9, the comparator 9 compares the next processing start step value set in the register 8 in S5 with the count value of the step counter 7 for each count, and waits until the values match. In this state, since the clock S1 is not supplied, the arithmetic processing unit 3 is stopped.

For example, at time t1 shown in FIG. 3, the register 8 holds N1 as the next processing start step value. Therefore, after the execution of the small unit process a1, the arithmetic processing unit 3 increases the count value of the step counter 7 to N
It waits until it becomes 1, that is, t2.

If they match, that is, when it is time to start the next process, the process returns to S3 and the clock generator 2
Restarts the supply of the clock S1 (at time t2 shown in FIG. 3). After that, the processing after S4 is executed, and the arithmetic processing unit 3 executes the next small unit processing.

Steps S3 to S9 are repeated for each small-unit process. After executing a certain small-unit process, the DSP performs a next small-unit process after a short stop period. Thus, the arithmetic processing unit 3 executes the small unit processes a2 to a5 during the period from t2 to t3 shown in FIG. As a result, as shown in FIG. 3D, in the DSP according to the present embodiment, the fluctuation frequency of the current consumption is about five times that of the conventional DSP shown in FIG. Shift to higher frequency side. Note that, in the present embodiment, the processing performed by the arithmetic processing unit 3 is divided into five small unit processes for each input cycle of the reference signal. Can move to higher frequency side. The number of the small unit processes can be freely determined from the ratio between the frequency of the reference signal and the frequency after the movement.

When all the small unit processes have been completed (S
7 (YES), in S10, the clock generator 2 stops both clocks S1 and S2 (at time t3 shown in FIG. 3). After that, returning to S1, the DSP waits until the next reference signal is input. This gives D
SP is set to S1 to S for each trigger input of the reference signal.
Step 10 is repeated.

In this embodiment, when all the small unit processes are completed, the clock generator 2
2 is stopped, the count value of the step counter 7 does not increase after t3 as shown in FIG. 3B.

As described above, the DSP according to this embodiment
Is a clock generator 2 that operates or stops the arithmetic processing unit 3 depending on whether or not the clock S1 is supplied.
A decoder 6 for setting the next processing start step value in the register 8 in accordance with the small unit processing; a step counter 7 for measuring time; a register 8 for holding the next processing start step value; ing. Thus, the clock generator 2 stops the arithmetic processing unit 3 each time the arithmetic processing unit 3 completes each small unit process, and when the values indicated by the step counter 7 and the register 8 match, When it is time to restart the processing of the unit 3, the comparator 9 instructs the clock generator 2 to restart the operation of the arithmetic processing unit 3.

Therefore, the DSP according to the present embodiment is
The arithmetic processing unit 3 can be stopped from the end of each small unit process to the time indicated by the next process start step value.
As a result, the fluctuation frequency of the current consumption of the DSP due to the start and stop of the operation of the arithmetic processing unit 3 can be changed to a higher frequency side as compared with the related art.

When the DSP is supplied to an audio circuit and the current consumption of the DSP fluctuates at a frequency in the audible band, a power supply circuit for supplying a constant voltage to the DSP or a circuit for receiving power supply from the power supply circuit In a peripheral circuit (not shown), the fluctuation of the current consumption has an adverse effect as audible noise, and becomes a serious problem.

However, in the DSP according to the present embodiment,
Since it is possible to change the fluctuation frequency of the consumption current and move the current out of the audible band, it is possible to reduce the adverse effect on the peripheral circuits.
Therefore, the peripheral circuit can set the resistance to noise lower than before. As a result, the peripheral circuit does not require the enhancement of the circuit as compared with the related art, and the manufacturing cost of the device provided with the DSP, such as the audio circuit, can be reduced.

Note that, in the DSP according to the present embodiment, the clock generator 2 performs
The operation of the arithmetic processing unit 3 is interrupted until the instruction from the comparator 9 is given, but the present invention is not limited to this. For example, the arithmetic processing unit 3 may be interrupted every time some small unit processing is completed. Further, the processing may be interrupted while the arithmetic processing unit 3 is executing the small unit processing. By suspending the arithmetic processing unit 3 at least once every input cycle of the reference signal, the same effect as in the present embodiment can be obtained.

However, when the arithmetic processing unit 3 is temporarily stopped at the end of each small-unit processing, the operation start and stop of the arithmetic processing unit 3 occur more frequently. Therefore,
The DSP can set the fluctuation frequency of the current consumption to a higher band. As a result, the fluctuating frequency can be changed more flexibly,
It can move out of the audible band without fail. As a result, the adverse effect on the peripheral circuit can be reduced more reliably. Also,
The point at which the arithmetic processing unit 3 stops can be specified at the end of each small unit process. Therefore, for example, when there is a period in which a malfunction occurs when the arithmetic processing unit 3 stops, such as while the arithmetic processing unit 3 is executing a specific instruction code, the stop of the arithmetic processing unit 3 during the period can be prevented. .

In this embodiment, the period from the start of each small unit process to the start of the next small unit process is determined, but the present invention is not limited to this. For example, the arithmetic processing unit 3 may be stopped for a predetermined period after the small unit processing is completed. However, if the time required for each small unit process in the arithmetic processing unit 3 changes, the time from the input of the reference signal to the start of each small unit process changes, so that the arithmetic processing unit 3 executes each small unit process. It is difficult to specify the period. As a result, for each input cycle of the reference signal, the arithmetic processing unit 3
It is difficult to guarantee whether each small unit process can be completed.

However, the step counter 7 according to the present embodiment is initialized each time the reference signal is input, and can measure a period from the input of the reference signal to the start of each small-unit processing. As a result, the arithmetic processing unit 3 can always start the next small unit process from a fixed point in time regardless of the time required for each small unit process. Therefore, the period during which the arithmetic processing unit 3 executes each small unit process can be specified more reliably. As a result, the suspension period of the arithmetic processing unit 3 can be reliably suppressed within an allowable range, and it can be easily assured that the arithmetic processing unit 3 completes all the small-unit processing within the input cycle of the reference signal.

By setting the sum of the maximum number of steps of each small unit process as the next process start step value,
The fluctuation frequency of the current consumption can be changed without lowering the processing speed of the DSP. When the arithmetic processing unit 3 executes the small unit process with the maximum number of steps, the arithmetic processing unit 3 does not stop at the end of the small unit process. Therefore, if such a case continues, the fluctuation frequency does not increase and a problem occurs. However, when the arithmetic processing unit 3 executes the small-unit processing with the maximum number of steps, it is a specific case, so that there is usually no problem.

Note that the decoder 6 according to the present embodiment
Based on the data stored in advance in the program ROM 5,
Although the next processing start step value is set in the register 8,
It is not limited to this. The decoder 6 may calculate the next processing start step value in accordance with the small-unit processing executed by the arithmetic processing unit 3 and set the calculated value in the register 8. Furthermore, in the present embodiment, the step counter 7 is initialized every time the reference signal is input, but the present invention is not limited to this. For example, it may be initialized at the start of each small unit process.
Further, the step counter 7 need not be cleared. However, when the decoder 6 sets the next processing start step value in the register 8, it is necessary to calculate the next processing start step value from the current count value, so that the processing of the decoder 6 is complicated. In any case, as long as the step counter 7 can count the clock S2 during the stop period provided between the small unit processes and determine the start time of the next small unit process, the same as in the present embodiment. The effect is obtained.

In the DSP according to the present embodiment, the clock generator 2 stops the clock S1 to stop the arithmetic processing unit 3, but the present invention is not limited to this. For example, the execution of the small-unit processing by the arithmetic processing unit 3 may be stopped by instructing the arithmetic processing unit 3 to repeat the non-operation processing. In this case, the step counter 7 and the register 8 can be compared by using an ALU or the like in the DSP instead of the comparator 9. Further, since the time can be measured by the number of times the non-operation processing is repeated, the DSP executes a predetermined program, so that the step counter 7 and the register 8 can be substituted. In addition, when clocking is performed by the number of non-operations, the clock generator 2 does not need to generate the clock S2. In any case, while the arithmetic processing unit 3 repeats the non-operation processing, among the circuits constituting the arithmetic processing unit 3 such as the arithmetic unit, the circuits with large current consumption stop operating. The current consumption of the entire processing unit 3 decreases. As a result, substantially the same effects as in the present embodiment can be obtained.

However, when the clock S1 is stopped,
Since the clock generator 2 and the program counter 4 are stopped, the current consumption of the DSP can be further reduced as compared with the operation of the clock S1. Step counter 7
Counts the number of pulses of the clock S2, thereby measuring the suspension period independently of the clock S1 supplied to the arithmetic processing unit 3, the program counter 4, and the like.
Of the next process can be determined. Therefore, the ratio between the operation period and the stop period can be set more finely.

The digital signal processing circuit according to the present embodiment is used for an audio circuit, but is not limited to this. For example, it may be used for an image processing circuit or the like. The present invention can be applied to any device including a digital signal processing circuit that performs a predetermined amount of signal processing for each predetermined reference signal and a peripheral circuit having a specific frequency band that is easily affected.

[0067]

As described above, the digital signal processing circuit according to the first aspect of the present invention includes the control means for causing the arithmetic processing means to temporarily suspend the processing of the small unit processing at least once every input cycle of the reference signal. It is a configuration provided.

Therefore, the digital signal processing circuit has an effect that the fluctuation frequency of the current consumption can be adjusted to the high frequency side, and the adverse effect on the peripheral circuits can be reduced. further,
Since the resistance to noise can be set lower than before, the effects of simplifying the configuration of the peripheral circuit and reducing the cost required for manufacturing are also achieved.

As described above, the digital signal processing circuit according to the second aspect of the present invention is the digital signal processing circuit according to the first aspect, wherein the point at which the arithmetic processing means starts the next small unit processing is controlled by the control. There is provided a next process start time designation means for designating the means. Further, the control means is configured to make the arithmetic processing means wait from the end of each small-unit processing to the next processing start time designated by the next processing start time designation means.

Therefore, the digital signal processing circuit can reliably change the fluctuation frequency of the current consumption to a higher frequency. As a result, there is an effect that the adverse effect on the peripheral circuit can be further reduced.

As described above, in the digital signal processing circuit according to the third aspect of the present invention, in the configuration of the second aspect of the present invention, the next processing start time setting means is configured such that the arithmetic processing means performs each small unit processing. In the configuration, the next processing start time calculated based on the start time is designated to the control means.

Therefore, even when the time required to execute each small unit process changes, the time when the arithmetic processing unit starts the next small unit process can be kept constant. In particular, since the start time of the last small unit process can be determined regardless of the time required for each small unit process, it is possible to easily and reliably guarantee that all the small unit processes are completed within one input cycle of the reference signal. It works.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a main configuration of a digital signal processing circuit.

FIG. 2 is a flowchart showing an operation of the digital signal processing circuit.

FIG. 3 is a timing chart showing a waveform of each part and a signal processing image in the digital signal processing circuit.

FIG. 4 shows a conventional example, and is a timing chart showing a waveform of each part of a digital signal processing circuit and a signal processing image.

[Explanation of symbols]

 Reference Signs List 2 Clock generator (control means) 3 Arithmetic processing section (arithmetic processing means) 6 Decoder (next processing start specifying means) 7 Step counter (control means) 8 Register (control means) 9 Comparator (control means)

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-67899 (JP, A) JP-A-2-28833 (JP, A) JP-A-2-110733 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 9/30-9/355 G06F 9/46

Claims (3)

(57) [Claims] 1. A digital signal processing circuit having an arithmetic processing means for executing a plurality of small unit processes one after another when a reference signal is input, and then waiting for the next reference signal input. A digital signal processing circuit comprising: a control means for temporarily suspending the processing of the small-unit processing at least once per input cycle. 2. The apparatus according to claim 1, further comprising: a next processing start time designation means for designating a time point at which the arithmetic processing means starts the next small unit processing to the control means. 2. The digital signal processing circuit according to claim 1, wherein said arithmetic processing means is made to stand by until the next processing start time point designated by said next processing start time designation means. 3. The next processing start time setting means designates to the control means a next processing start time calculated based on a time when the arithmetic processing means starts each small unit processing. The digital signal processing circuit according to claim 2.