JP3145982B2 - Semiconductor memory device and redundant cell address detecting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of detecting the address of a redundant cell thereof, and more particularly to a semiconductor memory device which eliminates a roll call circuit and facilitates address detection of a redundant memory cell and its redundancy. The present invention relates to a cell address detection method.

[0002]

2. Description of the Related Art In recent years, the capacity of semiconductor memory devices has been further increased, and as a countermeasure against such a problem, a redundant word and a redundant digit must be provided. For this reason, many products usually have a roll call circuit for judging whether a redundant word and a redundant digit are used or not, in order to investigate whether or not a defect is caused by redundancy during product evaluation and failure analysis.

For example, the block diagram shown in FIG. 6 is an example of a conventional roll call circuit. A roll call read circuit 14 for sending a roll call determination result to RWBST / N at the time of a roll call test, and a memory data RWBS
Sense amplifier data read circuit 14 for sending to T / N and R
A data amplifier 16 for amplifying the WBST / N pair and outputting the amplified data to a data out buffer and a data out buffer 17 for outputting the data to an I / O pad are provided. Also, A1
Signal XADD1 input to Am pin as X address
To XADDm and a signal XA input as an X address
A RED decoder 10 having DD1 to XADDm as inputs is provided. Similarly, an X decoder 11 having signals XADD0 to XADDm input to pins A0 to Am as X addresses and an output of the RED decoder 10 as inputs is provided. I have. Further, the output of the RED decoder 10 and the ATD
A roll call decoder 12 to which the output of the generation circuit 13 and the test mode activating signal B are input is also provided.

An input signal B is a test mode activating signal which is LOW only when the roll call test mode is used, and is normally HIGH. In this case, the contact C is LOW.
When the input A is LOW, the READT / N pair is RWB
The data is sent to the ST / N, amplified by the data amplifier 16 and output to the I / O pad via the data out buffer 17. In the roll call test mode, the input signal B is L
Since the output becomes OW, the output of the roll call decoder 12 and the contact D become LOW, and the contact C becomes HIGH, so that the sense amplifier data reading circuit 15 is turned OFF.
N, and output to the I / O pad via the data amplifier 16 and the data out buffer 17.

For example, HIGH is written in READT on the sense amplifier data read circuit side and LOW is written in READN in advance, and LOW data is sent to RWBST and HIGH data is sent to RWBSN from the roll call result read circuit side, so that I / O pads are sent to the I / O pads. The output data changes. Therefore, by performing a roll call test while changing the combination of HIGH or LOW of XADD1 to XADD9, it is determined whether the subsequent word selection is a redundant word or a normal word.

However, the prior art described above has a disadvantage that a roll call circuit for detection is required to detect a redundant address, and as a result, the circuit becomes large and the product becomes expensive. Further, when performing product evaluation and failure analysis using a roll call circuit, it is necessary to create a special program for exclusive use, and therefore, there is a drawback that a technician needs knowledge of the circuit.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, to detect the address of a redundant cell in a simple manner without using a conventional roll call circuit. It is an object of the present invention to provide a novel semiconductor memory device and a method of detecting addresses of redundant cells thereof.

[0008]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, the first aspect of the semiconductor memory device according to the present invention is a semiconductor memory device comprising a word line and a complementary signal line pair.
Digit lines are arranged orthogonal to each other,
A memory cell is provided at the intersection of the
In a semiconductor memory device having a cell array, complementary signals
At least two pairs of redundant digit lines
At the intersection of the redundant digit line and the word line.
A memory cell is provided and arranged along the redundant digit line.
The redundant memory cell to be placed is any one of the complementary signal line pairs.
Array pattern at the intersection with the word line on the side
Is different from the array pattern of the cell array,
The redundant digit line is unique.
The second aspect is that the redundant digit line
Is crossed at least once.
In a third aspect, the cell array is a DRAM cell
It is characterized by being .

In a first aspect of the method for detecting the address of a redundant cell in a semiconductor memory device according to the present invention, a method of detecting an address complementary to a word line is provided.
And a digit line comprising a signal line pair are arranged perpendicular, to form a cell array with memory cells provided at intersections between the word lines and the digit line, a complementary pair of signal lines
At least two pairs of redundant digit lines
A redundant memory cell is provided at an intersection of the redundant digit line and the word line, wherein the redundant memory cell is provided along the redundant digit line.
The redundant memory cell is connected to either side of each complementary signal line pair.
Array pattern at the intersection with the word line
The, when made different from the arrangement pattern of the cell array co
In addition, by making the redundant digit line unique,
It is possible to detect a replacement address when the cell array is replaced with a redundant memory cell, and the second mode is that one logic level is positive for all cells and the other is logic. A read operation is performed with the level being erroneous, and the replacement address is detected from the resulting bit map.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor memory device according to the present invention is arranged so that a word line and a digit line are orthogonal to each other.
In a semiconductor memory device in which a memory cell is provided at an intersection of the word line and the digit line to form a cell array,
At least two redundant word lines are provided, redundant memory cells are provided at intersections between the redundant word lines and the digit lines, and the two redundant word lines are crossed to form an array pattern of the cell array. In this case, the arrangement pattern of the cell array along the redundant word line is changed, and at least one pair of redundant digit lines is provided, and a redundant digit line is provided at the intersection of the redundant digit line and the word line. A memory cell is provided, and by crossing the redundant digit lines, an arrangement pattern of the cell array along the digit lines is changed with respect to the arrangement pattern of the cell arrays.

With this configuration, the cell pattern of the portion replaced with the redundant memory cell with respect to the pattern of the normal cell array changes, so that the replacement address can be easily detected when the cell array is replaced with the redundant memory cell. And the detection of the presence or absence of the replacement is also facilitated. Further, since it is not necessary to incorporate a conventional roll call circuit, it is possible to provide a product at low cost.

An embodiment of the present invention will be described below. In FIG. 1, W0 to W4 are word lines, RW0 and RW1 are redundant word lines, DG0 to DG3 are digit lines, and RDG.
0, RDG1 are redundant digit lines, m1 to m16 are normal memory cells, m17 to m36 are redundant memory cells, SA1
To SA6 are sense amplifiers connected to digit lines DG0 to DG3 and redundant digit lines RDG0 and RDG1;
0 to YSW3 are Y switches provided on digit lines DG0 to DG3, and RDW0 and RDW1 are redundant digit lines RD.
These are Y switches connected to G0 and RDG1.

The memory cell is composed of a diffusion layer Q, a contact C, and a pair of memory cells. Each memory cell is formed at an intersection of a word line and a digit line. The normal memory cells m1 to m16 are selected by word lines W0 to W4 and digit lines DG0 to DG3, and redundant cells m17 to m3 are selected.
6 is selected by the redundant word lines RW1 and RW0 or the redundant digit lines RDG1 and RDG0.

The cell pattern of the normal word line is NNTTN.
The TRUE cell and the NOT cell are repeated every two bits, such as N ..., TTNTNT .... In order to distinguish the cell pattern of the redundant word line, for example, to change the memory cell pattern at the lowest address of the redundant word line to a NOT cell, the pattern of the redundant word line RW0 is changed to select the memory cell m21. . Again, the second and subsequent bits from the lowest order have the same pattern as the normal word line.
Restored redundant word line pattern. As a result, the pattern of the redundant word line RW0 becomes NTNNNT. In the same manner, the cell pattern of the redundant word line RW1 is TNTTN
N ...

On the other hand, in order to distinguish the redundant digit line RDG0 from the normal digit line cell pattern, the least significant bit cell pattern is changed by twisting the TRUE signal and the NOT signal. As a result, the cell pattern of the redundant digit line RDG0 becomes TTTNN... And can be distinguished from the normal digit line cell pattern NTTN.
The redundant digit RDG1 has a cell pattern of N in a similar manner.
NNT... Can be distinguished from regular digit line patterns.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor memory device according to the present invention and a method of detecting addresses of redundant cells thereof will be described in detail with reference to the drawings. FIG. 1 is a diagram showing the structure of a specific example of a semiconductor memory device according to the present invention.
In a semiconductor memory device in which word lines W0 to W4 and digit lines DG0 to DG3 are arranged so as to be orthogonal to each other and memory cells m1 to m16 are provided at intersections of the word lines and digit lines to form a cell array, Redundant word lines RW0, RW1 are provided at the intersections of the redundant word lines RW0, RW1 and the digit lines DG0 to DG3.
And a semiconductor memory device configured to cross the redundant word lines to change the array pattern of the cell array along the redundant word lines with respect to the array pattern of the cell array. , At least a pair of redundant digit lines DG0 and DG1 are provided, and the redundant digit lines DG0 and DG1 and the word lines W0 to DG1 are provided.
Redundant memory cells m25 to m32 are provided at the intersection with W4, and by crossing the redundant digit lines,
A semiconductor memory device configured to change the array pattern of the cell array along the digit lines with respect to the array pattern of the cell array is shown.

Hereinafter, the present invention will be described in more detail with reference to FIGS. As shown in FIG. 1, in this example, word lines W0 to W4 and two redundant word lines RW0, RW
1 and digit lines DG0-DG3, two redundant digits R
DG0, RDG1, sense amplifiers SA1 to SA6 paired with respective digit lines, memory cells m1 to m36, diffusion layers Q in which memory cells m1 to m36 are formed, contacts C between the digit lines and the memory cells, It consists of an IO bus.

In the read operation, when the word line W0 is selected, the memory cell m to which the word line W0 is gate-input.
Data from 1, m2, m3, and m4 are transmitted to each digit line, and the potential of each digit line is input to each sense amplifier to amplify the data. One digit line is selected by the Y switch, and read data is transmitted to the IO bus.

In FIG. 1, memory cells m1 and m2 are connected to a signal line on the TRUE side of the digit line, and memory cells m3 and m4 are connected to a signal line on the NOT side of the digit line. . Below, the TRUE of the digit line
A cell connected to the side of the digit line is a TRUE cell, and a cell connected to the NOT side of the digit line is a NOT cell. FIG. 2 shows a further simplified pattern of the memory cell shown in FIG.

When the memory cell does not perform the write operation in the initial state and performs the read operation, the same data is read from the memory cells m1 and m2, and the data opposite to the memory cells m1 and m2 is read from the memory cells m3 and m4. . As described above, the memory cell group connected to the signal on the TRUE side of the digit line and the memory cell group connected to the signal on the NOT side of the digit line always read the reverse data. In the case of the configuration, if the data “0” is read without performing the write operation in the initial state, a bad BITMAP as shown in FIG. 3 results. Thus, the memory cell becomes a regular pattern by the mask pattern. Depending on the circuit configuration, the cell on the TRUE side may be FAIL and the cell on the NOT side may be PASS.
The cell on the UE side passes by reading data "0", and
The cell on the side will be described as a circuit configuration that becomes FAIL.

In the present invention, the redundant word lines RW0 and RW1 have a configuration in which the cell pattern of the least significant 1-bit address of the Y address is changed to distinguish it from the normal memory cell pattern described above. As shown in FIG. 1, the memory cell selected by the redundant word line RW0 and the digit line DG0 is a NOT-side cell m21.

On the other hand, the redundant word line RW1 and the digit line D
The memory cell selected by G0 is a cell m17 on the TRUE side.
The configuration is as follows. Thereby, the redundant word RW
The memory cell pattern on line 0 is NTNNNT..., And the memory cell pattern on the redundant word RW1 line is TN
TTNN... And the normal memory cell and the least significant 1 bit have different patterns.

The memory cell pattern on the normal word line is such that a TRUE cell and a NOT cell are repeated every two bits, but the cell pattern on the redundant word line is such that the first two bits are alternately a TRUE cell and a NOT cell every other bit. I have. As described above, in the present invention, the pattern of the first 1-bit memory cell is changed only in the redundant word line. Therefore, if "0" is read without writing, the first two bits are used if the device uses the redundant word. Since a pattern different from that of the memory cell on the regular word line is generated, the presence or absence of address replacement and the replacement address can be easily checked.

Similarly, redundant digit lines RDG0, RDG
The pattern of the digit line RDG0 is changed to TTTNN..., The digit line RDG1 by changing the pattern of the memory cell selected by the word line W0 so that the memory cell pattern on the first digit line can be distinguished from the memory cell pattern on the regular digit line. Are set to NNNTT.... This is because the cell selected by the redundant digit line RDG0 and the word line W0 is changed to the m25 of the TRUE cell by twisting the TRUE signal and the NOT signal of the redundant digit line RDG0.
It is realized by doing. In the same manner, the memory cell selected as word line W0 and redundant digit RDG1 is NOT
The cell is m26.

Thus, the redundant digits RDG0, RDG
The cell patterns on the DG1 line are TTTNNNTT, respectively.
N ..., NNNTTNNNT ... can be distinguished from the regular pattern. Note that the memory cell patterns on the regular digit lines are NTTNN,.
If the device uses a redundant digit, the TRU is not written and the data "0" is read out.
Since the E cell or the NOT cell continues for 3 bits, it is possible to easily check the presence / absence of the replacement by the redundant digit and the replacement address similarly to the redundant word described above.

FIG. 4 shows a defective bitmap when data "0" is read out without writing when using one redundant word and one redundant digit in the present invention.
FIG. 5 is a block diagram of the semiconductor memory device of the present invention. The basic operations of a data write / read operation and a redundant word / redundant digit selection circuit are the same as those of a conventional semiconductor memory device, and therefore will be briefly described.

An arbitrary word line is selected according to the address. T of the digit line depends on the write data of the memory cell.
The RUE signal and the NOT signal have a potential difference, and the minute potential of the digit line is further amplified by a sense amplifier connected to the digit line. Next, only one Y switch signal is selected by the Y address, and data is transmitted to the IO bus via the transfer gate.

The redundant word lines RW0 and RW1 are replaced with regular words by cutting the fuse element of each address in the program circuit. Similarly, redundant digit line R
DG0 and RDG1 are also replaced with regular digit lines by cutting the fuse element of each address in the program circuit. The redundant word and digit line selection circuit is the same as the conventional circuit.

FIG. 1 shows a general memory cell pattern, but TRUE memory cells and NOT memory cells are regularly arranged on a mask pattern. Explaining the read operation, the memory cell m1 is connected to the digit line DG
0 is connected to the signal on the TRUE side, and the word line W0
Is selected, the data of the memory cell m1 is changed to the digit line D.
Transmitted to G0 TRUE signal, digit line TRU
The E and NOT signals have a potential difference.

Then, the potential difference between the digit lines is further amplified by the sense amplifier SA1. Next, when YSW0 is selected by the Y address, the data amplified by the sense amplifier SA1 is transmitted to the IO bus, further amplified by the data amplifier DATA AMP, and output to the IO pin via the output circuit. By the way, if a read operation is performed without writing in the initial state, the memory cell m
When the initial potential of 1 is read out, one of the TRUE signal and the NOT signal always has a high potential. On the other hand, NOT
When the initial data of cell m5 is read, digit line DG
Since the TRUE and NOT signal waveforms of 0 are opposite to those of the TRUE cell, the read data is the reverse data of the TRUE cell.

For example, if a TRUE cell reads data "0", a NOT cell always reads data "1".
For this reason, if the write operation is not performed in the initial state and, for example, data “0” is read from all cells, the TRUE cell and N
The pattern of the OT cell occurs as it is divided into a pass address and a fail address. When a defective address is inspected by a memory tester, a pattern as shown in FIG. 3 is obtained.

[0032]

The semiconductor memory device according to the present invention and the method for detecting the address of the redundant cell thereof have the following effects because they are configured as described above. (1) The redundant address detection circuit (roll call circuit) and the test mode circuit which are conventionally provided become unnecessary. For this reason, the chip size can be reduced, and the cost can be reduced.

(2) A special program dedicated to replacement address detection is not required, and replacement addresses can be detected by simply checking a defective BITMAP with a simple pattern of only a read pattern without writing data to all memory cells. The burden on the person can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory cell of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing a memory cell in which the cell pattern of FIG. 1 is represented by TRUE and NOT cells.

FIG. 3 is a diagram showing a defective bitmap when the cell pattern of FIG. 2 is read with data “0” without writing.

FIG. 4 is a diagram showing a defective BITMAP read with data “0” when a redundant word RW0 and a redundant digit RDG0 are replaced one by one;

FIG. 5 is a block diagram of a semiconductor memory device of the present invention.

FIG. 6 is a block diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 W0-W4 Word line RD0, RD1 Redundant word line DG0-DG3 Digit line RDG0, RDG1 Redundant digit line SA1-SA6 Sense amplifier YSW0-YSW3, RDW0, RDW1 Y switch m1-m36 Memory cell Q Contact with diffusion layer C digit line

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-1-245498 (JP, A) JP-A-6-45548 (JP, A) JP-A-6-314498 (JP, A) JP-A-6-314498 338199 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 29/00

Claims (5)

(57) [Claims] 1. A semiconductor memory device in which a word line and a digit line comprising a complementary signal line pair are arranged orthogonally, and a memory cell is provided at an intersection of the word line and the digit line to form a cell array. At least two pairs of redundant digit lines composed of complementary signal line pairs are provided, redundant memory cells are provided at intersections of the redundant digit lines and the word lines, and the redundant memory cells arranged along the redundant digit lines are provided. A semiconductor memory, wherein an array pattern of which side of each pair of complementary signal lines intersects with the word line is different from the array pattern of the cell array and is unique for each redundant digit line. apparatus. 2. A semiconductor memory device according to claim 1, characterized in that are crossed at least once said redundant digit line. Wherein said cell array semiconductor memory device according to any one of claims 1 to 2 characterized in that it is a DRAM cell. 4. A digit line comprising a word line and a complementary signal line pair are arranged perpendicular, to form a cross point memory cell is provided in the cell array of the word line and the digit line, the complementary signal lines A redundant digit line consisting of pairs
A method of detecting addresses of redundant cells of a semiconductor memory device, wherein at least two pairs are provided, and redundant memory cells are provided at intersections of the redundant digit lines and the word lines, wherein the redundant memory cells are arranged along the redundant digit lines. Redundant memory
A cell may have the word on either side of each complementary signal line pair.
The arrangement pattern of the intersection with the line is
The redundancy pattern of the semiconductor memory device is made different from the array pattern and is made unique for each of the redundant digit lines, so that a replacement address can be detected when the cell array is replaced with a redundant memory cell. Cell address detection method. 5. The one logic level to all the cells positive, reads as erroneous the other logic level, according to claim 4, wherein the detecting the replacement address from the bit map is the result And address detection method for redundant cells of the semiconductor memory device.