JP3147154B2 - Insulated gate bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulated gate bipolar transistor or IGBT.

[0002]

2. Description of the Related Art M
OSFETs (field-effect transistors) have a disadvantage that they have a large on-resistance and are difficult to use in a large current region. In order to solve this drawback, an insulated gate bipolar transistor (IGBT) utilizing conductivity modulation has been put to practical use.

As shown in FIG. 1, a conventional insulated gate bipolar transistor includes a collector region 1 composed of a P-type semiconductor region and an N-type semiconductor region having a relatively high impurity concentration formed on the upper surface of the collector region 1. A drift region 3 formed of an N-type semiconductor region having a relatively low impurity concentration formed on the upper surface of the buffer region 2 and the collector region 1 via the buffer region 2, and a DSA (Di
A semiconductor including an island-shaped or lattice-shaped P-type semiconductor region formed by a ffusion self-alignment (Ffusion Self Alignment) method and an emitter region 5 formed in the base region 4 by an annular N-type semiconductor region formed by a DSA method. A base 6 is provided. An emitter electrode 7 electrically connected to the base region 4 and the emitter region 5 is provided on one main surface of the base 6.
And a gate electrode 9 disposed above the base region 4 interposed between the emitter region 5 and the drift region 3 with an insulating film (gate oxide film) 8 interposed therebetween. On the other main surface of the base 6, a collector electrode 10 electrically connected to the collector region 1 is formed.

In the insulated gate bipolar transistor of FIG. 1, when a positive voltage is applied to the gate electrode 9, an inversion region (channel region) is formed in the base region 4 directly below the gate electrode 9. In this state, when a voltage for increasing the potential on the collector electrode 10 side is applied between the collector electrode 10 and the emitter electrode 7, electrons flow from the emitter region 5 to the drift region 3 and the buffer region 2 through the channel region. . Along with this, holes are injected from the collector region 1 into the buffer region 2 and the drift region 3.
As a result, a large amount of carriers (electrons and holes) are accumulated in the buffer region 2 and the drift region 3, and conductivity modulation occurs. The electrons and holes injected into the buffer region 2 and the drift region 3 flow to the collector electrode 10 and the emitter electrode 7, respectively.

[0005]

By the way, in the insulated gate field effect transistor of FIG. 1, a voltage for increasing the potential of the collector electrode 10 is applied between the emitter electrode 7 and the collector electrode 10 as described above. In the state, the PN formed at the interface between the base region 4 and the drift region 3
A depletion layer extends from the junction 11. Since the impurity concentration of the drift region 3 is lower than the impurity concentration of the base region 4,
This depletion layer mainly spreads to the drift region 3 side. Here, when the application of the positive voltage to the gate electrode 9 is released and the current is turned off (switching off), the depletion layer spreads so as to reach the buffer region 2 and both ends of the depletion layer are located between the electrodes 7 and 10. The applied voltage is applied. Carriers accumulated in the drift region 3 during the above-described conductivity modulation are swept out to the buffer region 2 by the spread of the depletion layer. Here, the holes swept out into the buffer region 2 flow into the base region 4 due to the electric field generated at both ends of the depletion layer, and flow out from the emitter electrode 7. On the other hand, the electrons swept out into the buffer region 2 flow into the collector region 1, whereby holes are newly supplied from the collector region 1 to the buffer region 2. As a result, carriers are accumulated in the buffer region 2 for a while even after switching off, and a small current (tail current) is generated between the collector electrode 10 and the emitter electrode 7 until these carriers disappear. Keep flowing. It is desired that the tail current be as small as possible, but this is difficult in the conventional transistor structure.

Accordingly, an object of the present invention is to provide an insulated gate bipolar transistor having a novel structure capable of reducing tail current.

[0007]

SUMMARY OF THE INVENTION The present invention for solving the above problems and achieving the above objects will be described with reference to the reference numerals of the drawings showing the embodiments. 3
2, a semiconductor substrate 20 having an insulating film 30 selectively provided on the first main surface 28 of the semiconductor substrate 20.
An emitter electrode 29 provided on the first main surface 28 of the semiconductor substrate 20, a gate electrode 31 provided on the insulating film 30, and the second main surface of the semiconductor substrate 20 32. An insulated gate bipolar transistor comprising a collector electrode 33 provided at 32. The semiconductor substrate 20 comprises a collector region 21 of a first conductivity type and a second conductivity type of a conductivity type opposite to the first conductivity type. Buffer area 2
2, a drift region 23 of the first conductivity type, a base region 24 of the first conductivity type, an emitter region 25 of the second conductivity type,
First and second bypass regions 26 and 27 of the second conductivity type, and the collector region 21 is disposed so as to be exposed on the second main surface 32 of the semiconductor substrate 20. The buffer region 22 is disposed between the collector region 21 and the first main surface 28 of the semiconductor substrate 20 and is adjacent to the collector region 21 so that a PN junction 34 is formed between the buffer region 22 and the collector region 21. The drift region 23 is disposed between the buffer region 22 and the first main surface 28 of the semiconductor substrate 20 and the buffer region 22 is formed such that a PN junction 35 is formed between the buffer region 22 and the first main surface 28. 22 and has a lower impurity concentration than the buffer region 22, and the base region 24 has a portion exposed on the first main surface 28 of the semiconductor substrate 20. And has an impurity concentration higher than that of the drift region 23 and adjacent to the drift region 23 so as to face the buffer region 22 with the drift region 23 interposed therebetween. The semiconductor substrate 20 has a surface exposed to the first main surface 28 and is adjacent to the base region 24 so as to be surrounded by the base region 24 except for the exposed surface. The bypass region 26 is arranged so as to have a surface exposed on the first main surface 28 of the semiconductor substrate 20, is adjacent to the base region 24, and faces the buffer region 22 via the drift region 23. As described above, the second bypass region 27 is adjacent to the drift region 23 and the first bypass region 2
6 so as to connect the buffer region 22 with the first
The emitter electrode 29 is connected to the emitter region 25 and the base region 24 in a position adjacent to the bypass region 26 and the buffer region 22 and apart from the base region 24 when viewed in plan. The insulating film 30 is formed on the first main surface 2 of the semiconductor substrate 20.
8 so as to cover at least the surface of the base region 24 between the emitter region 25 and the first bypass region 26, and the gate electrode 31 is connected to the emitter region 25 of the base region 24. The collector electrode 33 is arranged so as to cover the surface of the portion between the first bypass region 26 and the first bypass region 26 via the insulating film 30.
The present invention relates to an insulated gate bipolar transistor which is connected to the collector region 21. The second bypass region 27 can be formed by diffusing impurities from the first and second main surfaces of the semiconductor substrate 20 as described in claim 2. Further, the second bypass region 27 can be formed by diffusing impurities only from the first main surface 28 side of the semiconductor substrate 20 as described in claim 3.

[0008]

According to the invention of each claim, the base region 2
4 has the same conductivity type as that of the base region 24, so that when a voltage for ON control is applied to the gate electrode 31, the first and second bypasses do not pass through the drift region 23. An emitter current and a collector current flow through the regions 26 and 27. At this time, since a PN junction is formed between the second bypass region 27 and the collector region 21, holes are injected from the collector region 21 into the second bypass region 27 and the buffer region 22, and drift due to diffusion. Flow into the area. As a result, the potential of the drift region 23 increases, and the PN junction 36 between the drift region 23 and the first bypass region 26 becomes in a forward bias state, and electrons are injected from the first bypass region 26 into the drift region 23. And drift region 2
3, the conductivity modulation occurs, and the on-resistance between the collector electrode 33 and the emitter electrode 29 decreases. When the voltage of the gate electrode 31 is controlled so as to be turned off, the depletion layer based on the PN junction 35 between the buffer region 22 and the drift region 23 spreads in the drift region 23 and the drift region 23
Carriers (holes, electrons) are swept out to the base region 24, the holes flow to the emitter electrode 29, and the electrons flow into the collector region 21 via the buffer region 22 by the electric field of the depletion layer. The electrons flowing into the collector region 21 from the base region 24 at the time of turning off are the sum of the electrons existing in the drift region 23 and the electrons existing in the base region 24 at the time of turning on. Now, the amount of carriers in the conventional drift region 3 shown in FIG.
Assuming that the carrier amount of the buffer region 3 is the same, the ratio of the carrier amount of the buffer region 2 in FIG. 1 to the carrier amount of the base region 24 in FIG. 3 corresponds to the first main surface 28 of the semiconductor substrate 20.
The buffer region 2 of FIG. 1 and the buffer region 22 of FIG.
20 are formed so as to correspond to almost all of the main surface of FIG.
In this case, the volume of the base region 24 is smaller than the volume of the buffer region 22. Therefore, the amount of accumulated carriers in the base region 24 when the transistor is turned on is smaller than the amount of accumulated carriers in the buffer region 22, and the tail current is reduced.

[0009]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS.

FIG. 2 shows an insulated gate bipolar transistor or IGBT semiconductor substrate 2 according to an embodiment of the present invention.
FIG. 3 shows the IGBT of the present embodiment in FIG.
FIG. 3 is an enlarged partially cutaway cross-sectional view taken along a line corresponding to line −A. The IGBT of the present embodiment includes a silicon semiconductor substrate 20, an emitter electrode 29, a gate electrode 31, a collector electrode 33, and an insulating film 30. The emitter electrode 29 is the first main electrode, and the collector electrode 33 is the second main electrode.
The main electrode and the gate electrode 31 can also be called control electrodes.

The semiconductor substrate 20 includes a P-type collector region 21 which may be referred to as a first semiconductor region, an N-type buffer region 22 which may be referred to as a second semiconductor region, and a third semiconductor region. Possible P-type drift region 23
A P-type base region 24, which may also be referred to as a fourth semiconductor region, an N-type emitter region 25, which may also be referred to as a fifth semiconductor region, and a second, which may also be referred to as sixth and seventh semiconductor regions. First and second N-type bypass regions 26, 27
And Semiconductor substrate 2 of IGBT according to the present invention
The new points of 0 are that the drift region 23 is the same P-type semiconductor region as the base region 24 and that the first and second bypass regions 26 and 27 are provided.

The P-type collector region 21 is arranged so as to be exposed on the second main surface 32 of the semiconductor substrate 20.

The N-type buffer region 22 is arranged between the P-type collector region 21 and the first main surface 28 of the semiconductor substrate 20 and has a P-type junction 34 between the P-type collector region 21 and the P-type collector region 21. It is adjacent to the collector region 21.

The P-type drift region 23 can be called a conductivity modulation region, and is an N-type buffer region 22.
And the first main surface 28 of the semiconductor substrate 20, and is adjacent to the N-type buffer region 22 so that a PN junction 35 is formed between the N-type buffer region 22 and the N-type buffer region 22. The impurity concentration of drift region 23 is lower than the impurity concentration of N-type buffer region 22.

The P-type base region 24 is arranged to have a portion exposed on the first main surface 28 of the semiconductor substrate 20 and is adjacent to the P-type drift region 23 and has a higher impurity concentration than the P-type drift region 23. Have. In this embodiment, as shown in FIG. 2, a plurality of (nine) N-type base regions 24 are formed in the P-type drift region 23 in an island shape. The base region 24 is formed by a well-known DSA method.
It is formed by selectively diffusing a shaped impurity. Therefore, the lower surface and the lower part of the side surface of the base region 24 are surrounded by the P-type drift region 23. This P-type base region 24
Are of the same conductivity type as the P-type drift region 23, they can be called a first base region, and the drift region 23 can be called a second base region.

The N-type emitter region 25 has a surface that is annularly exposed on the first main surface 28 of the semiconductor substrate 20, and is surrounded by the P-type base region 24 except for the exposed surface.
The emitter region 25 is formed by diffusing an N-type impurity into the P-type base region 24 by the DSA method.

The first N-type bypass region 26 is arranged to have a surface exposed on the first main surface 28 of the semiconductor substrate 20, is adjacent to the upper side of the P-type base region 24, and has an N-type buffer region. It is adjacent to the P-type drift region 23 so that a PN junction 36 is formed. In this embodiment, the first N-type bypass region 26 is formed in the same step and at the same depth as the emitter region 25, but may be formed in different steps at different depths.

The second N-type bypass region 27 is adjacent to the first N-type bypass region 26 and the N-type buffer region 22 so as to connect the first N-type bypass region 26 and the N-type buffer region 22. Further, it is arranged at a position distant from the P-type base region 24 in the outer peripheral direction when viewed in plan. The second bypass region 27 is formed as shown in FIG. 5 by diffusing N-type impurities from one and the other main surfaces of the P-type semiconductor substrate (wafer) 40 shown in FIG. And upper and lower N-type diffusion regions 27a and 27b having First
The N-type bypass region 26 and the N-type buffer region 22
Since the second N-type bypass region 27 is provided by diffusion of the N-type impurity after the formation thereof, the first N-type bypass region 26 is formed.
The N-type buffer region 22 is provided up to the side surface (outer peripheral surface) of the semiconductor substrate 20 in FIG. 3, and the second N-type bypass region 27 can be considered to exist between them. In this embodiment, the P-type base region 2 is longer than the shortest distance L1 between the first N-type bypass region 26 and the N-type buffer region 22.
4 and the second N-type bypass region 27, the shortest distance L2
Is long. Accordingly, the total distance from the outer peripheral edge of the base region 24 to the buffer region 22 through the first and second N-type bypass regions 26 and 27 is longer than the shortest distance L1.

The emitter electrode 29 is formed on the first
And is connected to a portion of the P-type base region 24 surrounded by the emitter region 25 and the emitter region 25. Note that the plurality of emitter electrodes 29 provided in the plurality of emitter regions 25 and the base region 24 are connected to each other.

The insulating film 30 has at least the P-type base region 2
The first and second N-type bypass regions 26 and 27 are provided on the first main surface 28 of the semiconductor substrate 20 so as to cover a portion on the outer peripheral side of the emitter region 25 and cover the surfaces of the first and second N-type bypass regions 26 and 27.

The gate electrode 31 has a portion on the outer peripheral side of the emitter region 25 of the P-type base region 24, that is, a portion between the N-type emitter region 25 of the P-type base region 24 and the first N-type bypass region 26. It is formed so as to cover through the insulating film 30. Note that the gate electrodes 31 of the plurality of minute IGBTs are connected to each other.

The collector electrode 33 is formed on the second
And is connected to the P-type collector region 21.

In this embodiment, the regions 21, 24, and 25 are called a collector region, a base region, and an emitter region corresponding to the bipolar transistor. However, the regions 21, 24, and 25 are corresponding to the insulated gate field effect transistor. It can also be called a drain region, a channel formation region, and a source region. Further, the IGBT of this embodiment can be considered as a semiconductor device having a four-layer structure of NPNP having an insulating gate.

When forming the semiconductor substrate 20 shown in FIG.
A P-type semiconductor substrate (wafer) 40 shown in FIG. 4 is prepared, and impurities are diffused from above and below to match the element division regions shown by broken lines as shown in FIG.
7b, the N-type impurity is diffused from the lower surface of the semiconductor substrate 40 to form an N-type bypass region 27.
Buffer region 22 is formed, and P-type impurities are diffused to form P-type impurities.
A P-type impurity is diffused from the upper surface of the semiconductor substrate 40 to form a P-type base region 24, and an N-type impurity is further diffused to form an emitter region 25 and a second N-type bypass. The region 27 is formed, and the insulating film 3 is formed.
0, the emitter electrode 29, the gate electrode 31, and the collector electrode 33 are formed, and then cut along a dividing line shown by a broken line in FIG.

When a positive voltage is applied to the gate electrode 31 of the IGBT of FIG. 3, an inversion region (channel region) is provided immediately below the gate electrode 31 of the P-type base region 24 in the same manner as in the conventional example.
Is formed. In this state, when a voltage for increasing the potential on the collector electrode 33 side is applied between the collector electrode 33 and the emitter electrode 29, the first N-type bypass region 26 and the second N-type bypass region 26 pass through the channel region from the N-type emitter region 25. Electrons are injected into the P-type collector region 21 via the second N-type bypass region 27 and via these and the buffer region 22. Along with this, holes are injected from the collector region 21 into the second N-type bypass region 27 and the N-type buffer region 22. The holes are provided through the lower region 27b of the second N-type bypass region 27 or through the second N-type bypass region 27.
Flows into the P-type drift region 23 via the N-type buffer region 22 without passing through the lower region 27b. This gives P
When the potential increases, the PN junction 36 becomes forward biased, and injection of electrons (minority carriers) from the first N-type bypass region 26 to the P-type drift region 23 occurs. As a result, conductivity modulation occurs in the P-type drift region 23, and the resistance at this portion decreases. P-type collector region 21 to N-type buffer region 2
2 starts flowing into P-type drift region 23 through P 2, the forward bias of PN junction 36 is maintained, and the injection of holes from P-type collector region 21 to N-type buffer region 22 continues. , N-type buffer region 22 is formed sufficiently thinner than the hole diffusion distance, so that almost all of the holes injected here pass through PN junction 35 in a reverse bias state and become P-type drift region 23. And the ON state of the IGBT is maintained. In this embodiment, since the drift region 23 has the same P-type as the base region 24, a current flows from the P-type drift region 23 to the emitter electrode 29 via the P-type base region 24. P-type collector area 21
From the P-type drift region 2 via the N-type buffer region 22
When the flow of holes into 3 starts, and a path for the collector current is formed in the central region of semiconductor body 20, the collector current passing through both first and second N-type bypass regions 26 and 27 is substantially reduced. Becomes zero. Therefore, the current paths of the first and second N-type bypass regions 26 and 27 are current paths only in the initial stage when the IGBT is turned from off to on, and can be considered as trigger current paths. P-type drift region 2
3 is formed to be thicker than the collector region 21, the buffer region 22, the base region 24, the emitter region 25, and the first N-type bypass region 26 in order to increase the breakdown voltage.
When T is turned on, conductivity modulation occurs here, so that the on-resistance is suppressed to a low value. Therefore, it is possible to provide an IGBT having low on-resistance despite high reverse breakdown voltage.

Next, the reason why the tail current is reduced by the IGBT of this embodiment will be described. When the IGBT of this embodiment is in the ON state, the potential of the collector electrode 33 is made higher than the potential of the emitter electrode 29 as described above. Therefore,
The PN junction 34 between the P-type collector region 21 and the N-type buffer region 22 is in a forward bias state, but the PN junction 35 between the N-type buffer region 22 and the P-type drift region 23
Is in a reverse bias state. This is the conventional IGBT of FIG.
And different. In the conventional IGBT, since the drift region 3 is the same N-type as the buffer region 2, a PN junction cannot be formed between the two, and a PN junction 11 occurs between the P-type base region 4 and the N-type drift region 3. . In the IGBT of this embodiment, since the impurity concentration of the P-type drift region 23 is lower than the impurity concentration of the N-type buffer region 22, when the PN junction 35 between them is in a reverse bias state, the depletion layer is on the P-type drift region 23 side. Spread. However, when a positive voltage is applied to the gate electrode 31 and the IGBT is in the ON state, electrons are injected into the P-type drift region 23, so that the spread of the depletion layer based on the PN junction 35 is limited. Thereafter, the application of the positive voltage to the gate electrode 31 is stopped, and P
When the channel of the base region 24 is extinguished and the IGBT is turned off, injection of electrons from the first N-type bypass region 26 to the P-type drift region 23 is stopped, and the PN junction 3
5, the depletion layer spreads so as to reach the base region 24 and the first N-type bypass region 26, and most of the voltage between the emitter electrode 29 and the collector electrode 33 is applied to both ends of the depletion layer. When the depletion layer spreads over the entire drift region 23 as described above, carriers accumulated in P-type drift region 23 during conductivity modulation are swept out to P-type base region 24. Holes in the carriers swept out to the P-type base region 24 flow out to the emitter electrode 29. The electrons in the base region 24 flow into the collector region 21 via the buffer region 22 due to a potential difference between both ends of the depletion layer. When electrons flow into the collector region 21, holes are injected into the buffer region 22, and a tail current flows as in the conventional case. However, the base region 24 is the first region of the semiconductor substrate 20.
Is formed in an island shape from the main surface 28 of
The volume can be reduced as compared with the buffer region 2 of the transistor in FIG. 1, and the total amount of accumulated electrons can be reduced. As a result, the tail current can be reduced as compared with the transistor of FIG.

[0027]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. Forming a type layer 23a ^- (1) P by the final epitaxial growth method that provided the N-type region 22a which functions as a final buffer area P-type semiconductor substrate 21a which functions as a collector region, as shown in FIG. 6 And this P
^- by impurity diffusion, as shown in FIG. 7 in the layer 23a second
An N-type region 27 'for the N-type bypass region is provided, and a P-type base region 24 and an N-type emitter region 26 are provided in a P-type region 23a surrounded by the region 27' as in FIG. be able to. Note that, also in FIG. 7, the elements are separated from each other by the portions indicated by broken lines. (2) In addition, a groove is formed in advance in a separation region indicated by a broken line in FIGS.
Can be formed. (3) The conductivity type of each of the regions 21 to 27 in FIG. 3 can be reversed from that in FIG. (4) Since only the trigger current flows through the second bypass region 27, the second bypass region 27 may not be provided on all side surfaces of the semiconductor substrate 20 but may be provided only on a part thereof. (5) The base region 24 can be formed in a stripe shape or a lattice shape.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional IGBT.

FIG. 2 is a plan view of a semiconductor substrate of the IGBT according to the embodiment of the present invention.

FIG. 3 is a partially cutaway enlarged cross-sectional view showing an IGBT according to an embodiment of the present invention in a longitudinal section at a portion corresponding to AA in FIG. 2;

FIG. 4 is a sectional view showing a semiconductor substrate for manufacturing the IGBT of FIG. 3;

FIG. 5 is a cross-sectional view showing a substrate in which a second bypass region is formed in FIG. 4;

FIG. 6 is a cross-sectional view showing a semiconductor substrate of a modified example in which an epitaxial layer is formed.

FIG. 7 is a cross-sectional view showing a semiconductor substrate of FIG. 6 in which a second bypass region is formed.

[Explanation of symbols]

 Reference Signs List 20 semiconductor substrate 21 collector region 22 buffer region 23 drift region 24 base region 25 emitter region 26, 27 first and second bypass regions

Claims (3)

(57) [Claims] 1. A semiconductor substrate (20) having first and second main surfaces (28, 32), and selectively provided on the first main surface (28) of the semiconductor substrate (20). Insulating film (30), an emitter electrode (29) provided on the first main surface (28) of the semiconductor substrate (20), and a gate electrode provided on the insulating film (30) (31)
And the second main surface (32) of the semiconductor substrate (20).
An insulated gate bipolar transistor provided with a collector electrode (33) provided in the semiconductor device, wherein the semiconductor substrate (20) is formed of a collector region (21) of a first conductivity type and a conductivity type opposite to the first conductivity type. A second conductivity type buffer region (22) and a first conductivity type drift region (2).
3), a base region (24) of the first conductivity type, an emitter region (25) of the second conductivity type, and first and second bypass regions (26, 27) of the second conductivity type. The collector region (21) is disposed so as to be exposed on the second main surface (32) of the semiconductor substrate (20); and the buffer region (22) is arranged in the collector region (21).
And the first main surface (28) of the semiconductor substrate (20) and the collector region (2) so that a PN junction (34) occurs between the collector region (21) and the collector region (21).
1) wherein said drift region (23) is said buffer region (22)
And the first main surface (28) of the semiconductor substrate (20) and the buffer region (2) so that a PN junction (35) occurs between the buffer region (22) and the first main surface (28).
A portion adjacent to (2) and having a lower impurity concentration than the buffer region (22), wherein the base region (24) is exposed on the first main surface (28) of the semiconductor substrate (20); And has a higher impurity concentration than the drift region (23), adjacent to the drift region (23) so as to face the buffer region (22) via the drift region (23). The emitter region (25) has a surface exposed on the first main surface (28) of the semiconductor substrate (20) and is surrounded by the base region (24) except for the exposed surface. The first bypass region (26) is adjacent to the base region (24) as described above.
0) The drift region (23) is disposed to have a surface exposed to the first main surface (28) and is adjacent to the base region (24) and in the buffer region (22).
The second bypass region (27) connects the first bypass region (26) and the buffer region (22) so as to be opposed to each other so as to face each other. As described above, the emitter electrode (29) is disposed adjacent to the first bypass region (26) and the buffer region (22) and away from the base region (24) when viewed in plan. Is the emitter region (25)
And the base region (24), and the insulating film (30) is formed on at least the base region (2) on the first main surface (28) of the semiconductor substrate (20).
4) The gate electrode (31) is disposed so as to cover a surface between the emitter region (25) and the first bypass region (26), and the gate electrode (31) is the emitter region of the base region (24). (25) and the first bypass region (2
And the collector electrode (33) is disposed so as to cover the surface of the portion between the collector electrode (33) and the collector region (21).
An insulated gate bipolar transistor, characterized in that it is connected to a transistor. 2. The semiconductor device according to claim 1, wherein the second bypass region has a first main surface and a second main surface.
2. The insulated gate bipolar transistor according to claim 1, comprising a region obtained by diffusing an impurity of the second conductivity type from 2). 3. The insulation according to claim 1, wherein said second bypass region is a region obtained by diffusing impurities of a second conductivity type only from a first main surface side of said semiconductor substrate. Gate type bipolar transistor.