JP3154100B2 - Manufacturing method of liquid crystal image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to the production how the liquid crystal image display device having a light-transmitting portion.

[0002]

2. Description of the Related Art The formation of a single-crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and is used to fabricate a normal Si integrated circuit.
Much research has been done because devices utilizing SOI technology have numerous advantages that cannot be achieved with i-substrates. That is, by using the SOI technology,. Easy dielectric separation and high integration. Excellent radiation resistance. The stray capacitance is reduced and the speed can be increased. Well steps can be omitted. Latch-up can be prevented. Advantages such as the possibility of a fully depleted field-effect transistor by thinning can be obtained.

[0003] In order to realize many of the above advantages in device characteristics, researches have been made on a method of forming an SOI structure for several decades. This content is, for example, Special Issue: “Single-
crystal silicon on non-si
ngle-crystal insulators ";
edited by G. W. Cullen, Jour
nal of Crystal Growth, vol.
ume 63, no 3, pp. 429-590 (198
3). It is summarized in.

In the past, SOS (silicon-on-sapphire) formed by heteroepitaxially forming Si on a single-crystal sapphire substrate by CVD (chemical vapor deposition).
Is known as the most mature SOI technology, but it has achieved some success. And, above all, the cost of substrates and the delay in increasing their area have hindered their application. In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt is roughly divided into the following two. (1) After oxidizing the surface of the Si single crystal substrate, open a window to open the Si
Base was partially exposed and is epitaxially laterally the part as a seed, a single crystal Si onto SiO ₂
Technology for forming layers. (2) A technique in which the surface of a Si single crystal substrate itself is used as an active layer, and SiO ₂ is formed below the active layer.

As means for realizing the above (1), CVD is used.
A method in which a single-crystal layer Si is directly laterally epitaxially grown by a method, a method in which amorphous Si is deposited and a solid-phase laterally epitaxial growth is performed by heat treatment, and an electron beam or a laser beam is applied to an amorphous or polycrystalline Si layer. A method in which a single crystal layer is grown on SiO ₂ by converging and irradiating an energy beam such as a laser beam and melting and recrystallizing, and a method in which a molten region is scanned in a band shape by a rod-shaped heater (Zone mel
Ting recrys tallization is known. Although each of these methods has advantages and disadvantages, it still has significant problems in controllability, productivity, uniformity, and quality, and there is no industrially practical method yet. For example, in the CVD method, sacrificial oxidation is required to make the thin film flat, and in the solid phase growth method, the crystallinity is poor. Further, the beam annealing method has a problem in controllability such as processing time by convergent beam scanning, beam overlap, focus adjustment, and the like. Among them, Zone Melting R
Although the crystallization method is the most mature and relatively large-scale integrated circuits have been prototyped, a large number of crystal defects such as sub-grain boundaries still remain, leading to the production of minority carrier devices. Absent. In addition, any of these methods requires a Si substrate, so that a high-quality single-crystal Si layer cannot be obtained on a transparent amorphous insulator substrate such as glass.

The method (2) in which the Si substrate is not used as a seed for epitaxial growth includes the following three methods.

[0007] An oxide film is formed on a Si single crystal substrate having a V-shaped groove anisotropically etched on its surface, and a polycrystalline Si layer is deposited on the oxide film as thick as the Si substrate, and then polished from the back surface of the Si substrate. Is to form a dielectrically separated Si single crystal region surrounded by V-grooves on a thick polycrystalline Si layer. In this method, although the crystallinity is good, a step of depositing polycrystalline Si several hundred μm thick and a step of polishing a single-crystal Si substrate from the back surface to leave only a separated Si active layer are required. Therefore, there is a problem in terms of controllability and productivity.

[0008] Simox (SIMOX: Sepe
ratio by ion implanted o
xygen) is a method of forming an SiO ₂ layer by ion implantation of oxygen into a Si single crystal substrate, and is the most mature method at present because of its good compatibility with the Si process. However, in order to form a SiO ₂ layer,
It is necessary to implant oxygen ions at 10 ¹⁸ ions / cm ² or more, the implantation time is long, the productivity is not high, and the wafer cost is high. Furthermore, many crystal defects remain, and from an industrial point of view, the quality has not reached a level sufficient to produce a minority carrier device.

[0009] This is a method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method uses P
Ion implantation of an N-type Si layer on the surface of a single-crystal Si single crystal substrate (Imai et al., J. Crystal Growth, v.
ol 63, 547 (1983)) or an island formed by epitaxial growth and patterning, and only the P-type Si substrate is made porous by anodizing in an HF solution so as to surround the Si island from the surface. This is a method of separating an N-type Si island from a dielectric by accelerated oxidation. In this method, the separated Si region is determined before the device process, and there is a problem that the degree of freedom in device design may be limited.

[0010] By the way, forming a semiconductor element on a light-transmitting substrate requires a contact sensor, which is a light receiving element,
This is important in configuring a projection type liquid crystal image display device. Further, in order to further increase the density, resolution and definition of pixels (picture elements) of sensors and display devices, high-performance driving elements are required. In addition, the number of switching elements for switching pixels, the number of terminals of driving circuits and peripheral circuits thereof are enormous, and the two are separately formed, and the mutual connection thereafter has a density that is no longer possible by mechanical connection. As a result, it is desirable that the semiconductor element and the peripheral drive circuit are formed in the same base by performing the same process, and the connection between them is performed in a normal integrated circuit. In this case, high-density mounting can be realized only by patterning a conductive thin film. Further, due to the inevitable industrial demand for higher performance of the product to be produced, it is necessary that the device provided on the light-transmitting substrate be produced using a single crystal layer having excellent crystallinity.

However, on a light-transmitting substrate represented by glass, generally, only amorphous or, at best, a polycrystalline layer is formed, reflecting the disorder of its crystal structure. It has been difficult to produce a drive element having the required or required performance in many crystal structures. This is due to the fact that the crystal structure of the base is amorphous, and a high quality single crystal layer cannot be obtained simply by depositing a Si layer. Any of the above-described methods using a Si single crystal substrate is not suitable for the purpose of obtaining a good quality single crystal layer on a light transmitting substrate.

A light-transmitting substrate represented by glass and Si
Attempts to create a single-crystal thin film Si on a translucent substrate by bonding with a substrate and thinning Si by polishing (Abe, Kuwabara, Nakazato, Uchiyama, Yoshizawa, IEICE technical report, SDM 90-156, 77 (199
0)), but there is no successful example because the difference between the two coefficients of thermal expansion is as large as one digit.

Therefore, a liquid crystal display device provided with an active matrix element, which has been commercialized as a flat panel display or a projection television, has a thin film transistor in which an amorphous or polycrystalline Si semiconductor layer is formed on a glass substrate. (TFT).

FIG. 1 is a schematic diagram for explaining a conventional active matrix type liquid crystal display device. 1 is a pixel switch, 5 is a liquid crystal pixel, 6 is a transparent substrate,
Reference numeral 2 denotes a buffer unit, 3 denotes a horizontal shift register unit, and 4 denotes a vertical shift register unit. The luminance signal and the audio signal of the television are compressed into a certain band and sent to the buffer unit 2 driven by the horizontal shift register 3 having a driving ability capable of following the frequency. Next, a signal is transferred to the liquid crystal by the vertical shift register 4 while the pixel switch 1 is ON.

Considering the high-definition television, the performance required for each circuit is as follows: a frame frequency of 60 Hz, a number of scanning lines of about 1,000, a horizontal scanning period of about 30 μsec (effective scanning period of 27 μsec), a number of horizontal pixels of about 1500, Then, the television signal is transferred to the buffer unit at a frequency of about 45 MHz. The period allowed for signal transfer per scanning line is 1-2 μsec. Therefore, as the performance required for each element circuit, the driving capability of the horizontal shift register is 45 MHz or more. The driving capability of the vertical shift register is 500 kHz or more. The drive capability of the transfer switch, which is driven by the horizontal shift register and transfers the television signal to the buffer unit, is 45 MHz or more.
The driving capability of the pixel switch is 500 kHz or more. Becomes The driving capability referred to here is the number of gradations N in the liquid crystal pixel.
When Vm is the voltage that gives the maximum or minimum transmittance of the liquid crystal and Vt is the threshold voltage of the liquid crystal obtained from the VT (voltage-transmittance) curve, Vm− (Vm-Vt) / N [V] This means that a voltage higher than or equal to the voltage is transferred.

As can be seen, the pixel switch
And, the vertical shift register may have relatively small driving capability, but the horizontal shift register and the buffer unit
High-speed driving is required. For this reason, in the current liquid crystal display device, pixel switches and vertical shift registers are made of polycrystalline Si or amorphous SiT deposited on a glass substrate.
It is formed monolithically with the liquid crystal by FT, and other peripheral circuits are supported by mounting an IC chip from outside.

In this case, in order to obtain a bright display image, the amount of light transmitted through the liquid crystal pixel portion must be increased.
On the other hand, in order to mount an IC chip, a glass substrate must have a strength equal to or higher than a certain value, and a glass substrate having a large thickness has been used. Therefore, sufficiently increasing the amount of transmitted light and using a thick glass substrate has caused a rise in manufacturing cost. According to the knowledge of the present inventors, it has been found that the transparent portion of the base under the liquid crystal pixel portion needs to be thin and have high light transmittance and have sufficient mechanical strength.

Moreover, such a configuration is not limited to a liquid crystal image display device, and can be applied to semiconductor optical members such as a contact type image sensor, an X-ray mask or a viewfinder, a pressure sensor, and micromechanics. It turned out.

On the other hand, by using a polycrystalline silicon TFT,
Attempts have been made to form the peripheral circuits monolithically, but since the driving capability of each TFT is small,
It is necessary to increase the size of the transistor and to make the circuit complicated.

[0020]

In order to further increase the density, resolution and definition of pixels (picture elements) of a display device, a high-performance driving element is required. In addition, the number of terminals of the switching element for switching pixels and the number of terminals of its driving circuit and peripheral circuits become enormous, and as described above, the mutual connection after separately creating both is no longer a mechanical connection (wire bonding, wire bonding, Bump connection etc.), the density becomes impossible. As a result, the semiconductor device and the peripheral driving circuit are processed in the same process in the same substrate,
It is desirable to make them, and the connection between them should be made by patterning of a conductive thin film as is done in a normal integrated circuit process. It becomes. In addition, due to the inevitable industrial demand for higher performance of the product to be produced, it is necessary to use a single crystal layer having the highest crystallinity as an element provided on a light-transmitting substrate. .

Therefore, it is very difficult to produce a driving element having the required or sufficient performance in amorphous Si or polycrystalline Si due to the crystal structure having many defects.

In addition to the above-mentioned technical problems of the base, the present inventors have found that in order to obtain a high-performance liquid crystal image display device, the structure of the switching element of the liquid crystal pixel portion and the semiconductor element of the peripheral circuit I realized that I had to design the structure from a new point of view.

[0023]

This onset bright [Means for solving problems], substrate and the substrate and a liquid crystal pixel portion formed on body, the liquid crystal image lower portion of the liquid crystal pixel portion in the substrate is translucent In a method for manufacturing a display device, a porous first substrate is provided.
The single crystal semiconductor layer formed above is interposed with a light-transmitting insulating layer
And bonded to the non-light-transmitting second base,
Removing the body by a process including etching;
The liquid crystal pixel portion was formed on the transparent insulating layer of the body
And a part of the second base below the liquid crystal pixel portion.
From the side where the single crystal semiconductor layer is not formed.
Forming a light transmitting portion by removed by a method for producing a liquid crystal image display device capable of light incident on the liquid crystal pixel portion.

[0024]

According to the present invention, an Si single crystal substrate which is economically excellent, has excellent flatness over a large area and has extremely excellent crystallinity is used, and a semiconductor active element is formed on an Si single crystal layer having extremely few defects. By reducing the stray capacitance of the semiconductor device, high-speed operation is possible, and there are no latch-up phenomena, etc., and elements and circuits excellent in radiation resistance are integrated on the same substrate as the liquid crystal image display pixel. A high-performance device can be provided.

Further, since the substrate that is impermeable to light in the visible light region in the liquid crystal image display device according to the present invention has a thickness of about 600 μm, there is a contrivance for accurately removing the portion below the liquid crystal pixel portion. As will be described later, the angle between the slope after removing the substrate and the membrane is preferably 55 ° to 90 °, and more preferably 90 °. Furthermore,
Although it is preferable that the removal of the substrate is surely completed when the membrane reaches the membrane, the present invention uses a substrate having anisotropic etching characteristics as the substrate.
With the above angle, accurate removal can be performed.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[0028] Figure 2, manufacture of the liquid crystal image display device of the present invention
FIG. 3 is a schematic view schematically showing steps of an embodiment of the method . In FIG. 2 (a), the substrate 7 non translucent substrate, the 8
Translucent insulating layer, 9 is a semiconductor single crystal layer. This substrate structure is widely known as an SOI structure, and two semiconductor substrates are bonded together via an insulating layer to make one of the substrates thinner, and is suitable in that the insulating layer can be freely selected. ing. Using known integrated circuit process technology SOI substrate shown in FIG. 2 (a), which are the semiconductor active devices required for a liquid crystal picture display device as shown in FIG. 2 (b), the pixel Sui switching element 10 and a drive circuit 11,
The peripheral circuit 12 is created. Thereafter, as shown in FIG. 2C, the liquid crystal 14 is sealed using the cover glass 15 and the sealing material 13. Needless to say, the liquid crystal portion requires an alignment film, a counter electrode, a filter, a polarizing plate, and the like, but these are well-known technical items and will not be described here. In this state, since the substrate is not transparent to visible light, it is not used as a projection display device in which a light source is arranged behind the substrate. Therefore, finally, as shown in FIG. 2D, the non-light-transmitting substrate 7 below the liquid crystal pixel portion 16 is removed from the back surface to the light-transmitting insulating layer 8 so that the light-transmitting insulating layer 8 is substantially light-transmitted. Create a liquid crystal image display device. It is also possible to fill the region 16 that has been partially removed due to a request for improvement in mechanical strength or reliability with a transparent resin, spin-on glass, or the like.

Further, in the liquid crystal image display device of the present invention, the light-transmitting region obtained by removing the non-light-transmitting substrate
At least provided N _x insulating layer, and the mechanical strength of the translucent regions, it is preferable to improve the reliability.

The method for forming the SiN _x insulating layer includes sputtering, low pressure CVD, and plasma CVD, but low pressure CVD is preferable from the viewpoint of controllability. The film configuration may be provided on the upper layer film (protective film) of the device, may be provided on the interlayer insulating film (inter-wiring film), or may be provided on the base insulating film.
Moreover, you may provide in these several parts. Furthermore, SiN
_The strength can be controlled by the thickness and patterning of the _x insulating layer.

FIG. 3 shows the production of the liquid crystal image display device of the present invention.
It is the schematic diagram which showed typically the process of other embodiment of the method . In this example, FIGS. 3A to 3C show FIGS. 2A to 2C.
3D, the non-light-transmitting substrate 7 below the liquid crystal pixel portion 16 is removed from the back surface to the light-transmitting insulating layer 8 as shown in FIG. After that , a SiN _x insulating layer 17 is further formed on the light-transmitting region from the back surface as a reinforcing layer, thereby producing a projection type liquid crystal image display device.

In the above-described display device, the thickness of the semiconductor active layer of the switching element 10 is set to
By making the thickness of the semiconductor active layer of the peripheral circuit 12 including the semiconductor device 1 smaller than that of the semiconductor device, a high-performance device can be obtained.

Next, a porous semiconductor (first base) used in the method for manufacturing a liquid crystal image display device of the present invention will be described.

The porous Si used as the porous semiconductor used in the present invention was discovered by Uhlir et al. In 1956 in the course of research on the electropolishing of semiconductors (AU).
hlir, Bell Syst. Tech. J. , Vo
l 35, 333 (1956)). In addition, Unagami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in an HF solution requires holes, and the reaction is as follows (T Eel:
J. Electrochem. Soc. , Vol. 12
7, 476 (1980)).

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ⁻ SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ^- where _{SiF 4 + 2HF → H 2 SiF} 6, e + , e ^-, respectively, represent the holes and electrons. Further, n and λ are the number of holes required for dissolving the Si1 atom, respectively, and it is assumed that porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

As described above, holes are required to form porous Si, and P-type Si is more easily transformed into porous Si than N-type Si. However, it is known that N-type Si is also transformed into porous Si when holes are injected (RP Holmstrom and JYC).
hi. Appl. Phys. Lett. Vol. 42,
386 (1983)).

This porous Si layer has a HF solution concentration of 50 to 2 compared to the density of single crystal Si of 2.33 g / cm ^3.
By changing the density to 0%, the density is 1.1 to 0.6 g.
/ Cm ³ . According to observation with a transmission electron microscope, the porous Si layer has holes having an average diameter of about 600 °. Although the density is less than half that of single crystal Si, single crystallinity is maintained, and a single crystal Si layer can be epitaxially grown on the porous layer.

In general, when a Si single crystal is oxidized, its volume increases about 2.2 times. However, by controlling the density of porous Si, it becomes possible to suppress the volume expansion of the Si single crystal. In addition, cracks introduced into the surface remaining single crystal layer can be avoided. The volume ratio R of single-crystal Si to porous Si after oxidation can be expressed as follows.

R = 2.2 × (A / 2.33) where A is the density of the porous Si. If R = 1,
That is, when there is no volume expansion after oxidation, A = 1.06
(G / cm ³ ) and the density of the porous Si layer is 1.06
By doing so, volume expansion can be suppressed.

Further, since the porous layer has a large amount of voids formed therein, the density is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
The chemical etching rate is significantly increased compared to the etching rate of the non-porous Si layer.

The method for manufacturing a liquid crystal image display device of the present invention utilizes the properties of the porous Si layer described above, and according to the present invention, non-light-transmitting via a light-transmitting insulating layer.
After forming a single crystal Si layer on the second substrate of sex, by removing necessary area only non-light-transmitting base portion, necessary for the single crystal Si layer formed non-translucent on a substrate It is possible to irradiate light only in a part of the area, and without using a translucent substrate typified by glass, it is easy to use and has excellent crystallinity in terms of productivity, uniformity, controllability, and economy. Can produce a light-transmitting SOI structure having a Si layer as excellent as a single crystal wafer.

First, an etching solution that can be suitably used in the present invention will be described.

FIGS. 4 to 11 show that the porous Si and the non-porous Si are respectively separated from hydrofluoric acid, a mixed solution of hydrofluoric acid and alcohol, a mixed solution of hydrofluoric acid and aqueous hydrogen peroxide, and a mixture of hydrofluoric acid and hydrogen peroxide. A mixture of alcohol and hydrogen peroxide, buffered hydrofluoric acid, a mixture of buffered hydrofluoric acid and alcohol, a mixture of buffered hydrofluoric acid and hydrogen peroxide, and a mixture of buffered hydrofluoric acid and alcohol The etching characteristics of a mixed solution with hydrogen oxide water are shown.

The porous Si is prepared by anodizing single-crystal Si, and the conditions are as follows. The starting material of porous Si formed by anodization is not limited to single-crystal Si, but may be Si having another crystal structure.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 ( Time) Thickness of porous Si: 300 (μm) Porosity: 56 (%) FIG. 4 shows that porous Si and non-porous single-crystal Si are infiltrated with hydrofluoric acid and etched when stirred. Si
And the etching time dependence of the thickness of single crystal Si.

The porous Si prepared under the above conditions was infiltrated with 49% hydrofluoric acid (open circles) at room temperature and stirred. Later, the decrease in the thickness of the porous Si was measured. Porous Si
Is rapidly etched, having a high degree of surface properties, and being uniformly etched to 90 μm in about 40 minutes and to 205 μm after 80 minutes. The etching rate depends on the solution concentration and the temperature.

Further, single crystal Si having a thickness of 500 μm was soaked in 49% hydrofluoric acid (black circles) at room temperature and stirred. later,
The decrease in the thickness of the single crystal Si was measured. Single crystal Si
Even after a lapse of 80 minutes, the etching was less than 60 °.

FIG. 5 shows the thicknesses of the etched porous Si and the single-crystal Si when the porous Si and the non-porous single-crystal Si were infiltrated into the mixed solution of hydrofluoric acid and alcohol without stirring. Of FIG.

The porous Si prepared under the above conditions was mixed at room temperature with a mixture of 49% hydrofluoric acid and alcohol (10:
1) (white circles) infiltrated without stirring. Later, the decrease in the thickness of the porous Si was measured. The porous Si is rapidly etched to 85 μm in about 40 minutes,
After lapse of minutes, 195 μm has a high degree of surface properties,
Etched uniformly. The etching rate depends on the solution concentration and the temperature.

In particular, by adding alcohol, bubbles of the reaction gas generated by the etching can be instantaneously removed from the etched surface without stirring, and the porous Si can be etched uniformly and efficiently.

Further, a single-crystal Si having a thickness of 500 μm is mixed with 49% hydrofluoric acid and alcohol at room temperature (10: 1).
(Black circles) infiltrated without stirring. Later, the decrease in the thickness of the single crystal Si was measured. The single crystal Si was etched only 60 ° or less even after 80 minutes.

FIG. 6 shows that the porous Si and the non-porous single-crystal Si were infiltrated into a mixed solution of hydrofluoric acid and hydrogen peroxide solution, and were stirred and stirred. 4 shows the etching time dependency of the thickness.

The porous Si prepared under the above conditions was infiltrated at room temperature in a mixed solution (1: 5) of 49% hydrofluoric acid and 30% aqueous hydrogen peroxide (open circles) and stirred. Later, the decrease in the thickness of the porous Si was measured. The porous Si is rapidly etched, having a high surface property of 112 μm in about 40 minutes and 256 μm after 80 minutes, and is uniformly etched. The etching rate depends on the solution concentration and the temperature.

In particular, by adding the hydrogen peroxide solution, the oxidation of Si can be accelerated, and the reaction rate can be increased as compared with the case of not adding the hydrogen peroxide solution. , Its reaction rate can be controlled.

Further, 500 μm-thick single-crystal Si was infiltrated at room temperature into a mixed solution (1: 5) of 49% hydrofluoric acid and 30% hydrogen peroxide (black circle) and stirred. Later, the decrease in the thickness of the single crystal Si was measured. The single crystal Si was etched only 60 ° or less even after 80 minutes.

FIG. 7 shows that the porous Si and the non-porous single-crystal Si were infiltrated into a mixed solution of hydrofluoric acid, alcohol and hydrogen peroxide without stirring, and the porous Si and the non-porous single crystal Si were infiltrated. 4 shows the etching time dependency of the thickness of single crystal Si.

The porous Si produced under the above conditions was infiltrated at room temperature into a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (open circle) without stirring. Later, the decrease in the thickness of the porous Si was measured. The porous Si is rapidly etched to 106 μm in about 40 minutes, and 244 μm after 80 minutes.
Also have a high degree of surface properties and are uniformly etched.
The etching rate depends on the solution concentration and the temperature.

In particular, by adding alcohol, bubbles of the reaction gas generated by the etching can be instantaneously removed from the etching surface without stirring, and the porous Si can be etched uniformly and efficiently.

In particular, by adding a hydrogen peroxide solution, the oxidation of Si can be accelerated, and the reaction rate can be increased as compared with the case of not adding the hydrogen peroxide solution. With this, the reaction speed can be controlled.

Further, single-crystal Si having a thickness of 500 μm was infiltrated at room temperature into a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (black circle) without stirring. Later, the decrease in the thickness of the single crystal Si was measured. The single crystal Si was etched only 60 ° or less even after 80 minutes. FIG. 8 shows the etching time dependency of the thickness of the etched porous Si and single-crystal Si when porous Si and non-porous single-crystal Si are infiltrated with buffered hydrofluoric acid and stirred.

The porous Si produced under the above conditions was treated with buffered hydrofluoric acid (4.5% HF + 36% NH) at room temperature.
₄ F + H ₂ O) infiltrate the (open circles), and stirred. Later, the decrease in the thickness of the porous Si was measured. The porous Si is rapidly etched to 70 μm in about 40 minutes, and
After elapse of 0 minutes, even 140 μm is uniformly etched with a high degree of surface property. The etching rate depends on the solution concentration and the temperature.

Further, 500 μm-thick single-crystal Si was treated with buffered hydrofluoric acid (4.5% HF + 36% NH ₄₎ at room temperature.
F + H ₂ O) (filled circles) and stirred. Later, the decrease in the thickness of the single crystal Si was measured. Single crystal Si is 12
Even after a lapse of 0 minutes, the etching was less than 100 °.

FIG. 9 shows etched porous Si and single-crystal Si when porous Si and non-porous single-crystal Si were infiltrated into a mixed solution of buffered hydrofluoric acid and alcohol without stirring. 4 shows the etching time dependence of the thickness of the film.

The porous Si prepared under the above conditions was treated with buffered hydrofluoric acid (4.5% HF + 36% NH) at room temperature.
₄ F + H ₂ O) and alcohol mixture (10: 1)
(Open circles) infiltrated without stirring. Later, the decrease in the thickness of the porous Si was measured. Porous Si is rapidly etched, having a high surface property of 67 μm in about 40 minutes and 112 μm after 120 minutes, and is uniformly etched. The etching rate depends on the solution concentration and the temperature.

In particular, by adding alcohol, bubbles of the reaction product gas can be instantaneously removed from the etched surface without stirring, and the porous Si can be uniformly and efficiently etched.

Further, 500 μm-thick single-crystal Si was treated with buffered hydrofluoric acid (4.5% HF + 36% NH ₄₎ at room temperature.
F + H ₂ O) and an alcohol mixture (10: 1) (filled circles) without stirring. Later, the single crystal S
The decrease in the thickness of i was measured. The single crystal Si was etched only 100 ° or less even after elapse of 120 minutes.

FIG. 10 shows that porous Si and non-porous single-crystal Si were infiltrated into a mixed solution of buffered hydrofluoric acid and hydrogen peroxide solution, and were etched when stirred. 4 shows the etching time dependency of the thickness of Si.

The porous Si produced under the above conditions was treated with buffered hydrofluoric acid (4.5% HF + 36% NH) at room temperature.
₄ F + H ₂ O) and mixed solution of 30% hydrogen peroxide (1:
5) Infiltrated (white circle) and stirred. Later, the porous Si
Was measured for a decrease in thickness. Porous Si is rapidly etched, having a high surface property of 88 μm in about 40 minutes and 147 μm after 120 minutes, and is uniformly etched. The etching rate depends on the solution concentration and the temperature.

In particular, by adding the hydrogen peroxide solution, the oxidation of Si can be accelerated, and the reaction rate can be increased as compared with the case of not adding the hydrogen peroxide solution. , Its reaction rate can be controlled.

Further, 500 μm-thick single-crystal Si was treated with buffered hydrofluoric acid (4.5% HF + 36% NH ₄₎ at room temperature.
F + H ₂ O) and a mixture of 30% hydrogen peroxide solution (1:
5) Infiltrated (black circles) and stirred. Later, the single crystal Si
Was measured for a decrease in thickness. The single crystal Si was etched only 100 ° or less even after elapse of 120 minutes.

FIG. 11 shows the etched porous material obtained when the porous Si and the non-porous single-crystal Si were wetted without being stirred in a mixed solution of buffered hydrofluoric acid, alcohol and aqueous hydrogen peroxide. 4 shows the etching time dependency of the thickness of Si and single crystal Si.

The porous Si produced under the above conditions was treated with buffered hydrofluoric acid (4.5% HF + 36% NH) at room temperature.
₄ F + H ₂ O), a mixture of alcohol and 30% aqueous hydrogen peroxide (10: 6: 50) (open circles) was infiltrated without stirring. Later, the decrease in the thickness of the porous Si was measured. Porous Si is rapidly etched, 83 μm in about 40 minutes, and 140 μm after 120 minutes.
It has a high degree of surface properties and is uniformly etched. The etching rate depends on the solution concentration and the temperature.

In particular, by adding alcohol, bubbles of the reaction gas generated by the etching can be instantaneously removed from the etching surface without stirring, and the porous Si can be etched uniformly and efficiently.

In particular, by adding the hydrogen peroxide solution, the oxidation of Si can be accelerated, and the reaction rate can be increased as compared with the case of not adding the hydrogen peroxide solution. With this, the reaction speed can be controlled.

Further, 500 μm-thick single-crystal Si was treated with buffered hydrofluoric acid (4.5% HF + 36% NH ₄₎ at room temperature.
F + H ₂ O), a mixture of alcohol and 30% aqueous hydrogen peroxide (10: 6: 50) (filled circles) was infiltrated without stirring. Later, the decrease in the thickness of the single crystal Si was measured. The single crystal Si is kept at 100 ° even after 120 minutes.
Only the following were etched.

The porous Si and the single crystal Si after the etching with the etching solution described above were washed with water, and the surface thereof was subjected to microanalysis with secondary ions. As a result, no impurities were detected.

Although the solution concentration of the hydrogen peroxide solution is 30% here, it is set to a concentration that does not impair the effect of adding the hydrogen peroxide solution and that is practically acceptable in the manufacturing process and the like.

The conditions of the solution concentration and the temperature are set within a range where the effects of hydrofluoric acid, buffered hydrofluoric acid and the above-mentioned aqueous hydrogen peroxide or the above-mentioned alcohol are exhibited, and the etching rate is practically acceptable in the manufacturing process and the like.

In the present application, the case of the above-mentioned solution concentration and room temperature is taken as an example, but the present invention is not limited to such conditions.

The HF concentration is set in the range of preferably 1 to 95%, more preferably 5 to 90%, and still more preferably 5 to 80% with respect to the etching solution.

The HF concentration in the buffered hydrofluoric acid is preferably set in the range of 1 to 95%, more preferably 1 to 85%, and still more preferably 1 to 70% with respect to the etching solution. The NH ₄ F concentration in the acid is set in the range of preferably 1 to 95%, more preferably 5 to 90%, and still more preferably 5 to 80% with respect to the etching solution.

The H ₂ O ₂ concentration is determined by
It is preferably set in the range of 1 to 95%, more preferably 5 to 90%, and still more preferably 10 to 80%, and within a range in which the effect of the hydrogen peroxide solution is exhibited.

The alcohol concentration is set to preferably 80% or less, more preferably 60% or less, and still more preferably 40% or less with respect to the etching solution, and is set within a range in which the effect of the alcohol is exerted.

The temperature is set in the range of preferably 0 to 100 ° C., more preferably 5 to 80 ° C., and still more preferably 5 to 60 ° C.

The alcohol used in the present invention may be ethyl alcohol, isopropyl alcohol, or any other alcohol that can be used in the production process or the like and has the above-mentioned effect of alcohol addition.

Next, a method for epitaxially growing a single crystal after making the substrate porous will be described.

As shown in FIG. 12 (a), first, a Si single crystal substrate was prepared and anodized (An) using an HF solution.
The entirety of the substrate is made porous by an oxidation method to form a porous single-crystal Si substrate 18. Epitaxial growth is performed on the porous substrate surface by various growth methods to form a thin film single crystal layer 19.

As shown in FIG. 12B, another Si substrate 20 is prepared, and a light-transmitting insulating layer 2 is formed on its surface.
After forming 1, the Si substrate having the insulating layer 21 on the surface is attached to the surface of the light- transmitting insulating layer 22 formed on the single-crystal Si layer on the porous Si substrate. In this attaching step, the cleaned surfaces are brought into close contact with each other, and then, in an oxidizing atmosphere or
Heat in a nitrogen atmosphere. Insulating layer 22 is for generating in order to reduce the interface state is the final active layer monocrystalline layer 19.

As shown in FIG. 12C, the entire porous Si substrate 18 is subjected to electroless wet chemical etching of only the porous Si with the above-mentioned porous Si selective etching solution to form an insulating layer 21 or 22 thereon. The thin-film single-crystal Si layer 19 is left and formed. According to this step, the single-crystal Si layer 19 having the same crystallinity as the Si wafer is flattened and uniformly thinned on the Si base 20 via the insulating layers 21 and 22.
A large area is formed over the entire area of the wafer.

Next, as shown in FIG. 12D, the entire surface of the etching prevention film 23 is removed except for the back surface region to be made translucent.
Then, the Si substrate 20 or the Si substrate 20 and the insulating layers 21 and 22 are removed by etching until the insulating surface of the insulating layer 21 or the single crystal surface of the single crystal Si layer 19 is exposed from the opening. FIG. 12 shows an example in which only the Si base 20 is removed by etching. Etching prevention film 2
For 3, use a Si ₃ N ₄ layer or Apiezon wax
be able to.

As shown in FIG. 12E, after the etching prevention film 23 is peeled off, the partially transparent S
A single-crystal Si layer 19 having a crystallinity equivalent to that of a silicon wafer is flattened and uniformly thinned on the i-substrate 20 and the insulating layers 21 and 22 to form a large area over the entire wafer.

A thin layer (Mem) on the surface of the light-transmitting region
There is no support directly underneath (a single crystal Si layer or a single crystal Si layer and an insulating layer).

A method for forming an electronic device on a single-crystal semiconductor layer before making the above-described substrate translucent will be described.

First, in the same manner as in the step of FIG.
A thin film single crystal layer 19 is formed on a porous single crystal Si substrate 18 (FIG. 13A) .

Next, in the same manner as in the step of FIG.
An insulating layer 21 is formed on the surface of another Si substrate 20,
It was formed on the single crystal Si layer on the multi-porous Si substrate insulating layer 2
It stuck on the second surface Ritsukeru (FIG 13 (b)).

[0096] In analogy to the procedure of FIG. 12 (c), the porous Si substrate 18 et etching to be left single-crystal Si layer 19 is thinned on the insulating layers 21 and 22 formed. Further
Next, an electronic device such as a transistor, a diode, a capacitor, and a resistor or an integrated circuit 24 thereof is formed on the single-crystal Si layer 19 (FIG . 13C) .

Next, in the same manner as in the step of FIG.
Except for the back surface region to be translucent, after covering all with the etching prevention film 23, the insulating surface of the insulating layer 21 through the opening,
Alternatively, until the single crystal surface of the single crystal Si layer 19 is exposed, S
The i-base 20 or the Si base 20 and the insulating layers 21 and 22 are removed by etching. The region on the transparent, contains at least one or more electronic devices. FIG.
(D) shows an example in which only the Si substrate 20 is removed by etching.

[0098] Figure 13 (e), the after peeling the anti-etching film 23, Si substrate 20 a portion became translucent, single crystal on the insulating layer 21, 22 Si layer 19
An electronic device 24 is formed therein, and is translucent.

The support does not exist directly under the thin layer (single-crystal Si layer or the single-crystal Si layer and the insulating layer) in which the electronic device is incorporated on the surface of the light-transmitting region. .

Next, a method for forming a single crystal layer before making the porous body and then selectively making only the substrate porous by anodizing will be described.

First, as shown in FIG. 14A, a low impurity concentration layer 32 is formed by epitaxial growth using various thin film growth methods. Alternatively, the P-type Si single crystal substrate 31
Ions are implanted into the surface of the substrate to form an N-type single crystal layer 32.

Next, as shown in FIG.
The i-single-crystal substrate 31 is transformed from the back surface into a porous single-crystal Si substrate 33 by an anodization method using an HF solution.

[0103] In analogy to the procedure of FIG. 12 (b), an insulating layer 35 to another Si substrate 3 fourth surface multi porous S
on the surface of the insulating layer 36 formed on the single-crystal Si layer on the i-base
Pasting Ri attached (FIG. 14 (c)).

[0104] In analogy to the procedure of FIG. 12 (c), the porous Si substrate 33 et etching to form a monocrystalline Si layer 32 is thinned is left on the insulating layers 35 and 36 (FIG. 14
(D)) .

Next, in the same manner as in the step of FIG.
Except for the back surface region to be light-transmitting, the entire surface is covered with the etching prevention film 37, and then the insulating surface of the insulating layer 35 is opened through the opening.
Alternatively, until the single crystal surface of the single crystal Si layer 32 is exposed, S
The i-base 34 or the Si base 34 and the insulating layers 35 and 36 are removed by etching. Figure 14 (e) Si substrate 3 to
An example in which only 4 is removed by etching is shown.

As shown in FIG. 14 (f), after the etching prevention film 37 is peeled off, the partially transparent S
A single-crystal Si layer 32 having a crystallinity equivalent to that of a silicon wafer is flattened and uniformly thinned on the i-substrate 34 and the insulating layers 35 and 36 to form a large area over the entire wafer.

The thin layer (Mem) on the surface of the light-transmitting region
There is no support directly underneath (a single crystal Si layer or a single crystal Si layer and an insulating layer).

Next, a method for forming an electronic device on a single crystal semiconductor layer before making the substrate light-transmitting will be described.

First, similarly to the step of FIG. 14A, the low impurity concentration layer 32 is formed by epitaxial growth using various thin film growth methods (FIG. 15A). Alternatively, protons are ion-implanted into the surface of the P-type Si single-crystal substrate 41 to form the N-type single-crystal layer 32.

Next, in the same manner as in the step of FIG.
The P-type Si single crystal substrate 31 is transformed from the back surface into a porous single crystal Si substrate 33 by an anodization method using an HF solution (FIG . 15B) .

[0111] In analogy to the procedure of FIG. 14 (c), the formation of the insulating layer 35 on the surface of another Si substrate 34, a multi-porous Si insulating layer was formed on the single crystal Si layer on the substrate 3 6 surface
The pasting Ri attached (FIG. 15 (c)).

[0112] In analogy to the procedure of FIG. 1 4 (d), the porous Si substrate 33 et etching to form a monocrystalline Si layer 32 is thinned is left on the insulating layers 35 and 36 (FIG. 15
(D)).

Here, as shown in FIG. 15D , electronic devices such as transistors, diodes, capacitors, and resistors or integrated circuits 38 thereof are formed on the single crystal Si layer 32.
To form

[0114] Next, in the same manner as the process of FIG. 14 (e), the except backside region to translucent, after covering all the etching prevention film 37, the insulating surface of the insulating layer 35 from the opening, Alternatively, until the single crystal plane of the single crystal Si layer 32 is exposed, the Si base 34 or the Si base 34 and the insulating layer 35,
36 is removed by etching. The region to be translucent contained at least one or more electronic devices. There shows an example of etching away only the Si substrate 34 in FIG. 15 (e)

[0115] Figure 15 (f), the after peeling the anti-etching film 37, Si substrate 37 a portion became translucent, single crystal Si layer on the insulating layer 35, 36 32
The electronic device 37 is formed therein, and is translucent.

The support does not exist directly under the thin layer (single-crystal Si layer or the single-crystal Si layer and the insulating layer) in which the electronic device is incorporated on the surface of the light-transmitting region. .

[0117] In the present invention, the thickness of that is epitaxially grown Si on a porous Si substrate monocrystalline Si thin film is preferably 50μm or less, more preferably 20μm or less.

[0118] In the present invention, cemented Ri alignment is easy adhesion sufficiently enough can not be peeled off in the van der Waals force by simply contacting at room temperature the respective surface after cleaning, but still this Heat treatment is performed in a nitrogen atmosphere at a temperature of 200 to 900 ° C., preferably 600 to 900 ° C., and the substrates are completely bonded.

[0119] In manufacturing methods of the present invention uses the substrate formed with the single crystal Si layer as described above, to form a circuit by conventional methods, it is possible to configure the liquid crystal display device

In the present invention, a semiconductor is used as the second substrate.
Of the present invention by using a conductor or a conductor.
Control of back surface potential in liquid crystal display device
Can be.

[0121] Oite the liquid crystal display device according to the present invention, the potential of the back electrode for controlling is off region of the parasitic transistor to the gate electrode support substrate, a base insulating layer and the gate insulating film, as shown in FIG. 16 When a PMOS transistor such as a CMOS inverter and an NMOS transistor are used together, a portion where the off regions of both parasitic transistors overlap is adopted. In addition, any means may be used to take out the electrodes as long as the function of the display device is not hindered.However, when taking out from the back surface of the substrate using a semiconductor, it is necessary to wire through a metal electrode such as aluminum. Control becomes easier. Alternatively, the substrate may be taken out from the upper side as described later. When the package is taken out from the upper side in this manner, wiring to the package side is easy, the size is reduced, and the assembly yield is improved.

[0122] The conductive substrate that can be used in the present invention is preferably a metal having a high melting point of 900 ° C or higher because it is bonded by heat treatment when a single-crystal Si thin film is formed. When a semiconductor substrate is used, a P-type or N- type Si substrate, which is commonly used, can be used.

In the present invention, the second portion below the pixel portion
The base is made transparent by etching away from the back surface. For the etching, it is desirable to use an etchant that can provide a sufficient ratio of the etching rate of Si to the base insulating layer (10: 1 or more). For example, when the most common SiO ₂ is used as the insulating layer, KOH or an aqueous solution of ethylenediamine is used as an etching solution. KHO is a 10-70% aqueous solution, the liquid temperature is 50-120 ° C., preferably KOH 20-5%.
0%, liquid temperature 70 to 110 ° C. At this time, an etch rate of 1 to 10 μm / min is obtained for Si. The aqueous solution of ethylenediamine is, to be precise, a mixture of ethylene, pyrocaracol and water, and the composition thereof is, for example, 10:
1:10. A liquid temperature of 80 to 150 ° C. and an etch rate of 0.5 to 5 μm / min can be realized. For more precise control of the etching rate, 5-20% of pyrazine is preferably added. FIG. 17 shows the etched state. FIG.
As shown in FIG. 7, the peripheral drive circuit portion is protected by the etching resistant layer and the substrate is removed by etching, leaving the substrate of the peripheral drive portion.
In FIG. 17, reference numeral 1000 denotes an anti-etching layer, 1001 denotes a back electrode , 1002 denotes a substrate, 1003 denotes a silicon oxide layer, 1004 denotes an etching stopper, 1005 denotes a silicon oxide layer, and 1006 denotes a semiconductor layer for forming a device.

The hollow portion may be left as long as it has sufficient strength, but may be filled with a light-transmitting filler for reinforcement. As the filler, a Si-based resin, which is generally most often used, is exemplified.

In the liquid crystal display device of the present invention, by controlling the potential of the substrate of the peripheral drive circuit, the leakage current due to the operation of the parasitic MOS transistor is reduced, and the channel potential of the semiconductor device used in the drive circuit is stabilized. . Further, since the active layer is made of a single-crystal Si thin film, the semiconductor device can be operated at a speed 5 to 100 times faster than when the semiconductor device is made of a polycrystalline TFT. In addition, by etching from the back surface, the substrate of the image display unit is removed to make only the image display unit transparent, and the rigidity is maintained by the remaining substrate.

In the present invention, for example, if a low power consumption CMOS inverter is used for the driving circuit and a high withstand voltage PMOS transistor having no back surface leakage is used for the switching element, the liquid crystal display device with reduced power consumption can use both of the PMOS transistors. If a transistor is used, an inexpensive liquid crystal display device can be provided, and if an NMOS transistor is used for a drive circuit and a PMOS transistor is used for a switching element, an inexpensive liquid crystal display device can be provided without back surface leakage.

Hereinafter, the present invention will be described with reference to specific examples.

[0128]

EXAMPLES (Example 1) A P-type (100) single-crystal Si substrate having a thickness of 300 μm was anodized in an HF solution to form a porous Si substrate.

The anodizing conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 ( Time) Thickness of porous Si: 300 (μm) Porosity: 56 (%) On the P-type (100) porous Si substrate thus obtained, a Si epitaxial layer was formed to 1.0 μm by low pressure CVD.
With a layer thickness of The deposition conditions are as follows.

Source gas: SiH ₄ Carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 3.3 nm / sec Next, a 1000 ° oxide layer is formed on the surface of the epitaxial layer. On the oxidized surface, another Si substrate on which a 5000 ° oxide layer and a 1000 ° nitride layer were formed was superposed, and heated at 800 ° C. for 0.5 hour in a nitrogen atmosphere to form two Si substrates. , Firmly bonded together.

Then, the bonded substrates were mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50), and was selectively etched without stirring.
After 65 minutes, only the non-porous Si layer remains without being etched, and single-crystal Si is used as an etch stop material.
The porous Si substrate was selectively etched and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is not more than 50 ° even after 65 minutes, and the selectivity with the etching rate of the porous layer reaches more than tenth power. The etching amount (several tens of mm) in the porous layer was practically negligible. Such places, Si substrate made porous having a thickness of 200μm is removed, 1.0 micron on SiO ₂
A single-crystal Si layer having a thickness of m was formed. When SiH ₂ Cl was used as the source gas, the growth temperature had to be raised by several tens of degrees, but the accelerated etching characteristic peculiar to the porous substrate was maintained.

A field effect transistor is formed on the single crystal Si thin film and connected to each other to form a complementary element,
And an integrated circuit thereof, and a pixel switching element and a driving peripheral circuit necessary for the liquid crystal image display device were formed. Note that a known MOS integrated circuit manufacturing technique was used for the manufacturing method of each transistor.

After a black matrix and a color filter were formed on the cover glass, a common electrode was formed and an alignment treatment was performed. An active matrix substrate was subjected to an orientation treatment, a seal material was printed, and then both were assembled to inject a liquid crystal. For the various steps relating to the liquid crystal, a known liquid crystal display device manufacturing technique was applied.

Thereafter, the Si substrate side was coated with a hydrofluoric acid-resistant rubber except for a portion immediately below the liquid crystal pixel portion, and the Si substrate was partially removed to the insulating layer using a mixed solution of hydrofluoric acid, acetic acid and nitric acid. Further, a transparent resin was filled in the recesses removed for improving the reliability, and a projection type liquid crystal image display device by light transmission was completed.

Example 2 A 5 μm thick Si epitaxial layer was grown on a 200 μm thick P-type (100) Si substrate by atmospheric pressure CVD. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. Temperature: 1080 ° C. Pressure: 760 Torr Time: 1 min. The Si substrate thus obtained was anodized in an HF solution to form a porous layer.

The anodizing conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Porous Si thickness: 200 (μm) Porosity: 56 (%) As described above, in this anodization, P-type (100) Si
Only the substrate was made porous, and there was no change in the Si epitaxial layer.

Next, 10 .ANG.
An oxide layer is formed on the oxidized surface.
The other Si substrate on which an oxide layer of 00 ° and a nitride film of 500 ° were formed and an insulating layer was arranged was superimposed, and heated at 800 ° C. for 0.5 hour in a nitrogen atmosphere to form two Si substrates. Laminated firmly.

Then, the bonded substrates were mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50), selective etching was performed without stirring. After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as an etch stop material, and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is not more than 50 ° even after 65 minutes, and the selectivity with the etching rate of the porous layer reaches not less than tenth power, The amount of etching (several tens of square meters) in the non-porous layer was practically negligible. As a result, the porous Si substrate having a thickness of 200 μm was removed and 5 μm was deposited on SiO _2.
A single-crystal Si layer having a thickness of μm was formed. As a result of a cross-sectional observation with a transmission electron microscope, no new crystal defects were introduced into the Si layer, and it was confirmed that good crystallinity was maintained. Bipolar and field effect transistors are formed on the single crystal Si thin film and connected to each other to form a complementary element and its integrated circuit to form a pixel switching element and a driving peripheral circuit necessary for a liquid crystal image display device. did. In addition, as a method of manufacturing each transistor, a known MOS and Bi-CMOS integrated circuit manufacturing technology was used.

After a black matrix and a color filter were formed on the cover glass, a common electrode was formed and an alignment treatment was performed. The active matrix substrate was subjected to an orientation treatment, a seal material was printed, and then both were assembled to inject a liquid crystal. For the various steps relating to the liquid crystal, a known liquid crystal display device manufacturing technique was applied.

Thereafter, the Si substrate side was coated with a hydrofluoric acid-resistant rubber except for a portion immediately below the liquid crystal pixel portion, and the Si substrate was partially removed to the insulating layer using a mixed solution of hydrofluoric acid, acetic acid and nitric acid. Further, spin-on-glass was filled in the recesses removed for improving reliability, and a projection type liquid crystal image display device by light transmission was completed.

Example 3 An N-type Si layer was formed to a thickness of 1 μm on a 200 μm-thick P-type (100) Si substrate by proton ion implantation.
Formed . The H ⁺ implantation amount is 5 × 10 ¹⁵ (ions / cm
² ). The substrate was anodized in a 50% HF solution. The current density at this time was 100 mA /
cm ² . The porosity at this time is 8.4 μm
/ Min. And a P-type (1
00) The entire Si substrate was made porous in 24 minutes. In this anodization, only the P-type (100) Si substrate was made porous, and the N-type Si layer did not change.

Next, the surface of the N-type Si layer is 1000 °
An oxide layer of 5,000 Å on the oxidized surface
The other Si substrate on which the oxynitride layer was formed was overlapped, and heated at 800 ° C. for 0.5 hour in a nitrogen atmosphere to firmly bond the two Si substrates.

Then, a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10: 6:
In step 50), selective etching was performed without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as an etch stop material, and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is not more than 50 ° even after 65 minutes, and the selectivity with the etching rate of the porous layer reaches more than tenth power. The etching amount (several tens of mm) in the porous layer was practically negligible. Such places, Si substrate made porous having a thickness of 200μm is removed, 1.0 micron on SiO ₂
A single-crystal Si layer having a thickness of m was formed. As a result of a cross-sectional observation with a transmission electron microscope, no new crystal defects were introduced into the Si layer, and it was confirmed that good crystallinity was maintained.

A bipolar element and a field effect transistor are formed on the single-crystal Si thin film and connected to each other to form a complementary element and an integrated circuit thereof. A circuit was formed. In addition, as a method of manufacturing each transistor, a known MOS and Bi-CMOS integrated circuit manufacturing technology was used.

After a black matrix and a color filter were formed on the cover glass, a common electrode was formed and an alignment treatment was performed. The active matrix substrate was subjected to an orientation treatment, a seal material was printed, and then both were assembled to inject a liquid crystal. For the various steps relating to the liquid crystal, a known liquid crystal display device manufacturing technique was applied.

Thereafter, the back surface of the Si substrate was coated with apiezone wax except for the portion immediately below the liquid crystal pixel portion, and the Si substrate was partially removed to the insulating layer using a mixed solution of hydrofluoric acid, acetic acid, and nitric acid. Further, a clear mold was filled in the recesses removed for improving the reliability, and a projection type liquid crystal image display device by light transmission was completed.

Example 4 A P-type (100) single crystal Si substrate having a thickness of 500 μm was anodized in a 50% HF solution. The current density at this time was 10 mA / cm ² . A low-pressure CVD method was used to grow a Si epitaxial layer to a thickness of 0.5 μm on the P-type (100) porous Si substrate having a porous layer having a thickness of 20 μm formed on the surface in 10 minutes. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂ (0.6 l / min) H ₂ (100 l / min) Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min Next, the surface of this epitaxial layer Was thermally oxidized by 50 nm. Another Si substrate having an oxide layer of 0.8 μm on the surface is superimposed on the thermal oxide film, and 900 ° C.
By heating for 1.5 hours, the two substrates were firmly bonded.

Thereafter, the Si substrate was removed from the back surface by grinding to a thickness of 490 μm to expose the porous layer.

Then, a mixed solution (10: 6: 5) of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution was applied to the bonded substrate.
Selective etching was performed without stirring in 0). 1
After 5 minutes, only the single-crystal Si layer remained without being etched, and the porous Si layer was selectively etched using the single-crystal Si as an etch stop material, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low.
It was about weak, the selectivity with the etching rate of the porous layer reached more than ten-fiveth power, and the etching amount (several tens of squares) in the non-porous layer was practically negligible. After removing the Si ₃ N ₄ layer, a 0.5 μm-thick single-crystal Si film was formed on a Si substrate having an insulating layer on the surface.
A layer could be formed.

The same effect can be obtained also when the piezo wax or the electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si layer can be completely removed.

A field effect transistor is formed on the single crystal Si thin film and connected to each other to form a complementary element,
And an integrated circuit thereof, and a pixel switching element and a driving peripheral circuit necessary for the liquid crystal image display device were formed. Note that a known MOS integrated circuit manufacturing technique was used for the manufacturing method of each transistor.

After a black matrix and a color filter were formed on the cover glass, a common electrode was formed and an alignment process was performed. The active matrix substrate was subjected to an orientation treatment, a seal material was printed, and then both were assembled to inject a liquid crystal. For the various steps relating to the liquid crystal, a known liquid crystal display device manufacturing technique was applied.

Thereafter, the back surface of the Si substrate was coated with apiezone wax except for a portion immediately below the liquid crystal pixel portion, and the Si substrate was partially removed to the insulating layer using a mixed solution of hydrofluoric acid, acetic acid, and nitric acid. Further, a clear mold was filled in the recesses removed for improving the reliability, and a projection type liquid crystal image display device by light transmission was completed.

[0159] As shown in the above embodiment, the present invention
The liquid crystal image display device uses an Si single crystal substrate which is excellent in economical efficiency, has excellent flatness over a large area, and has extremely excellent crystallinity. Integrates elements and circuits with high radiation resistance, low stray capacitance of the above semiconductor elements, high-speed operation, no latch-up phenomenon, etc. on the same substrate as the liquid crystal image display pixels. A high-performance device can be provided.

Also, the liquid crystal image display device according to the present invention
By selectively removing the porous substrate or porous layer,
By being formed on a high quality single crystal layer formed on a non-transparent substrate, high performance is obtained. In addition, by employing a Si substrate as an amorphous substrate, it can be a starting material that is extremely compatible with conventional silicon integrated circuit processes in terms of thermal, mechanical, chemical, or physical properties.

In general, when a light source having a considerably high light intensity is used in a projection type liquid crystal image display device, when light hits a peripheral circuit portion, a photoexcitation current is induced in the semiconductor layer, which may cause a malfunction. In the device according to the present invention, since the peripheral circuit portion is shielded from light, such a problem can be avoided.

Reference Example 5 A 200 μm thick P-type (100) single crystal Si substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Thickness of porous Si: 200 (μm) Porosity: 56 (%) MBE (Molecular Beam Epitaxy) on the P-type (100) porous Si substrate
axy) method to make the Si epitaxial layer 0.5 μm
Low temperature growth. The deposition conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr Growth rate: 0.1 nm / sec Next, a 100 nm oxide layer is formed on the surface of the epitaxial layer, and a 500 nm oxide layer is formed on the oxide surface. The other Si substrate on which the oxide layer was formed was overlapped and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby the two Si substrates were firmly joined.

Thereafter, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50), selective etching without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as an etch stop material, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
The etching rate of the non-porous layer (several tens of millimeters) is a thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 0.5 μm was formed on SiO ₂ .

As a result of observing the cross section with a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

Thereafter, the entire substrate was coated with Si ₃ N ₄ ,
Only the Si ₃ N ₄ on the back surface of the region to be light-transmitting is removed by etching. This substrate is first etched with a fluorinated nitric acid (84:16) solution for 19 minutes, leaving a 10 μm Si substrate. Next, when etching was performed for 10 minutes using a fluorinated nitric acid (1: 3: 8) solution, only the opening of Si ₃ N ₄ was etched, exposing SiO ₂ . After the removal of Si ₃ N ₄ , an SOI substrate having a Si layer having a translucency in a part of the substrate and having a crystallinity superior to that of a Si wafer could be produced.

Reference Example 6 A P-type (100) single-crystal Si substrate was anodized in an HF solution in the same manner as in Reference Example 5, and the resulting P-type (100) porous Si substrate was An Si epitaxial layer was grown at a low temperature of 0.5 μm by a plasma CVD method. The deposition conditions are as follows.

Gas: SiH ₄ High frequency power: 100 W Temperature: 800 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 2.5 nm / sec Next, a 100 nm oxide layer is formed on the surface of the epitaxial layer. The other Si substrate having a 500 nm oxide layer formed on the oxidized surface was overlaid and heated in an oxygen atmosphere at 900 ° C. for 0.5 hour, whereby the two Si substrates were firmly joined.

Thereafter, the bonded substrates are selectively etched while being stirred with a mixed solution (1: 5) of 49% hydrofluoric acid and 30% hydrogen peroxide solution. After 62 minutes, only the single crystal Si layer remains without being etched, and the single crystal Si is etched.
As a stop material, the porous Si substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 62 minutes.
The etching rate of the non-porous layer (several tens of millimeters) is a thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 0.5 μm was formed on SiO ₂ .

Thereafter, the entire substrate was coated with Si ₃ N ₄ ,
Only the Si ₃ N ₄ on the back surface of the region to be light-transmitting is removed by etching. This substrate is first etched with a fluorinated nitric acid (84:16) solution for 19 minutes, leaving a 10 μm Si substrate. Next, when etching was performed for 10 minutes using a fluorinated nitric acid (1: 3: 8) solution, only the opening of Si ₃ N ₄ was etched, exposing SiO ₂ . After the removal of Si ₃ N ₄ , an SOI substrate having a Si layer having a translucency in a part of the substrate and having a crystallinity superior to that of a Si wafer was obtained.

Reference Example 7 Anodization of a P-type (100) single-crystal Si substrate in an HF solution was performed in the same manner as in Reference Example 5, and the resulting P-type (100) porous Si substrate was The Si epitaxial layer was grown at a low temperature of 0.5 μm by the bias sputtering method. The deposition conditions are as follows.

RF frequency: 100 MHz High frequency power: 600 W Temperature: 300 ° C. Ar pressure: 8 × 10 ⁻³ Torr Growth time: 60 minutes Target DC bias: −200 V Substrate DC bias: +5 V Next, the surface of this epitaxial layer is 100 nm. Is formed on the oxidized surface, and SiO ₂ (300
nm) / Si ₃ N ₄ (100 nm) and another Si substrate on which the other Si substrate is formed is superposed at 900 ° C. in a nitrogen atmosphere.
By heating for 0.5 hour, both Si substrates were firmly joined.

Thereafter, the bonded substrates are selectively etched with a mixture of 49% hydrofluoric acid and alcohol (10: 1) without stirring. After 82 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 82 minutes.
The etching rate of the non-porous layer (several tens of millimeters) is a thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 0.5 μm was formed on SiO ₂ / Si ₃ N ₄ .

Thereafter, the entire substrate is covered with Si ₃ N ₄ as an etching prevention film, and Si on the back surface of the region to be light-transmissive is formed.
Only ₃ N ₄ are removed by etching. This substrate is first etched with a hydrofluoric acid (84:16) solution for 19 minutes,
The Si substrate is left by μm. Next, fluorinated nitric acid (1: 3:
8) After etching with the solution for 10 minutes, only the openings of Si ₃ N ₄ were etched, exposing Si ₃ N ₄ . Si
After removing the ₃ N ₄ , a part of the substrate becomes light-transmitting, and the SOI has a Si layer having a crystallinity as excellent as a Si wafer.
The substrate was created.

Reference Example 8 An N-type (100) monocrystal Si substrate having a thickness of 200 μm was anodized in an HF solution under the same conditions as in Example 5 to obtain an N-type (100). A 5 μm low-temperature Si epitaxial layer was grown on a porous Si substrate by a liquid phase growth method. The growth conditions are as follows.

Solvent: Sn Temperature: 900 ° C. Growth atmosphere: H ₂ Growth time: 50 minutes Next, a 100 nm oxide layer is formed on the surface of the epitaxial layer, and a 500 nm oxide layer is formed on the oxide surface. The other Si substrate was stacked and heated at 1000 ° C. for 0.5 hour in a nitrogen atmosphere.
Both Si substrates were firmly joined.

Thereafter, the bonded substrates are selectively etched while stirring with 49% hydrofluoric acid. After 78 minutes, only the single-crystal Si layer remains without being etched, and the single-crystal Si layer remains.
Was used as an etch stop material, the porous Si substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, and is 50 ° even after 78 minutes.
The etching rate of the non-porous layer (several tens of millimeters) is a thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single-crystal Si layer having a thickness of 5 μm was formed on SiO ₂ .

Thereafter, the entire substrate is covered with SiO ₂ as an etching prevention film, and the SiO ₂ on the back surface of the region to be light-transmissive is formed.
Only ₂ is removed by etching. When this substrate was etched with ethylenediamine (17 ml) + water (8 ml) + pyrocatechol (3 g) for 4 hours, only the SiO ₂ opening was etched, exposing the SiO ₂ layer immediately below the Si layer. After removing the SiO _{2 of the} etching prevention film,
An SOI substrate having a Si layer in which a part of the substrate became translucent and having excellent crystallinity comparable to that of a Si wafer was produced.

Reference Example 9 Anodization of a P-type (100) single-crystal Si substrate in an HF solution was performed in the same manner as in Reference Example 5, and the resulting P-type (100) porous Si substrate was By the low pressure CVD method, S
An i-epitaxial layer was grown at 1 μm. The deposition conditions are
It is as follows.

Source gas: SiH ₄ Carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 3.3 nm / sec Next, a 100 nm oxide layer is formed on the surface of the epitaxial layer. On the oxidized surface, another Si substrate having a 500 nm oxide layer formed on the surface is superimposed and heated at 1000 ° C. for 0.5 hour in a nitrogen atmosphere.
Both Si substrates were firmly joined.

Thereafter, the bonded substrate was treated with a mixed solution of buffered hydrofluoric acid (36% NH ₄ F + 4.5% HF + H ₂ O), alcohol and 30% hydrogen peroxide (10: 6:
In step 50), selective etching is performed without stirring. 205
After a minute, only the single-crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single-crystal Si as a material for the etch stop and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 205 minutes.
It is about 0 ° or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of degrees) in the non-porous layer is a practically negligible decrease in film thickness. That is, porous S having a thickness of 200 μm
The i-substrate was removed, and a single-crystal Si layer having a thickness of 1 μm was formed on SiO ₂ .

When SiH ₂ Cl ₂ was used as the source gas, the growth temperature had to be raised by several tens of degrees, but the accelerated etching characteristic peculiar to the porous substrate was maintained.

A MOSFET was formed on a single crystal Si layer. Since a known integrated circuit manufacturing technique is used for the method of manufacturing the MOSFET, the description is omitted here.

Thereafter, the entire substrate is covered with SiO ₂ as an etching prevention film, and the SiO ₂ on the back surface of the region to be light-transmissive is formed.
Only ₂ is removed by etching. This substrate is 6MKO
After etching with H for 200 minutes, only the opening of SiO ₂ was etched, exposing the SiO ₂ layer immediately below the Si layer. After removing the SiO _{2 of the} etching preventing film, an SOI substrate having a Si layer having a part of the substrate light-transmitting and having excellent crystallinity comparable to that of a Si wafer was formed.

Reference Example 10 A 1 μm-thick Si epitaxial layer was grown on a P-type (100) Si substrate having a thickness of 200 μm by a CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min. This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / mi.
n. And a P-type (100) having a thickness of 200 μm
The entire Si substrate was made porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer did not change.

Next, 10 .ANG.
An oxide layer having a thickness of 0 nm is formed.
The other Si substrate on which the 0 nm oxide layer was formed was overlapped and heated in a nitrogen atmosphere at 900 ° C. for 0.5 hour, whereby both Si substrates were firmly joined.

Then, the bonded substrate was mixed with buffered hydrofluoric acid (36% NH ₄ F + 4.5% HF + H ₂ O).
Selective etching is performed while stirring with a mixed solution (1: 5) with 0% hydrogen peroxide solution. After 191 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 191 minutes.
It is about 0 ° or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of degrees) in the non-porous layer is a practically negligible decrease in film thickness. That is, porous S having a thickness of 200 μm
The i-base was removed, and a single-crystal Si layer having a thickness of 1.0 μm was formed on SiO ₂ .

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

Thereafter, the entire substrate was covered with Si ₃ N ₄ ,
Only the Si ₃ N ₄ on the back surface of the region to be light-transmitting is removed by etching. This substrate is first etched with a fluorinated nitric acid (84:16) solution for 19 minutes, leaving a 10 μm Si substrate. Next, when etching was performed for 10 minutes using a fluorinated nitric acid (1: 3: 8) solution, only the opening of Si ₃ N ₄ was etched, exposing SiO ₂ . After the removal of Si ₃ N ₄ , an SOI substrate having a Si layer having a translucency in a part of the substrate and having a crystallinity superior to that of a Si wafer was obtained.

Reference Example 11 A Si epitaxial layer was grown to 5 μm on a P-type (100) Si substrate having a thickness of 200 μm by atmospheric pressure CVD. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. Temperature: 1080 ° C. Pressure: 760 Torr Time: 1 min. The Si substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Porous Si thickness: 200 (μm) Porosity: 56 (%) As described above, in this anodization, P-type (100) Si
Only the substrate was made porous, and there was no change in the Si epitaxial layer.

Next, the surface of the epitaxial layer is
An oxide layer having a thickness of 0 nm is formed.
The other Si substrate on which the 0 nm oxide layer was formed was overlapped and heated in an oxygen atmosphere at 900 ° C. for 0.5 hour, whereby the two Si substrates were firmly joined.

Thereafter, the bonded substrates are selectively etched with a mixture of 49% hydrofluoric acid and alcohol (10: 1) without stirring. After 275 minutes, only the single crystal Si layer remains without being etched, and the single crystal Si is etched.
As a stop material, the porous Si substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 275 minutes.
It is about 0 ° or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of degrees) in the non-porous layer is a practically negligible decrease in film thickness. That is, porous S having a thickness of 200 μm
The i-substrate was removed, and a single-crystal Si layer having a thickness of 5 μm was formed on SiO ₂ .

As a result of observation of a cross section by a transmission electron microscope, S
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

Thereafter, the entire substrate is coated with Si ₃ N ₄ ,
Only the Si ₃ N ₄ on the back surface of the region to be light-transmitting is removed by etching. This substrate is first etched with a fluorinated nitric acid (84:16) solution for 19 minutes, leaving a 10 μm Si substrate. Next, when etching was performed for 10 minutes using a fluorinated nitric acid (1: 3: 8) solution, only the opening of Si ₃ N ₄ was etched, exposing SiO ₂ . After the removal of Si ₃ N ₄ , an SOI substrate having a Si layer having a translucency in a part of the substrate and having a crystallinity superior to that of a Si wafer was obtained.

Reference Example 12 An N-type Si layer was formed to a thickness of 1 μm by ion implantation of protons on the surface of a P-type (100) Si substrate having a thickness of 200 μm.
Formed. The H ⁺ implantation amount is 5 × 10 ¹⁵ (ions / cm ² )
Met. This substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (10 μm) having a thickness of 200 μm.
0) The entire Si substrate was made porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the N-type Si layer did not change.

Next, the surface of the N-type Si layer is
Formed on the oxidized surface, SiO ₂ on the surface
(200 nm) / Si ₃ N ₄ (100 nm) is formed on another Si substrate, and the substrate is placed in an oxygen atmosphere.
By heating at 0 ° C. for 0.5 hour, both Si substrates were firmly joined.

Thereafter, the bonded substrates are selectively etched with buffered hydrofluoric acid (36% NH ₄ F + 4.5% HF + H ₂ O) while stirring. After 258 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single crystal Si as a material for the etch stop, and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, and is 10
It is about 0 ° or less, the selectivity with respect to the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several tens of degrees) in the non-porous layer is a practically negligible decrease in film thickness. That is, porous S having a thickness of 200 μm
i Substrate is removed and 1.0 μm on SiO ₂ / Si ₃ N ₄
A single-crystal Si layer having a thickness of m was formed.

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

Thereafter, the entire substrate is covered with Si ₃ N ₄ as an etching prevention film, and the Si on the back surface of the region to be light-transmissive is formed.
Only ₃ N ₄ are removed by etching. This substrate is first etched with a hydrofluoric acid (84:16) solution for 19 minutes,
The Si substrate is left by μm. Next, fluorinated nitric acid (1: 3:
8) After etching with the solution for 10 minutes, only the openings of Si ₃ N ₄ were etched, exposing Si ₃ N ₄ . After the removal of the Si ₃ N ₄ of the etching prevention film, a SOI substrate having a Si layer in which a part of the substrate became transparent and had excellent crystallinity comparable to that of a Si wafer was produced.

Reference Example 13 A P-type (100) single-crystal Si substrate having a thickness of 500 μm was anodized in a 50% HF solution. The current density at this time was 10 mA / cm ² . A porous layer having a thickness of 20 μm was formed on the surface in 10 minutes. An Si epitaxial layer was grown on the P-type (100) porous Si substrate at a low temperature of 0.5 μm by a low pressure CVD method. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂ (0.6 l / min) H ₂ (100 l / min) Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min Next, the surface of this epitaxial layer Was thermally oxidized by 50 nm. An Si substrate having an 800 nm oxide layer on the surface is superimposed on the thermal oxide film, and 900 ° C. in an oxygen atmosphere.
By heating for 5 hours, both substrates were firmly joined.

Thereafter, 490 μm from the back surface of the Si substrate.
It was removed by grinding to expose the porous layer.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Thereafter, the bonded substrate was treated with a mixture of 49% hydrofluoric acid, alcohol and hydrogen peroxide (10: 6: 5).
In step 0), selective etching is performed without stirring. After 15 minutes, only the single-crystal Si layer remains without being etched, and the single-crystal Si is used as an etch stop material to form a porous Si layer.
The layer was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low.
Å is weak, the selectivity with the etching rate of the porous layer reaches more than ten-fiveth power, and the etching amount (several Å) in the non-porous layer is a film thickness reduction that can be ignored in practical use. Si
₃ After removal of the N ₄ layer, Si having an insulating layer on the surface
A single-crystal Si layer having a thickness of 0.5 μm was formed on the substrate.

[0220] The same effect can also be obtained when apiesone wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si layer can be eliminated.

Thereafter, the entire substrate is coated with SiO ₂ as an etching prevention film, and SiO ₂ on the back surface of the region to be light-transmitting is formed.
Only ₂ is removed by etching. When this substrate was etched with ethylenediamine (17 ml) + water (8 ml) + pyrocatechol (3 g) for 4 hours, only the SiO ₂ opening was etched, exposing the SiO ₂ layer immediately below the Si layer. After removing the SiO _{2 of the} etching prevention film,
An SOI substrate having a Si layer in which a part of the substrate became translucent and having excellent crystallinity comparable to that of a Si wafer was produced.

Reference Example 14 A Si epitaxial layer was grown to 1 μm on a P-type (100) Si substrate by CVD in the same manner as in Reference Example 10, and the substrate was anodized in a 50% HF solution. went.

Next, the surface of the epitaxial layer is
A Si substrate having a 0 nm oxide layer on the surface is superimposed,
By heating at 1100 ° C. for 0.5 hour in a nitrogen atmosphere, both Si substrates were firmly joined.

[0224] Si ₃ N ₄ is deposited to a thickness of 0.1 µm by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Thereafter, the bonded substrates are selectively etched while being stirred with a mixed solution (1: 5) of 49% hydrofluoric acid and hydrogen peroxide solution. After 62 minutes, only the single-crystal Si layer remained without being etched, and the porous Si substrate was selectively etched using the single-crystal Si as a material for the etch stop and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 62 minutes.
The selectivity with the etching rate of the porous layer is as high as ten-fifth power or more, and the etching amount (several tens of square meters) in the non-porous layer is a thickness reduction that can be ignored in practical use. That is, the porous Si substrate having a thickness of 200 μm was removed, and after removing the Si ₃ N ₄ layer, a single-crystal Si layer having a thickness of 1 μm was formed on the insulating substrate.

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

A MOSFET was formed on a single crystal Si layer. Since a known integrated circuit manufacturing technique is used for the method of manufacturing the MOSFET, the description is omitted here.

Thereafter, the entire substrate is covered with SiO ₂ as an etching prevention film, and the SiO ₂ on the back surface of the region to be made transparent is formed.
Only ₂ is removed by etching. This substrate is 6MKO
After etching with H for 200 minutes, only the opening of SiO ₂ was etched, exposing the SiO ₂ layer immediately below the Si layer. After removing the SiO _{2 of the} etching preventing film, an SOI substrate having a Si layer having a part of the substrate light-transmitting and having excellent crystallinity comparable to that of a Si wafer was formed.

[0230] The above reference as illustrated in the examples, a multi-porous Si substrate is removed by a process including at least wet chemical etching of the non-light-transmitting insulator substrate (S
i) a single-crystal semiconductor layer is formed on the surface of the substrate, and a portion of the insulator substrate is moved from the surface on which the single-crystal semiconductor layer is not formed (the back surface) to the insulating layer near the surface. Alternatively, at least until the single crystal semiconductor layer is exposed, the layer is removed by a process including wet chemical etching, and a continuous thin layer is left without a support directly therebelow, and the non-light-transmitting substrate is partially made light-transmitting. be able to.

Further, according to the present embodiment , before changing to a light-transmitting property, an electronic device can be formed at least in a portion to be light-transmitting, and then can be changed to a light-transmitting property by the above-described method.

According to the present embodiment , after a single-crystal Si layer is formed on a non-light-transmitting insulating substrate, the light-transmitting portion is changed to light-transmitting by removing a non-light-transmitting substrate portion only in a necessary region. It is easy to use and does not use a translucent substrate represented by glass, and is excellent in productivity, uniformity, controllability, and economy, and has excellent crystallinity comparable to that of a single crystal wafer. Si
It becomes possible to create a light-transmitting SOI structure substrate having a layer.

Further, the light-transmitting SOI according to the present reference example
The substrate can be used as a viewfinder, a contact sensor, or a translucent substrate for a liquid crystal display, and can be applied to an X-ray mask, a pressure sensor, micromechanics, and the like.

(Embodiment 15) FIG. 18 is a schematic process chart of this embodiment.

P-type (100) having a thickness of 300 μm
Anodizing a single crystal Si substrate in an HF solution,
A porous Si substrate was formed.

Anodizing conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 ( Time) Thickness of porous Si: 300 (μm) Porosity: 56 (%) P-type (100) porous Si substrate 101 thus obtained
The Si epitaxial layer 102 is formed thereon by the low pressure CVD method.
Was grown with a layer thickness of 1.0 μm. The deposition conditions are as follows.

Source gas: SiH ₄ Carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 3.3 nm / sec Next, the surface of the epitaxial layer 102 is exposed to 1000 ° C.
Is formed on the oxidized surface, and 50
The other Si substrate 107 on which the 00 ° oxide layer 104 and the 1000 ° nitride layer 105 are formed is superposed and heated at 800 ° C. for 0.5 hour in a nitrogen atmosphere, thereby firmly bonding the two Si substrates. Was.

Then, the bonded substrates were mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50), and was selectively etched without stirring.
After 65 minutes, only the non-porous Si layer remains without being etched, and single-crystal Si is used as an etch stop material.
The porous Si substrate 101 was selectively etched and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is not more than 50 ° even after 65 minutes, and the selectivity with the etching rate of the porous layer reaches not more than the tenth power. The etching amount (several tens of mm) in the porous layer 101 was negligible for practical use. In this case, the porous Si substrate 101 having a thickness of 200 μm is removed and S
Single crystal Si having a thickness of 1.0 μm on iO ₂ 103
The layer 102 was formed. SiH ₂ C as source gas
When l is used, the growth rate needs to be increased by several tens of degrees, but the accelerated etching characteristic peculiar to the porous substrate is as follows.
Maintained.

A field effect transistor is formed on the single crystal Si thin film 102 and connected to each other to form a complementary element and an integrated circuit thereof, and a pixel switching element and a driving peripheral circuit required for a liquid crystal image display device. Was formed.
The method of manufacturing each transistor is described in a well-known MOS.
Integrated circuit manufacturing technology was used.

After a black matrix and a color filter were formed on the cover glass, a common electrode was formed and an alignment treatment was performed. An active matrix substrate was subjected to an orientation treatment, a seal material was printed, and then both were assembled to inject a liquid crystal. For the various steps relating to the liquid crystal, a known liquid crystal display device manufacturing technique was applied.

Thereafter, the Si substrate 107 below the liquid crystal pixel portion
Was removed by the following method.

A 30% by weight aqueous KOH solution was heated to about 110 ° C., and etching was advanced in the (100) direction of Si using SiN as a mask. The etch rate is anisotropic with respect to the crystal plane, and is about 300 μm with respect to the (100) plane.
/ H. The shape after the etching is shown in FIG. 19, and the angle formed by the slope after the etching is 55 °, indicating that the anisotropy is high. When the insulating layer 104 is reached, the etching is substantially completed. That is, the side etch rate in the lateral direction is very small. According to this method, the Si substrate 107 under the liquid crystal pixel portion can be removed with high accuracy.

Finally, spin-on-glass was filled in the recesses removed for improving the reliability, and a projection type liquid crystal image display device by light transmission was completed.

(Example 16) A liquid crystal image display device was completed in the same manner as in Example 15 except that the Si substrate 107 was removed by the following method.

75 ml of ethylenediamine, catechol 1
A mixed solution prepared at a ratio of 2 g, 24 ml of water and 0.45 g of pyrazine was heated to about 115 ° C., and etching was performed using SiN as a mask. This method has a very high selectivity to SiO ₂ of 1000 or more, and SiO ₂ can be used as a membrane and an etching resistant mask.

(Example 17) A liquid crystal image display device was completed in the same manner as in Example 15 except that the Si substrate 107 was removed by RIE. The etching could be performed almost perpendicularly to the mask pattern.

(Example 18) A liquid crystal image display device was completed in the same manner as in Example 15 except that the Si substrate 107 was removed by the following method.

A 1: 1 aqueous solution of hydrazine and water was added to about 100
C., and anisotropic etching was performed using SiO ₂ as a mask. The etch rate is 2 μm / min.

Example 19 An Al substrate having an Al ₂ O ₃ (ruby) film on its surface was used as a substrate impermeable to light in the visible light region.
A liquid crystal image display device was completed in the same manner as in Example 15 except that Al was removed by plasma etching with an l-based gas.

According to the present invention, since a substrate having anisotropic etching characteristics can be freely selected, a clear liquid crystal surface can be obtained by selecting a ruby film or the like as the substrate as in this embodiment.

Example 20 A liquid crystal image display device was completed in the same manner as in Example 15 except that the Si substrate was removed in the form of an apple as shown in FIG.

According to the present invention, since accurate etching is possible, various patterns can be made to emerge by a backlight as in this embodiment.

[0254] As shown in the above embodiments, the present invention
The liquid crystal image display device uses an Si single crystal substrate which is excellent in economical efficiency, has excellent flatness over a large area, and has extremely excellent crystallinity. Integrates elements and circuits with high radiation resistance, low stray capacitance of the above semiconductor elements, high-speed operation, no latch-up phenomenon, etc. on the same substrate as the liquid crystal image display pixels. A high-performance device can be provided.

Also, the liquid crystal image display device according to the present invention
By selectively removing the porous substrate or the porous layer by anisotropic etching, a high-quality single-crystal layer formed on a non-transparent substrate can be obtained, thereby improving the performance. In addition, by employing a Si substrate for the non-transparent electrode, it can be used as a starting material that is extremely thermally, mechanically, chemically or physically compatible with the conventional silicon integrated circuit process.

In general, when a light source having a considerably high light intensity is used for a projection type liquid crystal image display device, when light hits a peripheral circuit portion, a photoexcitation current is induced in the semiconductor layer, which may cause a malfunction. In the device according to the present invention, since the peripheral circuit portion is shielded from light, such a problem can be avoided.

Further, the liquid crystal image display device according to the present invention
Since a substrate having anisotropic etching characteristics is used as the non-light-transmitting substrate, a portion below the liquid crystal pixel portion can be accurately removed.

Embodiment 21 FIG. 21 shows an outline of the manufacturing process of this embodiment.

P-type (100) having a thickness of 300 μm
Anodizing a single crystal Si substrate in an HF solution,
A porous Si substrate was formed.

Anodizing conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 ( Time) Thickness of porous Si: 300 (μm) Porosity: 56 (%) P-type (100) porous Si substrate 101 thus obtained
The Si epitaxial layer 102 is formed thereon by the low pressure CVD method.
Was grown with a layer thickness of 1.0 μm. The deposition conditions are as follows.

Source gas: SiH ₄ Carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 3.3 nm / sec Next, the surface of the epitaxial layer 102 is exposed to 1000 ° C.
Is formed on the surface of the oxide film.
Oxide layer 104, 1000 ° nitride layer 105 and another Si substrate 107 on which a 2000 ° or more SiH _x insulating layer 106 is formed as a reinforcing material, and heated at 800 ° C. for 0.5 hour in a nitrogen atmosphere. As a result, the two Si substrates were firmly bonded.

Then, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
6:50), and was selectively etched without stirring.
After 65 minutes, only the non-porous Si layer remains without being etched, and single-crystal Si is used as an etch stop material.
The porous Si substrate 101 was selectively etched and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is not more than 50 ° even after 65 minutes, and the selectivity with the etching rate of the porous layer reaches not more than the tenth power. The etching amount (several tens of mm) in the porous layer 101 was negligible for practical use. In this case, the porous Si substrate 101 having a thickness of 200 μm is removed and S
Single crystal Si having a thickness of 1.0 μm on iO ₂ 103
The layer 102 was formed. SiH ₂ C as source gas
When l is used, the growth temperature needs to be raised by several tens of degrees, but the accelerated etching characteristic peculiar to the porous substrate is as follows.
Maintained.

A field effect transistor is formed on the single crystal Si thin film 102 and connected to each other to form a complementary element and an integrated circuit thereof, and a pixel switching element and a driving peripheral circuit required for a liquid crystal image display device. Was formed.
The method of manufacturing each transistor is described in a well-known MOS.
Integrated circuit manufacturing technology was used.

After a black matrix and a color filter were formed on the cover glass, a common electrode was formed and an alignment process was performed. An active matrix substrate was subjected to an orientation treatment, a seal material was printed, and then both were assembled to inject a liquid crystal. For the various steps relating to the liquid crystal, a known liquid crystal display device manufacturing technique was applied.

Then, the Si substrate 107 side is coated with a hydrofluoric acid-resistant rubber except for a portion immediately below the liquid crystal pixel portion, and the Si substrate 107 is partially covered up to the insulating layer 104 using a mixed solution of hydrofluoric acid, acetic acid and nitric acid. Then, the projection type liquid crystal image display device by light transmission was completed.

As in the present embodiment, a substrate formed by bonding a substrate having an insulating film formed on a Si substrate and a substrate obtained by making the Si substrate porous and then epitaxially growing Si on the porous Si is made of a single Si substrate. Since there is no restriction on the underlying insulating film of the crystal film, the thickness can be reduced to several μm, and a SiN film or the like can be used.

Further, by providing a light transmitting film for improving the film strength between the non-light transmitting substrate and the single crystal TFT at the time of producing the SOI substrate, there is no restriction on the production in forming the TFT. , A flexible manufacturing method can be provided. Further, since the reinforcing layer is formed before the removal of the non-light-transmitting layer, damage at the time of removing the non-light-transmitting layer can be avoided.

Reference Example 22 As shown in FIG. 22, the SiN _x insulating layer was subjected to selective etching of silicon (N / P ⁺ ) to leave a 5000 ° Si layer 110 under the insulating film, and the Si layer 110 was 800 ~ 1000 ° C
After thermally oxidizing the Si layer 110 to make it translucent, the SiN _x insulating layer 1 is formed on the thermally oxidized film 110 by CVD.
A liquid crystal image display device was prepared in the same manner as in Example 21 except that No. 11 was formed. According to this embodiment, the strength can be improved by the two-layered reinforcing film.

Further, by forming a light-transmitting thin-film conductive film such as ITO on the SiN _x insulating layer, the back potential can be controlled.

Example 23 As shown in FIG. 23, a liquid crystal image display device was prepared in the same manner as in Example 1 except that Lp-SiN 156 having a large film strength was used as the interlayer insulating film of the SiTFT. Lp-SiN
Adhesion to the problem metal film in the case of using the film as an interlayer insulating film, H ₂ protected effectively, and the like.

With respect to the adhesion to the metal film, the problem can be solved by forming a sandwich structure with a film such as SiO ₂ or BPSG. Regarding the H ₂ protection effect,
Vth (threshold voltage) can be controlled by controlling the impurity concentration of the MOS channel portion in advance.

( Reference Example 24) As shown in FIG. 24, O ⁺ was approximately 1 × 10 ¹⁸ cm ⁻² 200
By ion implantation at kev and performing a heat treatment at about 1300 ° C., an SiO ₂ layer 202 is formed in the substrate 201.

The substrate 201 prepared as described above is subjected to thermal oxidation and LP-CVD to form SiO ₂ 204 / SiN.
two-layered film of _x 205 is formed on the front and back. Subsequently, the back surface is patterned, and the window of the panel portion is opened.

Next, etching of Si is performed using a KOH system or the like. The Lp-SiN film serves as a mask material for KOH. S
In the etching of i, all or part of the etching is performed. Subsequently, this is thermally oxidized, so that only the rear surface of the panel portion is thermally oxidized.

Thereafter, in the step of peeling off the surface SiN film and forming the TFT, the back side is further reinforced by using thermal oxidation and CVD. In particular, the Lp-SiN film 207 used for the LOCOS oxidation method or the like is a tensil film having an internal stress of about 10 ¹⁰ dyn / cm ² , and is optimal as a backside reinforcing film. 209 is a gate electrode, 210 is the source and drain of the MOS transistor.

When the non-light-transmitting substrate 201 is etched from the back surface, the film strength of the light-transmitting region is determined only by the insulating film 202 and the Si layer 203 on the upper surface of the non-light-transmitting substrate. The degree of freedom in the film configuration is narrow. However, according to the present embodiment, the film strength on the back surface can be improved without being restricted by the TFT.

Example 25 As shown in FIG. 25, a liquid crystal image display device was manufactured in the same manner as in Example 21 except that the SiN _x insulating layer 251 was patterned so as to become smaller from the center of the light-transmitting region toward the periphery. Created.

According to this embodiment, the intensity of the light-transmitting region can be adjusted, and the strength at the center of the light-transmitting region, which is particularly weak, can be reinforced.

As described in detail above, the liquid crystal image display device according to the present invention uses an Si single crystal substrate which is economically excellent, has uniform flatness over a large area, and has extremely excellent crystallinity. Since the active element is formed on the Si single crystal layer having extremely few defects, the floating capacitance of the semiconductor element is reduced, high-speed operation is possible, there is no latch-up phenomenon, etc. A high-performance device in which a circuit is integrated on the same substrate as a liquid crystal image display pixel can be provided.

Also, the liquid crystal image display device according to the present invention
By selectively removing the porous substrate or porous layer,
By being formed on a high quality single crystal layer formed on a non-transparent substrate, high performance is obtained. Further, by adopting the Si substrate as the non-transparent substrate, it can be a starting material that is extremely compatible with the conventional silicon integrated circuit process in terms of thermal, mechanical, chemical or physical properties.

In general, when a light source having a considerably high light intensity is used in a projection type liquid crystal image display device, when light hits a peripheral circuit portion, a photoexcitation current is induced in the semiconductor layer, which may cause a malfunction. In the device according to the present invention, since the peripheral circuit portion is shielded from light, such a problem can be avoided.

Furthermore, the liquid crystal image display device according to the present invention
An SiN _x insulating layer is provided in the light-transmitting region where the non-light-transmitting substrate has been removed.
By doing so , the strength of the area is reinforced and reliability is improved.

Embodiment 26 FIG. 26 shows an example of a liquid crystal display device using a CMOS inverter as a peripheral drive circuit and a PMOS transistor as a switching element of a pixel electrode. This drawing is a cross-sectional view of only the substrate on which the semiconductor device such as a transistor is incorporated. 6 in the figure
1 is a supporting substrate, 62 is a base insulating layer, 63 is an element isolation oxide film, 64 is a source region of an NMOS transistor, 65 is a drain region of an NMOS transistor, and 66 is a PMOS.
A drain region of a transistor, 67 a source region of a PMOS transistor, 68 a gate oxide film, 69 a gate electrode, 70 a channel region of an NMOS transistor, 7
1 is a channel region of a PMOS transistor, 72 is an N-type electric field relaxation region, 73 is a P-type electric field relaxation region, and 74 is Al
(Wiring) electrodes, 75 are NMOS transistors, 76, 7
7 is a PMOS transistor, 78 is a storage capacitor, 79 is a CMOS inverter, 80 and 81 are interlayer insulating films, 82 is a common electrode, and 83 is a pixel electrode. 84 is a backside filler,
85 is a back electrode.

The substrate configured as described above and the other substrate provided with the common electrode are arranged to face each other with a spacer interposed therebetween, and liquid crystal is sealed to form a panel.

In the liquid crystal display device, it is an essential condition that light can pass through the image display unit in both the reflection type and the transmission type. Therefore, conventionally, one quartz plate has been used. On the other hand, although Si is generally well known as an active layer of a transistor, it is extremely difficult to produce single crystal Si, which is most desirable as an active layer, and it has been virtually impossible to form it on quartz. Therefore, when a transistor is formed in a pixel display portion or when integrated with peripheral driving circuits, polycrystalline Si that can be formed on quartz has been used.

However, there is a limit in polycrystalline Si in order to make the screen higher in definition and drive at a higher speed in response to a demand for higher quality images, and the structure of a liquid crystal display device having a semiconductor device using single crystal Si is limited. Was desired.

In this embodiment, a semiconductor or conductor is used as a substrate, and a single-crystal Si thin film is formed via an insulating layer.
Only the image display section is made transparent by removing the above-mentioned substrate, and the substrate of the peripheral drive circuit section is provided with control means for the back surface potential to control the substrate potential, thereby improving the performance of the semiconductor device and achieving high speed. It is a liquid crystal display device.

That is, an active matrix type liquid crystal display device having a semiconductor active element in which an active layer is formed by a single crystal Si thin film formed on a semiconductor or conductor substrate via an insulating layer, wherein the image display portion is The substrate is removed and only the insulating layer is removed or a transparent filler is filled after the substrate is removed to have transparency, and the peripheral driving circuit portion has the substrate remaining and has a back surface potential control means. It is characterized by the following.

[0290] Single-crystal Si thin film according to the present embodiment is obtained by a method using a multi-porous Si substrate. The polycrystalline Si thin film obtained by the latter manufacturing method has few defects and is an ideal semiconductor as an active layer of a transistor.

In this embodiment, a CMOS inverter with low power consumption is used for the peripheral drive circuit, a PMOS transistor having high withstand voltage without back surface leakage for switching the pixel electrode, and a P-type Si substrate for the substrate. An equimetal electrode is provided to control the substrate potential. As the translucent filler 84, a Si-based resin was used.

In this example, an 8000 ° Si oxide film was used for the base insulating layer, and a 30% aqueous solution of KOH was used for etching Si, and an etching rate of 4 μm / min was obtained at 100 ° C. At this time, LP-
CVD (Low Pressure Chemical Chemical)
50 deposited by Vapor Deposition
A 00 ° Si nitride film was used. It is desirable that the thickness of this film is large, but if it is 6000 to 8000 ° or more, the film is easily cracked and the etching resistance is deteriorated. Therefore, about 1000-6000 ° is desirable.

FIG. 27 shows the wiring state of the back electrode. In the figure, reference numeral 90 denotes a counter substrate provided with a common electrode, which is disposed to face the substrate with an adhesive 91 and sandwiches a liquid crystal 92. Reference numeral 93 denotes a pad on a driving circuit unit such as a CMOS inverter, which is connected to the package 95 by a bonding wire 94, while the back surface electrode 85 is fixed to the package 95 via a paste conductive material. The potential is controlled by being connected to the package 95 side. The thickness of the Si support substrate is 55
0 μm, which is sufficient to maintain the strength of the entire chip.

FIG. 28 shows another embodiment for realizing this embodiment. FIG. 28 shows a structure in which a back electrode is provided on the upper surface of the device region. Reference numeral 501 denotes a separation layer for separating elements, and reference numeral 502 denotes a back electrode. In this method, an opening 503 penetrating the interlayer insulating film 63 and the base insulating film 62 is formed when the contact hole is processed after the device is formed. 28 was obtained by implanting 1 × 10 ¹⁵ cm ⁻² ions of boron in order to improve the ohmic properties of the contact, forming a low-resistance p-type diffusion layer 504 and then depositing Al.

With this structure, the film could be favorably driven with the thickness (T _BOX ) of the base insulating layer set to 8000 °, V _SS = 0 V, V _DD = 14 V, and the back potential of 2 to 5 V. Then, 64 gradations, with the light transmittance of the display unit being 90% or more,
A liquid crystal display device of 100,000 pixels has been realized.

In the liquid crystal display device of this embodiment, the single crystal Si thin film is used for the active layer of the semiconductor device, so that the semiconductor device used for the entire device is 5 to 10 times smaller than the conventional polycrystalline TFT.
It can be driven 0 times faster, and furthermore, by controlling the back potential, the leakage current of the parasitic element of the semiconductor device used for the peripheral drive circuit can be sufficiently reduced to improve the performance of the circuit. The liquid crystal display device capable of high-definition, high-quality image display with tens of thousands of pixels or more is further made transparent by removing the substrate of the image display unit even in a circuit using single crystal Si. This is a liquid crystal display device having sufficient strength secured above.

(Embodiment 27) In order to eliminate the need for the above bonding, it is conceivable to provide an image display area and peripheral circuits on the same substrate.

FIG. 29 is a schematic sectional view in the case where a liquid crystal pixel portion and peripheral circuits are provided on the same substrate.

As shown in FIG. 29, the same substrate insulating layer 506
Above, an image display area 507 including a pixel TFT and a pixel electrode
And a peripheral circuit 508 for driving the same, are connected to each other by a data line and a gate line, and the image display region is formed by etching a semiconductor substrate with an etching solution such as KOH in order to transmit light. The peripheral circuit area is made transparent and the device characteristics (for example, MOS
Leakage current amount) is affected by the potential on the back surface of the peripheral circuit, and the above structure can be realized by leaving the semiconductor or conductive substrate 509 on the back surface so that a predetermined potential can be applied.

However, when the transparent substrate region and the conductor substrate region are formed on the same substrate, a region 510 where the substrate film thickness changes naturally occurs, and as shown in FIG. When the transition region is reached, the transition region of the conductive substrate has a non-uniform film thickness, so the manner in which an electric field is applied varies, causing variations in device characteristics in peripheral circuits. In the case of reaching the area, there is a problem that the transparency becomes incomplete and defective pixels are caused.

The present embodiment has a portion that is a semiconductor or conductor substrate with an insulating layer interposed therebetween, and a portion that is composed only of an insulating layer. An image display area is provided in a portion consisting of only the layers, the connection between the two is made with the same wiring material as that used in the peripheral circuit and the image display area, and the transition area of the semiconductor or conductor substrate thickness An image display device characterized in that the wiring area is wider than that of the image display device.

That is, in this embodiment, since the peripheral circuit and the image display area do not exist on the transition area, there is no adverse effect on the peripheral circuit.

Here, that the wiring area is wider than the transition area means that the wiring area is preferably not less than the transition area + 0.3 mm. This is a value in consideration of the alignment margin at the position where the transition region is formed, and the transition region does not cover the regions 507 and 508 even if the misalignment occurs.

FIG. 30 is a sectional view of a main part of an image display device according to the present invention, and FIG. 31 is a plan view. The plan view is common to each embodiment described later. 509 is a semiconductor or conductor substrate, 506 is an insulating layer, 508 is a peripheral circuit formation region, 507 is an image display region, 511 is 508 and 507
Are electrically isolated from each other. Reference numeral 510 denotes a transition region of the substrate film thickness.

Peripheral circuit formation area 508 and image display area 5
07 is formed in the semiconductor region on the insulating layer by a semiconductor device manufacturing process. These are electrically isolated by, for example, an element isolation region 511 formed in a LOCOS step, a trench isolation step, a PN junction isolation step, or the like. The wiring member 512 includes the peripheral circuit formation region 508 and the image display region 5.
07, Al, Ti, T
metals such as a, Mo, Cu, W, TiSi ₂ , TaSi
_In addition to silicide such as ₂ , WSi ₂ , and MoSi ₂ , porous Si and ITO are used after a film is deposited by a CVD method, a sputtering method, an evaporation method, or the like, and a desired pattern is formed by a photolithography process.

These wiring members 512 are usually formed with a thickness of several thousand Å and a width of about 1 to 100 μm.

The peripheral circuit 508 is formed on a semiconductor or conductive substrate excluding the transition region 510, and
Reference numeral 07 is formed on a transparent substrate excluding the transition region, electrically insulates both regions from each other, and connects a desired terminal with a wiring member 512 to form a peripheral circuit with less characteristic variation and an image display with less image defects. The region can be formed on the same substrate, and a high-resolution image display device capable of fine patterning at low cost can be realized.

(Embodiment 28) FIG. 32 is a cross-sectional view of main parts showing another embodiment of the image display device according to the present invention.

In the embodiment shown in FIG. 32, the wiring member has two layers (51
3,514) provided in the case of the multiple wiring.
In addition to the effects described above, there is a strong advantage against disconnection. The transition region of the film thickness resulting from the etching generally has a width of several hundred μm. For example, if wirings are formed at a pitch of 10 μm in the transition region having a width of 500 μm, the length is 500 μm and the width is 7 μm.
The regions 508 and 507 must be connected by a long and thin wiring, and disconnection of the wiring is a serious problem. With a multi-wiring structure, redundancy is increased and resistance to disconnection is increased. Various combinations in the case of multiplex wiring are conceivable.
3 is Al, 514 is polycrystalline Si, 513 is ITO, 51
4 is Al or the like. In addition, three or more wiring members can be provided.

(Example 29) FIG. 33 shows the case where single crystal Si is used for the wiring member. FIG. 33 (a) shows single crystal Si 516 on the surface and FIG.
Shows a case where single crystal Si 516 is formed by embedding.
Single crystal Si 516 is electrically insulated from isolation region 511.

When a single crystal wiring is used, a wiring having a low resistance of several tens of Ω / □ can be formed without deteriorating the flatness of the substrate surface. For example, when the present invention is used in a liquid crystal display device, it is caused by a step. Disorder of liquid crystal alignment can be reduced.

(Embodiment 30) FIG. 34 shows a case where the peripheral circuit 508 and the image display unit 507 have a completely separated structure.

In this embodiment, since the peripheral circuit 508 and the image display unit 507 are completely separated from each other, they are not only insulated, but also the capacitive coupling between them is reduced. Problems such as talk and malfunction of the peripheral circuit 508 are reduced.

Reference Example 31 The present embodiment shown in FIG. 35 is an example of a liquid crystal display device manufactured by a general semiconductor manufacturing process. Peripheral circuit 508
The image display area 507 is formed in the semiconductor layer on the insulating layer, and both are insulated by the LOCOS insulating film 517. Further, the wiring member 512 is formed by the LOCOS 51
7 formed on the peripheral circuit 5 through a contact hole.
08 and the image display area 507 are mutually connected. L
A semiconductor substrate 509 is provided below the peripheral circuit with a certain region of the OCOS 517 as a boundary, and the potential of the semiconductor substrate 509 is set to a desired value V _Ref to suppress variations in device characteristics. 515
Is an insulating film for preventing the wiring 512 and the regions 508 and 507 from being short-circuited at unnecessary places.

[0315] The foregoing description has been made as an example a display device using the TFT, is not limited to the TFT in the present invention, an active matrix liquid crystal display device and a driving circuit using a diode, an MIM element It goes without saying that a similar effect can be obtained even in a built-in simple matrix type liquid crystal display device.

The connection between the image display section and the peripheral circuit can be made at low cost by fine patterning. In addition, since the peripheral circuit is reliably formed on the semiconductor or conductive substrate, variations in device characteristics of the peripheral circuit are reduced. It is possible to reduce an area of an image defect where transparency is incomplete.

(Example 32) Next, an active matrix type liquid crystal display device using the characteristics of a CMOS inverter and using it in a peripheral drive circuit and using PMOS transistors as switching elements will be described.

FIG. 36A shows an equivalent circuit of each pixel of the liquid crystal display device. 520 is a gate electrode, 521 is a storage capacitor, and 522 is a liquid crystal capacitor. In a conventional liquid crystal display device, the active layer of the transistor is a polycrystalline Si thin film.

At present, as described above, it is general that a circuit is formed by combining a plurality of types of semiconductor devices, for example, in one display device. However, semiconductor devices have different characteristics, and by forming a plurality of types of semiconductor devices on the same substrate, it is not possible to set optimal conditions for each device, and the problems of each device cannot be solved. It will also be used.

FIG. 36B shows a SIMOX (Separa)
Tion by Implanted Oxigen)
NMOS transistor 523 formed using a substrate, P
4 shows an equivalent circuit of a CMOS inverter having a MOS transistor 524. On the substrate side of the CMOS inverter,
A parasitic MOS transistor having a supporting substrate as a gate electrode and an insulating layer between the supporting substrate and an active layer as a gate insulating layer is generated. In the case of a conventional CMOS inverter, this parasitic MOS
It is difficult to increase the absolute value of the threshold voltage of the transistor, setting V _back to any value, the parasitic N
The MOS or PMOS transistor operates and leak current flows. FIG. 36C shows the input / output characteristics of this CMOS transistor. As shown in this figure, V _back
= In the vicinity of 0V, due to the leakage current of the PMOS transistor even if V _in is close to the V _DD in order to parasitic PMOS transistor is in operation, the output is not completely drop to V _SS. On the other hand V _back = in the vicinity of 3V, V _in order to parasitic NMOS transistor is operating even if close to the V _SS NM
The output is completely V
Does not go up to _DD .

Although the CMOS inverter has the above-mentioned problems, the NMOS transistor formed on a thin film single crystal can be used alone to form, for example, a “kink” in which there is a step in static characteristics.
A phenomenon has been observed, and in order to alleviate this phenomenon, it is necessary to provide a passage through which the generated hole escapes.

In a PMOS transistor, the driving speed is limited by the parasitic capacitance between the source / drain and the channel region.

As described above, the characteristics of the semiconductor active elements are different from each other, and the required characteristics and conditions are also different depending on the application in which the semiconductor active elements are incorporated. If a plurality of semiconductor active elements are formed on the same substrate, May be contradictory, and a method for obtaining more desired characteristics has been desired.

[0324] The present inventors have result of intensive studies to solve the above problems, paying attention to the characteristics of the semiconductor active element can be Oh Ru degree controlled by the thickness of the active layer, to achieve the present embodiment Reached. For example, in order to improve the input / output characteristics of the above-mentioned CMOS inverter, the active layer is made thicker than before, and in order to design a fully depleted type with priority on high-speed driving, the active layer is made thinner. It is effective to design a thick active layer to prevent the occurrence of a voltage drop, and to thicken the active layers of the NMOS and PMOS transistors to provide withstand voltage.

In the present embodiment, in view of the above viewpoint, in a semiconductor device using a plurality of semiconductor active elements, in order to obtain more excellent characteristics, means for controlling the film thickness of the active layer in accordance with the required characteristics. It was taken.

That is, in this embodiment, in a semiconductor device having a plurality of semiconductor active elements having an active layer formed of a single crystal semiconductor thin film formed on an insulating layer, the thickness of the active layer of the semiconductor active element is at least 2 It is intended to provide a semiconductor device characterized in that there are different types. This implementation
In the example , the plurality of semiconductor active elements include not only the case where a plurality of types of elements are used but also the case where a plurality of the same elements are used.

Further, the present embodiment is an active matrix type liquid crystal display device using the above-mentioned means and using a CMOS inverter as a peripheral drive circuit and a PMOS or NMOS transistor as a pixel switching element. An object of the present invention is to provide a liquid crystal display device wherein the thickness of the active layer is larger than the thickness of the active layer of the switching element.

A method for forming a different active layer according to this embodiment will be described.

The active layer is made of a single crystal semiconductor thin film. For convenience of explanation, the most commonly used Si will be described. As a method of forming single-crystal Si thin film, after the single-crystal Si thin film is epitaxially grown on the porous Si substrate, etched porous Si substrate by bonding the substrate. Thus single-crystal Si thin film obtained by almost no defects, Ru can perform high-speed driving.

The single-crystal Si layer according to this embodiment is made of porous Si obtained by making the single-crystal Si substrate porous as in the above-described embodiment.
It is formed using a substrate.

Next, a method of changing the thickness of the active layer will be described.

FIG. 37 shows two methods. First, a support substrate 525 having a single crystal Si layer 527 on a base insulating layer 526 is prepared, and the surface is thermally oxidized at 100 to 500 ° to form a pad SiO ₂ layer 528. After depositing a SiN layer 529 at 1000 to 3000 ° by LP-CVD, patterning is performed to obtain FIG. Next, the portion of the single crystal Si from which the SiO ₂ layer 528 and the SiN layer 529 have been removed is etched from the surface using a chlorine-based gas. For example, when the thickness of the original Si layer 527 is 10000, etching is performed at 2000 to 6000. Thus, FIG. 37B is obtained. After this, the SiO ₂ layer 528, Si
When the N layer 529 is sequentially removed, a thick single-crystal Si layer A and a thin single-crystal Si layer B are obtained. Further, after preparing (a), by performing a heat treatment in an oxygen or steam gas atmosphere at 900 to 1200 ° C., only the portion not covered with the SiN layer 529 can be oxidized (c). Original Si
When the thickness of the layer 527 is 10000 °, the selected SiO ₂
Oxidize the layer to 6000-15000 °. Thereafter, unnecessary portions including the selective SiO ₂ layer are etched to obtain a single crystal Si layer having a different thickness (b).

Thus, the semiconductor active element is formed by changing the thickness of the single crystal Si according to the design conditions.

In the present embodiment, in the case of a semiconductor device having a plurality of semiconductor active elements, each active layer is changed to a desired state, and as a result, active layers having different thicknesses exist in the same device. The characteristics of each element are improved, and the performance of the entire device is improved.

More specifically, the film thickness is set according to the purpose of the apparatus. For example, when a high withstand voltage and a high voltage are required, it is effective to set the film thickness thick. This is effective not only in improving the performance of individual transistors but also in suppressing the operation of a parasitic element (for example, a parasitic PMOS transistor or the like) by increasing the film thickness. When high speed is required at a relatively low voltage, a thin film is desirable.
The thin film is effective not only for improving the performance of each transistor but also for improving the characteristics of the entire circuit mainly due to the effect of reducing the parasitic capacitance.

The optimum value of the thickness of the active layer according to the present embodiment differs depending on the intended apparatus. For example, in the case of an NMOS transistor, the generation of hot carriers is more remarkable than in the case of a PMOS transistor, so that the withstand voltage tends to decrease. Therefore, in circuits requiring high withstand voltage and high voltage, NMOS
The optimum value of the active layer of the transistor is thicker than that of the PMOS transistor.

FIG. 38 is a sectional view showing an embodiment of the liquid crystal display device according to the present invention. The basic configuration is the same as that of the liquid crystal display device shown in FIG. 26 described above, and duplicate description will be omitted. In this embodiment, the CM used for the peripheral drive circuit is used.
The thickness of the active layer of the OS inverter 59 is large,
On the other hand, the active layer of the PMOS transistor 57 used for switching the pixel electrode is 2000-600.
0 °. In addition, the active layers of the PMOS transistor and the NMOS transistor in the CMOS inverter of the drive circuit are respectively junction-separated. In the present embodiment, since the active layer is formed by the above-described method for manufacturing a single-crystal Si thin film, a Si substrate is used as the support substrate 61, and a hollow portion 84 in which a display portion requiring transparency is etched away. However, since the single-crystal Si thin film can be formed on a transparent substrate such as glass, the entire surface can be a glass substrate.

FIG. 39 (a) shows an equivalent circuit diagram of this embodiment. Reference numeral 300 denotes a horizontal shift register for driving the signal line 310, reference numerals 301 to 303 denote red (R), green (G), and blue (B) video signal lines, respectively, and reference numeral 304 denotes a MOS for transferring a signal to a buffer capacity by MOS. Transistor, 30
5 is a buffer capacity for temporarily storing the signal of each signal line,
306 is a MOS transistor switch for transferring the signal stored in the buffer capacity to the pixel unit, 307 is a liquid crystal capacity, 308 is a vertical shift register for driving the gate line 69, and 309 is a display unit. As shown in b), the display portion 309 is a hollow portion 84 from which the supporting substrate is removed, and the portion where the peripheral driving circuit is formed is S
This is the remaining opaque portion 312 of the i-substrate.

In this embodiment, the PM used for the drive circuit
Since the OS and the sources and drains 64 to 67 of the NMOS transistors 55 and 56 are separated from the base oxide film 12 by several thousand degrees or more, even if an inversion layer is formed on the upper surface of the base oxide film 12 by the potential of the supporting substrate, the source No current flows between the drain / drain. Therefore there is no need to issue the operation of a parasitic MOS transistor, the input-output characteristic, V _DD
= 8 V, V _SS = −6 V, base insulating film thickness = 5000 °, and shows the ideal curve shown in FIG.

As described above, the distance from the bottom surface of the source / drain to the top surface of the base oxide film depends on the impurity concentration of the channel region, because the MOS transistor using the base oxide film as the gate oxide film does not operate. , 2000
It is preferable to set the temperature to about 10,000 °. Even without this distance, the operation can be controlled by increasing the absolute value of the threshold value of the parasitic MOS transistor.

In this embodiment, since the parasitic transistor can be sufficiently turned off even with a relatively small thickness of the base insulating film of 5000 °, high voltage driving can be easily performed.
In this embodiment, since V _DD -V _SS = 14 V is possible,
A voltage of ± 5 V or more can be applied to the liquid crystal used for the liquid crystal display. As a result, a liquid crystal panel having 100,000 pixels or more was realized with a high gradation of 64 gradations or more.

In this embodiment, a PMOS transistor is used for the switching element in the pixel portion. However, a similar configuration can be made by using an NMOS transistor.

Reference Example 33 Next, as another reference example, SOI (Silicon) was used.
FIG. 40A shows an LSI realized by a CMOS circuit formed on an “on-insulator”. In the figure, 411 is a supporting substrate, 412 is a base insulating layer, 413 is an element isolation oxide film, 414 is an NMOS source region, 415 is an NMOS drain region, 416 is a PMOS drain region, 417 is a PMOS source region, 418 is a gate oxide film, 419 is a gate electrode, 420 is an NMOS channel region, 421 is a PMOS channel region, 424 to 427 are electrodes, 440
Is an interlayer insulating film. In this embodiment, the active layer thickness of the NMOS transistor is 4000 to 10,000
The active layer thickness of the S transistor is 500 to 3000 °.

As shown in the figure, the source 414 and the drain 415 of the NMOS transistor do not reach the underlying insulating layer. The static characteristics of the NMOS and PMOS transistors are shown in FIGS. Thus, the normal NMOS
"Kink" seen in the transistor is not seen,
Since no leakage current flows on the back surface, the support substrate 411
Can be set freely within the range of 0 to + 7V.

When a CMOS ring oscillator and a shift register were constructed using the NMOS and PMOS transistors of this embodiment, the operation of the ring oscillator and the shift register was confirmed within the gate length range of 0.2 to 3.0 μm. Since the breakdown voltage of the NMOS transistor was improved, it was possible to drive 7 V even with a gate length of 0.5 μm.

When this embodiment is applied, for example, a normal CM
In an OS inverter, a PMOS transistor and an NMOS transistor
In order to improve the degree of freedom in circuit design by equalizing the current driving power of the transistors and making the on / off characteristics equal, PMOS
Although the area of the transistor and the area of the NMOS transistor are changed, the area of the NMOS transistor can be reduced by changing the thickness of the active layer to improve the degree of integration of the entire device.

( Reference Example 34) FIG. 41 shows still another reference example. In this embodiment, 10
High breakdown voltage MOSFET of more than V and fully depleted high-speed CMOS
This is a semiconductor device in which logic is integrated. In the figure, 611
Is a supporting substrate, 612 is a base insulating layer, 613 is an element isolation oxide film, 614 is an NMOS source region, and 615 is an NMOS.
A drain region 616 is a PMOS drain region;
Is a PMOS source region, 618 is a gate oxide film, 619
Is a gate electrode, 620 is an NMOS channel region, 621
Is a PMOS channel region, 624 is a high-breakdown-voltage NMOS source and drain electrode, 625 is a CMOS logic-side PMOS and NMOS transistor electrode, 640 is an interlayer insulating film, 643 is a high-breakdown-voltage NMOS drain electric field relaxation region, and 644 is a high-breakdown-voltage NMOS. Source area, 645 is NM
This is an OS drain region.

The high-breakdown-voltage NMOS FET of this embodiment showed a withstand voltage of 15 V or more as shown in FIG. 42 without the hole generated near the drain deteriorating the withstand voltage.
This is because the thickness of the active layer was increased to secure a hole escape route. On the other hand, although the NMOS transistor in the logic section has a thin active layer and a withstand voltage of 8 V, the drain and source capacitances are small, and the same circuit formed on the bulk due to the complete depletion of the channel section. The operation speed was improved about twice as much as that of FIG.

[0349] (Reference Example 35) Still another reference example in FIG. 43, a high speed Bi-CMOS
1 shows a cross section of a main part of an SRAM (static random access memory using a CMOS inverter of a bipolar transistor).

First, the SRAM will be briefly described. FIG. 44 shows an overall configuration diagram of a static RAM mounted with a logic circuit in this embodiment. Clock shaping circuit 7 described later
The clock input from 05 is divided into six by the first stage clock driver A 701 and drives the next stage clock driver B 703. The first-stage clock driver A 701 is formed on a gate array 704 having 1000 gates together with a part of the clock driver B 703 and a logic circuit (for example, a flip-flop 702). The area around the gate array 704 is SRA
M macro cells are arranged in a 512 word × 18 bit configuration, and an input / output circuit 706 surrounds them.

Next, the details of the SRAM macro cell will be described with reference to FIG.
It is shown in FIG. One macro cell has 64 word lines (horizontal lines) and a 9-bit data line (2 lines per cell).
Main <br/> Mo Li cells 811 arranged in an array in the vertical direction of the line) on the certain word line driver 64 for driving the word lines 1 to 64: 809 and 810, for selecting a word line Decoder 802, an address latch 801 for temporarily storing a code for selecting a word line, a current switch 803 for writing data to a selected memory cell 811, and a sense switch for reading data written in each memory cell 811. The portion surrounded by a broken line as an array 1 of 804 including an amplifier 808, an output buffer 807 for amplifying the read data, and a discharge circuit 806 for erasing the memory cell data is repeated many times on the chip. I have. However, the figure shows that the word line driver is common between the arrays.

The details of the clock shaping circuit in FIG. 44 are shown in FIG.
6 is shown. The clock shaping circuit is a circuit for eliminating delays in rising and falling of the input signals P1 and N1 and obtaining a more ideal pulse signal as the outputs P0 and N0, and a buffer 902 for differentially amplifying the input signals. , A shaping circuit 903 constituted by differential amplification, and a delay circuit 901. V _CC indicates a high voltage side power supply, and V _EE indicates a low voltage side power supply.

In this embodiment, the word driver, the current switch, the discharge circuit and the pulse shaping circuit are constituted by bipolar transistors, and the other circuit sections are constituted by CMOS inverters.

Next, the CMOS inverter and the bipolar transistor shown in FIG. 43 will be described. 43, reference numeral 711 denotes a support substrate, 712 denotes a base insulating layer, 713 denotes an element isolation oxide film, 714 denotes an NMOS source region, and 715 denotes N.
MOS drain region, 716 is a PMOS drain region,
717 is a PMOS source region, 718 is a gate oxide film,
719 is a gate electrode, 720 is an NMOS channel region,
721 is a PMOS channel region, 724 is an NMOS source electrode, 725 is an NMOS drain electrode, and 726 is PM
OS drain electrode, 727 is a PMOS source electrode, 73
0 is NPN bipolar transistor, 731 is NMOS
Transistor 732 is a PMOS transistor 740
Is a collector buried layer, 741 is a collector extraction layer, 742
Is an intrinsic collector region, 743 is a p-type base region, 744
Is an n ⁺ type emitter region, 745 is an emitter region, and 746 is an emitter region.
Is a collector region, 747 is a base region, 748 is an emitter electrode, and 750 is an interlayer insulating film.

In this embodiment, the thickness of the active layer is set to 1.0 μm in order to sufficiently reduce the resistance of the buried collector layer.
The MOS transistor side is a fully depleted type in order to reduce the junction capacitance, and has an active layer thickness of 500 to 3000 °.

In this embodiment, the capacity of the collector substrate is almost zero.
fF. Further, by using the SOI MOS, the power consumption could be reduced to 1/10, though the speed was reduced by about 10% as compared with the logic having the bipolar configuration.

As specifically described in the present embodiment, the semiconductor active element has different characteristics and conditions required depending on the application, and in order to satisfy different requirements on the same substrate, it is necessary to use a semiconductor active layer. The structure of the present embodiment for sufficiently obtaining the required characteristics by changing the film thickness is a very simple and effective means. According to the present embodiment , it is possible to obtain a semiconductor device having higher performance than the conventional one without increasing the cost.

[0358]

As described above, according to the present invention, an excellent driving element which solves the conventional problems can be obtained, and an excellent liquid crystal image display device having high image quality can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a conventional active matrix type liquid crystal display device.

FIG. 2 is a schematic diagram for explaining a basic process of one embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining a basic process of another embodiment of the present invention.

FIG. 4 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 5 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 6 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 7 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 8 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 9 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 10 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 11 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 12 is a schematic diagram for explaining a basic process of the embodiment of the present invention.

FIG. 13 is a schematic view for explaining a basic process of another embodiment of the present invention.

FIG. 14 is a schematic diagram for explaining a basic process of another embodiment of the present invention.

FIG. 15 is a schematic diagram for explaining a basic process of another embodiment of the present invention.

FIG. 16 is a schematic diagram showing the relationship between the thickness of a base insulating layer and the operating voltage of a CMOS.

FIG. 17 is a schematic view for explaining a method for manufacturing a semiconductor substrate portion of the liquid crystal display device of the present invention.

18 is a schematic diagram for explaining a manufacturing <br/> granulation process of a liquid crystal display equipment according to an embodiment 15 of the present invention.

19 is a schematic diagram for explaining a state of the liquid <br/> crystal pixel subordinate side of the liquid crystal display device according to Embodiment 16 of the present invention.

It is a schematic view for explaining a state of the liquid <br/> crystal pixel subordinate side of the liquid crystal display device according to an embodiment 20 of Figure 20 the present invention.

21 is a schematic diagram for explaining a manufacturing <br/> granulation process of a liquid crystal display equipment according to an embodiment 21 of the present invention.

LCD equipment according Reference Example 22 [Figure 22] The present invention
It is a schematic sectional view showing a.

FIG. 23 is a schematic sectional view showing a part of a liquid crystal display device according to Embodiment 23 of the present invention.

According Reference Example 24 [Figure 24] The present invention is a schematic diagram for explaining a manufacturing process of a liquid crystal display device.

FIG. 25 is a schematic bottom view showing a part of a liquid crystal display device according to Embodiment 25 of the present invention.

FIG. 26 is a schematic sectional view showing a liquid crystal display device according to Embodiment 26 of the present invention.

FIG. 27 is a schematic sectional view showing a wiring state of a back electrode of a liquid crystal display device according to Embodiment 26 of the present invention.

FIG. 28 is a schematic sectional view showing another wiring state of the back electrode of the liquid crystal display device according to Embodiment 26 of the present invention.

29 is a schematic view illustrating a portion of the liquid crystal display device according to the present invention.

FIG. 30 is a schematic sectional view showing a part of a liquid crystal display device according to Embodiment 27 of the present invention.

FIG. 31 is a schematic plan view of a liquid crystal display device according to Embodiment 27 of the present invention.

FIG. 32 is a schematic sectional view showing a part of a liquid crystal display device according to Embodiment 28 of the present invention.

FIG. 33 is a schematic sectional view showing a part of a liquid crystal display device according to Embodiment 29 of the present invention.

FIG. 34 is a schematic sectional view showing a part of a liquid crystal display according to Embodiment 30 of the present invention.

FIG. 35 is a schematic cross-sectional view of a portion of a liquid crystal display device according to Reference Example 31 of the present invention.

FIG. 36 is a schematic diagram for explaining the operation of the MOS transistor.

FIG. 37: Changing the thickness of the single crystal Si layer according to the present invention
It is a schematic diagram explaining a method .

FIG. 38 is a schematic sectional view showing a liquid crystal display device according to Embodiment 32 of the present invention.

FIG. 39 is a schematic diagram for explaining a circuit configuration of a liquid crystal display device according to Embodiment 32 of the present invention.

FIG. 40 is a schematic diagram for explaining a CMOS transistor included in an LSI according to a thirty-third embodiment of the present invention;

41 is a schematic sectional view of a CMOS circuit according to Reference Example 34 of the present invention.

FIG. 42 is a graph showing characteristics of a MOS transistor according to Reference Example 34 of the present invention .

43 is a schematic cross-sectional view of the SRAM according to Reference Example 35 of the present invention.

FIG. 44 is a schematic diagram for explaining the configuration of a circuit block of the SRAM in accordance with Reference Example 35 of the present invention.

FIG. 45 is a circuit configuration diagram of the SRAM shown in FIG. 44;

FIG. 46 is a circuit configuration diagram of a clock shaping circuit used in Embodiment 35 of the present invention.

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/786 H01L 29/78 626C 627Z 627D (31) Priority claim number Japanese Patent Application No. 4-40490 (32) Priority date 1992 January 31 (199.2.1.31) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-40448 (32) Priority date January 31, 1992 (1992. 1.31) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-40453 (32) Priority date January 31, 1992 (199.2.1.31) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-40449 (32) Priority date January 31, 1992 (199.2.1.31) (33) Priority claim country Japan (JP) (72) Inventor Junichi Hoshi 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Akira Ishizaki Tokyo 3-30-2 Shimomaruko, Ta-ku Canon Inc. (72) Inventor Tetsunobu Kochi 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Narutari Sugawa Daejeon, Tokyo 3-30-2 Shimomaruko-ku Canon Inc. (72) Inventor Shunsuke Inoue 3-30-2 Shimomaruko 3-chome Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Toru Koizumi 3-chome Shimomaruko, Ota-ku, Tokyo 30-2 Canon Inc. (72) Inventor Takanori Watanabe 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Mamoru Miyawaki 3-30-2 Shimomaruko, Ota-ku, Tokyo No. Canon Inc. (56) References JP-A-4-299317 (JP, A) JP-A-2-198428 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1368 G02F 1/13 101 G02F 1/1333 500

Claims (7)

(57) [Claims] 1. A and a substrate and a liquid crystal pixel portions formed on said substrate, in the manufacturing method of the liquid crystal image display device lower portion of the liquid crystal pixel portion in the substrate is translucent, porous Single crystal semiconductor formed on a first substrate
The layer is bonded to the non-light-transmitting second substrate via the light-transmitting insulating layer.
Then, the first substrate is removed by a process including etching, and the liquid crystal pixel portion is formed on the light-transmitting insulating layer of the second substrate.
After the formation of the second pixel, the second
A part of the base is not provided with the single crystal semiconductor layer.
A method for manufacturing a liquid crystal image display device, characterized in that a light transmitting portion is formed by removing the light from the surface side so that light can enter the liquid crystal pixel portion. 2. A Following removal of the first substrate, a manufacturing method of claim 1 a liquid crystal image display device, wherein further comprising the step of forming a semiconductor element on the monocrystalline semiconductor layer. 3. A liquid crystal image display according to claim 1, wherein said first substrate is made porous by anodization
Device manufacturing method. 4. A process according to claim 1 liquid crystal image display device according the first substrate, characterized in that it consists of Si. 5. The method according to claim 1, wherein said single crystal semiconductor layer is made of Si . 6. The method according to claim 1, wherein said second substrate is made of Si . 7. The method according to claim 1, wherein the etching is wet etching.