JP3157274B2 - Optical semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device in which a photodiode and a bipolar IC are integrated.

[0002]

2. Description of the Related Art An optical semiconductor device in which a light receiving element and a peripheral circuit are integrated and formed in a monolithic manner is different from a hybrid IC in which a light receiving element and a circuit element are separately manufactured, and cost reduction can be expected. It has the advantage of being strong against noise due to external electromagnetic fields.

[0003] As a conventional structure of such an optical semiconductor device, for example, one described in Japanese Patent Application Laid-Open No. 1-205564 is known. This is shown in FIG. In the figure,
(1) is a P-type semiconductor substrate, (2) is a P-type epitaxial layer, (3) is an N-type epitaxial layer, and (4) is a P-type epitaxial layer.
^{A +} type isolation region, (5) an N ⁺ type diffusion region, (6) an N ⁺ type buried layer, (7) a P type base region, and (8) an N ⁺ type emitter region. The photodiode ( 9 ) is formed by a PN junction of a P-type epitaxial layer (2) and an N-type epitaxial layer (3), the N ⁺ type diffusion region (5) is taken as a cathode, and the isolation region (4) is taken as an anode. Things. The NPN transistor ( 10 ) has a buried layer (6) provided at the boundary between the P-type epitaxial layer (2) and the N-type epitaxial layer (3), and uses the N-type epitaxial layer (3) as a collector. Then, an acceleration electric field is formed by the auto-doped layer (11) from the substrate (1), thereby facilitating the movement of carriers generated in a region deeper than the depletion layer.

[0004] Such a device is molded with a resin through which light having the wavelength of the optical signal can pass because of the necessity of receiving the optical signal. In addition, even in a region such as the NPN transistor ( 10 ), light-generated carriers are generated by light incidence, and these carriers cause a parasitic effect or a malfunction. Therefore, it is necessary to provide the IC chip with a means for irradiating light only to the photodiode ( 9 ).

The simplest method as the above means is to use an Al wiring layer using a multilayer wiring technology as a light shielding film. That is, after connecting the elements in a single-layer or multilayer structure, the IC is interposed via an interlayer insulating film made of a polyimide resin.
An Al film is formed on the entire surface of the chip, and the photodiode ( 9 ) portion of the Al film is opened to form a window for light incidence.

[0006]

However, if the polyimide resin is coated on the polyimide resin with an Al film having a certain area or more, heating (300 to 400
It is known that the temperature of (° C.) causes the Al film to bulge. This blister is considered to be caused by moisture adhering to the resin because the polyimide resin is hygroscopic, and the moisture is evaporated by heat treatment.
Therefore, when covering with an Al film, it is necessary to provide a gas vent hole for each certain area (detailed in Japanese Patent Publication No. 58-46853). On the other hand, if a vent hole is provided, light naturally enters from there, and photo-generated carriers are generated in unnecessary portions, resulting in a parasitic effect,
It may cause malfunction.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has a through hole (50) for venting gas in a light shielding film (42). No circuit element is arranged below, and the epitaxial layers (25) and (24) to which light reaches are separated by a P ⁺ separation region ( 26 ), and the photo-generated carriers generated in the separated region are separated by V _CC or GND.
By letting the gas escape into the chamber, both gas release and prevention of malfunction are achieved. Further, by providing a P ⁺ buried layer at the bottom of the circuit element disposed around the through hole, malfunction prevention is more effectively performed.

[0008]

According to the present invention, the through holes (5) are formed in the light shielding film (42).
By providing 0), the gas generated from the polyimide resin can be exhausted from the through hole (50). Therefore, Al
No blistering of the film occurs. On the other hand, no circuit element is arranged below the through hole (50) (dummy photodiodes are arranged), and the photogenerated carriers generated here are released to a fixed potential. Then, the P ⁺ buried layer (5
3) forms a barrier between the substrate (23) and the first epitaxial layer (24), so that the substrate (23)
The movement of minority carriers (electrons) generated in the step can be prevented.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described in detail. First, the overall outline will be described with reference to FIG.
I do. FIG. 4 shows a photodiode (21) And NPN Transient
Star (22FIG. Same figure
Wherein (23) is a P-type single-crystal silicon semiconductor substrate.
Plate (24) is non-plated on the substrate (23)
First epitaxy with a thickness of 15 to 20 .mu.
Layer (25) is on the first epitaxial layer (24)
With phosphorous (P) doping by vapor phase epitaxy
6 μm second epitaxial layer. Substrate (23)
Has lower impurity concentration than that of general bipolar IC
The first epitaxial layer having a specific resistance of 40 to 60 Ωcm is used.
The axial layer (24) is formed by laminating non-doped layers.
To form a diffusion region of 1000 Ω · cm or more during lamination.
200 to 1500 after completion of heat treatment
It has a specific resistance of Ω · cm. Second epitaxial layer
(25) is that phosphorus (P) is 10 ^Fifteen-10¹⁶cm^-3About Do
The specific resistance of 0.5-3.0Ωcm
Have.

First and second epitaxial layers (24)
(25) is a P that completely penetrates both ⁺Type separation area (2
6) By the photodiode (21) Forming part and NPN
Transistor (22) Formed part and electrically separated
You. This separation area (26) Is from the surface of the substrate (23)
A first separation region (27) diffused downward;
2 from the boundary between the epitaxial layers (24) and (25)
A second isolation region (28) diffused in the direction;
Third isolation region formed from the surface of the axial layer (25)
(29) and the first and second
The epitaxial layers (24) and (25) are separated into islands.

On the surface of the second epitaxial layer (25) in the photodiode ( 21 ) portion, the photodiode ( 21 )
To form an N ⁺ -type diffusion region (30) for taking out the cathode. When the N ⁺ -type diffusion region (30) is expanded to substantially the entire surface of the first island region, the take-out series resistance of the cathode can be reduced. The oxide film on the N ⁺ type diffusion region (30) is partially opened, and an antireflection film (31) is formed so as to cover the opening and directly contact the silicon surface. The antireflection film (31) is composed of a silicon nitride film (SiN) having a thickness of 400 to 1000 ° and a silicon oxide film (SiO ₂ ) having a thickness of 4000 to 7000 °. A part of the antireflection film (31) is removed, and the cathode electrode (32) makes ohmic contact with the N ⁺ type diffusion region (30) through the contact hole in the removed part. Further, the isolation region ( 26 ) is used as the anode-side low-resistance extraction region of the photodiode ( 21 ), and the anode electrode (33) contacts the surface of the isolation region ( 26 ).

At the boundary between the first and second epitaxial layers (24) and (25) of the NPN transistor ( 22 ),
An N ⁺ type buried layer (34) is buried. Second epitaxial layer (25) above buried layer (34)
On the surface, a P-type base region (35), an N ⁺ -type emitter region (36), and an N ⁺ -type collector contact region (37) of the NPN transistor ( 22 ) are formed.
On each diffusion region, an electrode wiring (3
8) makes ohmic contact via the contact hole.
The anode electrode (32) and the cathode electrode (33)
Is based on the first wiring layer. PIX on it
And the second-layer electrode wiring (4).
0) is provided. The electrode wirings (38) and (39) extend over the insulating film to electrically connect the elements, the photodiode ( 21 ) functions as an optical signal input section, and the NPN transistor ( 22 ) functions as a signal processing circuit together with other elements. Constitute.

On the electrode wiring (40), PIX (Hitachi Chemical:
Film thickness of 1.0 to 2.
0 μm interlayer insulating film (41) covers the interlayer insulating film (41)
A light-shielding film (42) of a third-layer Al film is formed thereon. The light-shielding film (42) is again covered with a jacket coat made of a polyimide resin. Then, the interlayer insulating films (39) and (41) on the photodiode ( 21 ) and the light shielding film (4)
2), and the jacket coat is removed for light incidence, and the entire chip is molded with an epoxy resin having a light refractive index equivalent to that of a silicon oxide film and transmitting light of a wavelength of an optical signal. Is done.

[0014] photodiode (21), the such V _CC potential of + 5V to the cathode electrode (32), an anode electrode (3
3) The device is operated in a reverse bias state in which a GND potential is applied. When such a reverse bias is applied, the first and second epitaxial layers (24) (2) of the photodiode ( 21 ) are
The depletion layer extends from the boundary of 5), and particularly greatly expands in the first epitaxial layer (24) since the first epitaxial layer (24) is a high resistivity layer. The depletion layer easily spreads to the substrate (23) and has a thickness of 20 to 2 mm.
An extremely thick depletion layer of 5 μ can be obtained. Therefore, the junction capacitance of the photodiode ( 21 ) is reduced, and high-speed response is enabled.

Subsequently, the details of the through-hole which is a feature of the present invention will be described. FIG. 1 is a sectional view showing a through hole (50), and FIG.
Is a plan view. The light-shielding film (42) covering the polyimide interlayer insulating film (41) covers most of the area other than the photodiode ( 21 ) and has a through-hole (50) not shown in FIG. The through hole (50) is 10μ ×
The light-shielding film (42) has a size of about 10 μ
A large number of portions are provided at regular intervals so as not to be continuous with an area of 00 μ × 300 μ or more.

The lower portion of the through hole (50) is provided with an interlayer insulating film (4).
1) (39), a silicon oxide film, a second epitaxial layer (25), a first epitaxial layer (24), and a substrate (23) are continuous. The area (in the dotted line) into which the light passing through the through-hole (50) is incident is surrounded by P ⁺
It is electrically separated from the others by the separation region ( 26 ). The incident area forms a dummy photodiode with a PIN junction from the second epitaxial layer (25) to the substrate (23). The surface of the second epitaxial layer (25) provided with N ⁺ -type contact region (51), applying a V _{C C} potential by electrode (52). With this, the substrate (2
3 by the applied GND and said V _CC to) a dummy photodiode is reverse biased in the same manner as photodiode (21).

A circuit element such as an NPN transistor ( 22 ) is disposed in an island region separated by the separation region ( 26 ) and adjacent to the through hole (50). A P ⁺ buried layer (53) is formed at the bottom of the circuit element. The circuit element is configured using the second epitaxial layer (25),
The first epitaxial layer (24) is not used. Therefore, the P ⁺ buried layer (53) can be formed at the boundary between the substrate (23) and the first epitaxial layer (24) without any trouble. Further, if the first isolation region (27), which is a part of the isolation region ( 26 ), is expanded to form a P ⁺ buried layer (53), the P ⁺ buried layer (53) can be easily formed without requiring an additional step.

Naturally, when light enters from the through hole (50) of the light shielding film (42), electron-hole pairs are generated in the dummy photodiode. What greatly contributes to the parasitic effect and malfunction is the behavior of electrons, which are minority carriers in the electron-hole pairs generated near the substrate (23). These electrons are quickly extracted by the electrode (52) to which V _CC is applied because the region where light is incident is electrically separated by the P ⁺ separation region ( 26 ) and is reverse-biased. . Further, since there is provided the substrate P ⁺ buried layer of high impurity concentration than (23) (53) between the substrate (23) and the first epitaxial layer (24), P ⁺ buried layer, as shown in FIG. 3 A barrier according to (53) is formed. Therefore, the minority carriers generated on the substrate (23) are difficult to move to the circuit element side. Therefore, even an adjacent circuit element can be prevented from malfunctioning due to light-generated minority carriers.

The area of the region where the light passing through the through-hole (50) is incident can be calculated from the refractive index of each material and the incident angle according to equation (1). sin θ ₁ / sin θ ₂ = n ₂ / n ₁ (1) where θ ₁ is the incident angle, θ ₂ is the outgoing angle, n ₁ is the refractive index of the incident side material, and n ₂ is the outgoing side material. It is a refractive index.

FIG. 3 shows the result calculated by the equation (1). Since the light that has entered in the substantially horizontal direction with respect to the surface of the semiconductor package theoretically spreads the most, if it is calculated how much the light that has entered in the substantially horizontal direction spreads, it is possible to determine the area where the light is incident. it can. In FIG. 4, since this element is molded with a resin having a refractive index of 1.45,
When the outgoing angle is calculated from the refractive index n = 1.0 of the outside air and the incident angle ≒ 90 ° (horizontal light) by the equation (1), the outgoing angle is 43 °. The next material change is at the interface between the resin and the jacket coat. In the through-hole (50), the interlayer insulating films (41) and (39) exist under the jacket coat, and these are all made of polyimide resin.
1) Up to (39) can be regarded as the same material layer.
Calculated from the incident angle of 43 ° and the refractive index of polyimide = 1.78, the emission angle of this region is 34 °. Thereafter, similarly calculated, it becomes 44.5 ° for the oxide film and 17 ° for the silicon (epitaxial layer). After that, the area of the region where the light passing through the through hole (50) is incident is calculated in consideration of the film thickness of each material.

A P ⁺ separation region ( 26 ) is arranged so as to surround the region calculated in this way. However, the electrode (52) is not arranged in a portion where light is expected to enter, in order to avoid unnecessary light scattering. Further, since the distance between the contact region and (51) P ⁺ isolation region (26) is defined by the breakdown voltage (V _{C C} between and GND), to determine the position of the consideration to the isolation region (26) . In FIG. 2, the contact region (5
The reason why the P ⁺ isolation region ( 26 ) on the side provided with 1) is arranged farther than the others is due to the above two points.

As described above, according to the present invention, the gas generated by the polyimide resin can be exhausted by providing the through hole (50) in the light shielding film (42), and at the same time, the carrier generated by the light passing through the through hole (50) is removed. it is possible to suck in V _CC potential, but also can prevent parasitic effects or malfunction. In addition, since a P ⁺ buried layer (53) is provided at the bottom of the circuit element adjacent to the through hole (50) to form a barrier for minority carriers, it is possible to prevent minority carriers from moving to the circuit element side, and to reduce parasitic effects. The effect and the prevention of malfunction can be further ensured.

Further, as in this embodiment, the P ⁺ buried layer (5
If 3) is formed in the first isolation region (27), it can be performed without adding a process. Furthermore, even if the first isolation region (27) is expanded, the second and third isolation regions (28)
Since (29) does not expand, the circuit element is inserted through the through-hole (50).
The chip size does not increase due to the expansion of the first isolation region (27).

The above embodiment is described using a three-layer Al as an example.
However, two-layer Al, four-layer Al, or the like can be similarly implemented.
Furthermore, in addition to the through hole (50), a photodiode (2
1A configuration that also extends the first separation region (27) of the
Through-hole (50) and photodiode (21) Excluding only part
Forming first isolation region (27) over the entire surface of chip
It is good.

[0025]

As described above, according to the present invention,
By providing the through-hole (50), the gas generated from the polyimide resin can escape from the through-hole (50), so that the blistering phenomenon of the light shielding film (42) can be prevented. On the other hand, for light that cannot be blocked by providing the through hole (50), no circuit element is arranged below the through hole (50), and the carrier generated as a dummy photodiode is sucked out. And adverse effects (parasitic effects and malfunctions) on other circuit elements can be prevented.

Further, by providing a P ⁺ buried layer (53) at the bottom of the circuit element around the through hole (50) and forming a barrier against minority carriers, the above-mentioned parasitic effect,
Malfunction prevention can be more completely prevented. P
^{If the} buried layer (53) is formed by expanding the first isolation region (27), which is a part of isolation, as in the present embodiment, no additional process is required, and the chip size is reduced. There is no increase.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a diagram for explaining the present invention.

FIG. 4 is a diagram for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (2)

(57) [Claims] 1. A photodiode for inputting an optical signal and a transistor for a signal processing circuit are formed on the same substrate, and a region excluding a region of the photodiode is covered with a light-shielding film. In an optical semiconductor device in which transistors are connected and the light-shielding film and the wiring layer are interlayer-insulated with a polyimide-based insulating film, a large number of through-holes are provided in the light-shielding film, and light passing through the through-holes is provided. No circuit element is arranged in the semiconductor region that reaches, a periphery of the semiconductor region in which the incident light reaches is surrounded by a high-concentration separation region, and a circuit element is arranged around the separation region, and a substrate is provided on the bottom of the circuit element. the same conductivity type a buried layer of high impurity concentration than the substrate provided with the optical semiconductor device you characterized in that escape photogenerated carriers generated in the semiconductor region where the light reaches the fixed potential. Wherein said isolation region comprises coupled a plurality of regions, wherein some of them and forming the buried layer extends to the bottom of the circuit element
Item 1. Optical semiconductor device according to item 1.