JP3173461B2 - Pseudo-normal test circuit and pseudo-normal test method for memory patrol function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a pseudo-normal test circuit and a pseudo-normal test method for checking the normality of an error detection function using a memory patrol.

[0002]

2. Description of the Related Art A memory patrol function is used particularly for early detection of a memory failure. This memory patrol function is generally implemented over the entire memory while the hardware changes the patrol address. When trying to confirm the normality of the error detection function by the memory patrol, it was necessary to wait until the memory patrol came to a certain test address. For this reason, depending on the test execution timing, the time required for the test is not constant, and an apparatus having a large memory capacity may take a very long time.

[0003]

In particular, in recent years, the memory capacity per device has been increased, and the time required for one round of patrol has been increased. Therefore, it is required to shorten the time required for the pseudo normal test of the memory patrol function. Have been.

[0004] JP-A-5-233472, JP-A-6-233
-67989, JP-A-6-149685,
JP-A-6-290114, JP-A-9-44411
JP-A-9-91206 discloses an error detection / correction method using a memory patrol, but does not disclose a test method for confirming the normality of the operation. Japanese Unexamined Patent Publication No. Hei 3-9801 describes a test for the normality of the operation of a memory error detection / correction circuit. However, this test aims at simplification of the circuit and does not shorten the test time.

A main object of the present invention is to provide a pseudo normal test circuit of a memory patrol function which shortens a test time in a normality test of an error detection function by a memory patrol.

[0006]

According to the present invention, there is provided a pseudo normal test circuit for confirming the normality of an error detection function by a memory patrol, wherein a memory access mode for storing a normal memory access operation or a memory control register access operation is stored. A memory access mode control unit that includes a mode setting register and outputs a control signal in accordance with a mode stored in the memory access mode setting register; and a patrol start address setting register, and includes a control signal input from the memory access mode control unit. Identify whether the operation is a memory access operation or a memory control register access operation, perform a normal memory read / write operation during the memory access operation, and stop the memory patrol operation during the memory control register access operation ,
Set the patrol start address to the start address setting register.
And write a normal value to the test address in the memory.
After setting the error check bit lock,
Write a fault value different from the normal value to the
Set bit unlock to restart the memory patrol operation.
Is started, characterized in that it comprises, a memory access controller to start the normality test error detection function according to the memory patrol from the specified address in the patrol start address setting register.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram of a pseudo normal test circuit having a memory patrol function according to an embodiment of the present invention. The pseudo normal test circuit shown in FIG. 1 includes a ROM 3 for storing software, an MPU 1, a memory access mode control unit 4, and a memory access control unit 5, and performs a normality check of the patrol function for the memory 6, that is, a pseudo normal test. Do.

The memory access mode control unit 4 includes a memory access mode setting register 10 and, according to the value of the memory access mode setting register 10, requests the memory access control unit 5 to perform a normal memory access or a memory control register access. And outputs a control signal for identifying.

The memory access control unit 5 includes a patrol start address setting register 7 as a memory control register.
And an error check bit lock / release setting register 8 and a patrol operation stop / start instruction register 9 for performing a memory access control operation in accordance with a control signal input from the memory access mode control unit 4.

The memory 6 is a memory having an error check bit for an error check function for each word.

The software in the ROM 3 controls the memory access mode setting register 10 in the memory access mode control unit 4 and the registers 7 to 9 in the memory access control unit 5.

The pseudo normal test circuit of the memory patrol function holds the memory address specified by the software in the patrol start address setting register 7 and starts the next patrol operation from the address in this register.

Next, the operation of this embodiment will be described with reference to FIG.
This will be described with reference to FIG. FIG. 2 is a flowchart for explaining the operation of this embodiment.

The memory access mode control unit 4 stores the memory access mode set by software in the register 10 and outputs a control signal to the memory access control unit 5 according to the mode.

The memory access control unit 5 identifies a memory access operation or a memory control register access operation based on a control signal input from the memory access mode control unit 4.

In a memory access operation, a normal memory read / write operation is performed, and in a memory control register access operation, a specified register read or write operation is performed.

In this embodiment, the memory control register access operation includes patrol start address setting, error check bit lock / release setting, and patrol function stop / start instruction.

First, software in the ROM 3 instructs the patrol operation stop / start instruction register 9 to stop the patrol operation, and the patrol operation stops (step 100).

Next, a patrol start address is set in the patrol start address setting register 7 (step 110). The closer the set value is to the memory address to be tested, the shorter the time required for the pseudo normal test.

After writing a normal value, for example, "1" to the test address in the memory (step 120), an error check bit lock is set in the error check bit lock / release setting register 8 (step 130).
A failure value different from the normal value, for example, "0" is written to the memory (step 140). This causes a mismatch between the memory value and the error check bit in a pseudo manner.

Then, error check bit lock release is set in the error check bit lock / release setting register 8 (step 150), and the patrol operation stop / start instruction register 9 is instructed to restart the patrol operation (step 160).

In this embodiment, the number of patrol operations from the patrol start address to the memory test address is determined. Therefore, when the patrol check reaches the test address after a predetermined time, whether the memory pseudo-normal error is correctly detected is determined. You can check

Next, as another embodiment of the present invention,
Although the basic configuration is as described above, a pseudo-normal test of error notification a plurality of times will be described.

In the flowchart shown in FIG. 2, after the patrol start address is set, the process from writing the memory normal value to locking the error check bit and writing the memory fault value is repeated a plurality of times for different memory addresses. For example, if it is repeated at five locations on the memory, it can be used as a pseudo-normal test for specifications such as reporting a failure process five times when an error is detected.

[0026]

As described above, the pseudo-normal test circuit for the memory patrol function of the present invention has the patrol start address setting register, and stores the memory address specified by software in the patrol start address setting register. In order to start the next patrol operation from the address in this register, the time required for false normal error detection, that is, the test time, depends on how far the patrol start address is set from the memory address to be tested. This has the effect of being constant and short regardless of the memory capacity.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a pseudo normal test circuit having a memory patrol function according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating the operation of this embodiment.

[Explanation of symbols]

 1 MPU 2 RAM 3 ROM 4 Memory access mode control unit 5 Memory access control unit 6 Memory 7 Patrol start address setting register 8 Error check bit lock / release setting register 9 Patrol operation stop / start instruction register 10 Memory access mode setting register 100 to 170 processing steps

Claims (4)

(57) [Claims] 1. A pseudo-normal test circuit for confirming the normality of an error detection function by a memory patrol, comprising: a memory access mode setting register for storing a mode of a normal memory access operation or a memory control register access operation; A memory access mode control unit that outputs a control signal in accordance with a mode stored in a mode setting register; and a patrol start address setting register. The control signal input from the memory access mode control unit controls a memory access operation or a memory control. A register access operation is identified, a normal memory read / write operation is performed during a memory access operation, and a memory patrol operation is stopped during a memory control register access operation, and a patrol is started for the patrol start address setting register. After setting the address and writing the normal value to the test address in the memory, set the error check bit lock, write the fault value different from the normal value to the memory, set the error check bit lock release, and set the memory patrol operation And a memory access control unit for starting a normality test of an error detection function by a memory patrol from an address designated by the patrol start address setting register. circuit. 2. A pseudo-normal test circuit for a memory patrol function according to claim 1, wherein after writing a normal value to a test address in the memory, an error check bit lock is set to cause a fault in the memory different from the normal value. A pseudo normal test circuit for a memory patrol function, wherein writing of a value is repeated a plurality of times for different memory addresses. 3. A quasi-normal test method for confirming the normality of an error detection function by a memory patrol. A step of instructing patrol operation to stop and patrol operation being stopped, and setting a patrol start address to a patrol start address setting register. After setting, write a normal value to the test address in the memory, set the error check bit lock and write a failure value different from the normal value to the memory, and set the error check bit unlock and patrol Restarting the operation; and a pseudo-normal test method for a memory patrol function. 4. A pseudo-normal test method for a memory patrol function according to claim 3, wherein after writing a normal value to a test address in the memory, an error check bit lock is set and a fault different from the normal value is set in the memory. A pseudo normal test method for a memory patrol function, wherein a step of writing a value is repeated a plurality of times for different memory addresses.