JP3175982B2 - Reference voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a reference voltage in a semiconductor integrated circuit, and particularly to a circuit having a low current consumption.
The present invention also relates to a reference voltage generation circuit that can stably generate a reference voltage even when noise is mixed.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of a conventional reference voltage generating circuit. In this circuit, a constant reference voltage VREF is obtained at an output terminal 52 by dividing the power supply voltage by a pair of resistors 50 and 51.

[0003]

By the way, the value of the reference voltage VREF fluctuates due to mixing of noise. In order to prevent such voltage fluctuations due to noise, it is necessary to reduce the resistance values of the resistors 50 and 51 to lower the impedance between the power supply potential and the ground potential.
However, there is a problem that the current consumption constantly increases by lowering the impedance.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a reference voltage generating circuit which has a small steady current consumption and a small fluctuation of the reference voltage due to noise. .

[0005]

A reference voltage generating circuit according to the present invention comprises a first resistor having one end connected to a first potential, the other end connected to a reference voltage output terminal, and a second end connected to a second output terminal. A second resistor having the other end connected to the output terminal, a first transistor having a collector connected to the first potential, and an emitter connected to the output terminal. A second transistor having a collector connected to the second potential and an emitter connected to the output terminal, and having the same value as a voltage appearing at the output terminal by the first and second resistors. Bias means for supplying the DC bias voltage to the bases of the first and second transistors.

[0006]

In the reference voltage generating circuit configured as described above, the voltage at the output terminal fluctuates, and the potential difference between the DC bias voltage and the voltage at the output terminal becomes the forward voltage between the base and emitter of the first or second transistor. Exceeds the first or second
One of the transistors conducts and rapidly charges or discharges the output terminal in a direction to absorb the voltage fluctuation of the output terminal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a reference voltage generating circuit according to a first embodiment of the present invention. The reference voltage generating circuit of this embodiment includes four resistors 10 to 13, a reference voltage output terminal 14, a PNP-type bipolar transistor 15, and an NPN-type bipolar transistor 16.

One end of the resistor 10 is connected to the ground potential,
The other end is connected to the output terminal 14. One end of the resistor 11 is connected to a positive power supply potential, and the other end is connected to the output terminal 14. Therefore, the potential difference between the power supply potential and the ground potential is divided by the resistors 10 and 11, and the divided voltage is output from the output terminal 14 as the reference voltage VREF.

The collector of the PNP-type bipolar transistor 15 is connected to the ground potential, and the emitter is connected to the output terminal 14. NPN type bipolar transistor 16
Is connected to a positive power supply potential, and the emitter is connected to the output terminal 14.

The two resistors 12 and 13 are connected in series between a positive power supply potential and a ground potential. The resistors 12 and 13 generate a DC bias voltage VB0 by dividing the potential difference between the power supply potential and the ground potential in the same manner as the resistors 10 and 11. This bias voltage VB0 is applied to both transistors 1
Supplied to 5, 16 bases. The value of the bias voltage VB0 is set to be equal to the reference voltage VREF. That is, assuming that the resistance values of the resistors 10, 11, 12, and 13 are R10, R11, R12, and R13, respectively, R10: R11 = R
The resistance ratio between the two resistors 12 and 13 is set so as to satisfy the relationship of 12: R13. Further, the resistance values of the resistors 12 and 13 are set high enough to supply a sufficient base current to one of the transistors 15 and 16, so that the DC current flowing from the power supply potential to the ground potential is minimized. . Here, the operation of the reference voltage generating circuit when noise is superimposed on the reference voltage VREF will be described with reference to the waveform diagram of FIG.

First, the case where the reference voltage VREF rises above the design voltage VA due to noise will be described. By the way, the forward voltage between the base and the emitter is determined by the material of the substrate on which the transistor is formed.
It is assumed that the voltage is, for example, 0.6 V in the transistors 15 and 16. Therefore, when the reference voltage VREF becomes higher than the bias voltage VB0 by 0.6 V, a voltage of 0.6 V is applied between the base and the emitter of the transistor 15, so that a base current flows through the transistor 15.
Then, since the emitter current flows in the transistor 15, the reference voltage VREF appearing at the output terminal 14 to which the emitter is connected decreases. As a result, the reference voltage V
The noise component of (VA + 0.6) V or more contained in REF is absorbed by the ground potential.

Next, a case where the reference voltage VREF is lowered by noise will be described. Reference voltage VREF is bias voltage V
When the voltage becomes 0.6V lower than BO, a voltage of 0.6V is applied between the base and the emitter of the transistor 16, and the transistor 16
Base current flows through 16. Then, a collector current flows in the transistor 16, and the design voltage VREF appearing at the output terminal 14 to which the emitter is connected increases. As a result, a noise component of (VA + 0.6) V or less included in the reference voltage VREF is absorbed by the power supply potential.

Therefore, in the circuit of the first embodiment,
Due to the operation of the transistors 15 and 16, the reference voltage VREF does not fluctuate more than 0.6 V from the design voltage VA.
For this reason, it is not necessary to suppress the fluctuation of the reference voltage VREF by reducing the resistance values of the resistors 10 and 11. Therefore,
It is possible to set the resistance values of the resistors 10 and 11 high,
Steady current consumption can be reduced.

FIG. 3 is a circuit diagram of a reference voltage generating circuit according to a second embodiment of the present invention. This embodiment differs from the embodiment of FIG. 1 in that different bias voltages are supplied to the bases of the transistors 15 and 16, and the other points are the same as those of the embodiment of FIG. . Therefore, in FIG. 3, the portions corresponding to FIG. 1 are denoted by the same reference numerals, and only different portions will be described.

That is, the bias voltage VB1 supplied to the base of the PNP transistor 15 is formed by two resistors 17 and 18 connected in series between the power supply potential and the ground potential. The bias voltage VB2 supplied to the base is formed by two resistors 19 and 20 connected in series between the power supply potential and the ground potential.

Since the two resistors 17 and 18 and the resistors 19 and 20 connected in series are inserted between the positive power supply potential and the ground potential, a direct current flows through each of them. However, in order to suppress the value of the DC current as in the circuit of the first embodiment, the values of the resistors 17 to 20 are set to such a high value that a sufficiently large base current can be supplied to one of the transistors 15 and 16. Therefore, the value of this DC current is small.

The value of the DC bias voltage VB1 is equal to the value of the transistor in a normal state where noise is not mixed.
15 is set so that the base current does not flow, but the base current flows to the transistor 15 due to a slight change in the reference voltage VREF. Since the forward voltage between the base and the emitter of the transistor 15 is 0.6 V, the bias voltage VB1
Is lower than (VREF-0.6) V, the transistor 15
, The voltage between the base and the emitter becomes 0.6 V or more, and a base current flows. Therefore, for example, when the reference voltage VREF is 0.
The value of the bias voltage VB1 is set to (VREF−0 .0) so that the base current flows through the transistor 13 when the voltage rises by 2V.
4) Set to V.

The value of the DC bias voltage VB2 is set such that the base current does not flow through the transistor 16 in a normal state where noise is not mixed, but the base current flows through the transistor 16 due to a slight change in the reference voltage VREF. I do. Now, since the base-emitter forward voltage of the transistor 16 is 0.6 V, the bias voltage VB2 becomes (VRE
When the voltage is higher than (F + 0.6) V, the voltage between the base and the emitter of the transistor 16 becomes 0.6 V or more, and a base current flows. Therefore, for example, the value of the bias voltage VB2 is set to (VREF + 0.4) V so that the base current flows through the transistor 16 when the reference voltage VREF becomes lower by 0.2V.

In the circuit of the second embodiment, the reference voltage VREF
FIG. 4 shows a waveform diagram in the case where noise is applied to the data. Now, when the reference voltage VREF becomes higher than the design voltage VA by 0.2 V due to noise, the potential difference between the bias voltage VB1 between the base and the emitter of the transistor 15 and the voltage VREF becomes 0.6 V. Electric current flows. Then, since an emitter current flows in the transistor 15, the output terminal to which the emitter is connected is output.
The voltage of 14 drops. As a result, a noise component of (VA + 0.2) V or more contained in the reference voltage VREF is absorbed by the ground potential.

When the reference voltage VREF falls below the design voltage VA by 0.2 V due to noise, the bias voltage VB2, which is the voltage between the base and the emitter of the transistor 16, and the voltage VB
Since the potential difference from REF becomes 0.6 V, the transistor 16
, The base current flows. Then, since a current flows through the collector of the transistor 16, the voltage appearing at the output terminal 14 to which the emitter is connected decreases. As a result, a noise component of (VA-0.2) V or less contained in the reference voltage VREF is absorbed by the power supply potential.

In the circuit of the second embodiment, the transistor
Since the base bias voltages 15 and 16 can be set individually, the fluctuation voltage of the reference voltage VREF can be made smaller than that of the circuit of the first embodiment, for example, 0.2 V. Further, the resistances of the resistors 10 and 11 can be set high as in the circuit of the first embodiment, and the resistances of the resistors 17 to 20 can be set high as well. Current consumption can be reduced.

[0023]

As described above, according to the present invention, it is possible to provide a reference voltage generating circuit which consumes less steady current and has less fluctuation of the reference voltage due to noise.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a reference voltage generation circuit according to a first embodiment of the present invention.

FIG. 2 is an output voltage waveform diagram of the embodiment circuit of FIG. 1;

FIG. 3 is a circuit diagram of a reference voltage generation circuit according to a second embodiment of the present invention.

FIG. 4 is an output voltage waveform diagram of the embodiment circuit of FIG. 2;

FIG. 5 is a circuit diagram of a conventional reference voltage generation circuit.

[Description of Signs] 10, 11, 12, 13, 17, 18, 19, 20: resistor, 14: output terminal, 15: PNP-type bipolar transistor, 16: NP
N-type bipolar transistor.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shinichi Oserai 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa In-house Toshiba Microelectronics Corporation (56) References JP-A-59-108425 (JP, A) JP-A-59-143426 (JP, A) JP-A-62-119613 (JP, A) JP-A-52-112754 (JP, A) JP-A-64-61808 (JP, A) JP-A-3-273320 (JP) (A) JP-A-3-55613 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G05F 3/22 H03F 1/30 H03K 19/00

Claims (2)

(57) [Claims] 1. A first resistor having one end connected to a first potential, the other end connected to an output terminal of a reference voltage, and one end connected to a second potential, and the other end connected to the output terminal. A connected second resistor, a collector connected to the first potential, an emitter connected to the output terminal, a first transistor of a first polarity, and a collector connected to the second potential; A second transistor having an emitter connected to the output terminal, a second transistor having a second polarity, and the first and second resistors generating a DC bias voltage having the same value as the voltage appearing at the output terminal to generate the first and second DC bias voltages. A reference voltage generation circuit, comprising: a bias generation unit that supplies a bias to a base of the two transistors. 2. A first resistor having one end connected to a first potential and the other end connected to an output terminal of a reference voltage, one end connected to a second potential, and the other end connected to the output terminal. A first bipolar transistor having a first polarity, a collector connected to the first potential, an emitter connected to the output terminal, and a collector connected to the second potential; A second bipolar transistor having a second polarity whose emitter is connected to the output terminal; and a base-emitter sequence of the first bipolar transistor with respect to a voltage appearing at the output terminal by the first and second resistors. A first DC bias voltage which is higher than a voltage lower by the direction voltage and which is supplied to a base of the first bipolar transistor by a first bias generating means and output by the first and second resistors. A second DC bias voltage which is lower than a voltage obtained by adding a forward voltage between the base and the emitter of the second bipolar transistor to the voltage appearing at the terminal, and is supplied to the base of the second transistor. A reference voltage generation circuit, comprising: a bias generation unit.