JP3178894B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for improving a wiring pattern structure in a semiconductor device.

[0002]

2. Description of the Related Art As is well known, high speed, low power consumption and high integration are required for LSI, and in order to realize these demands, miniaturization of circuit patterns is an essential technology. Has become. Logic LSIs such as microcomputers and memory LSIs such as dynamic RAMs and static RAMs all have a minimum circuit pattern dimension (pattern size) of, for example, 1.0 to 1.2 μm.
It is miniaturized from about one to about 0.8 μm,
In the future, the formation of finer circuit patterns of about 0.5 to 0.6 μm or less will be required.

At the same time as the miniaturization of such circuit patterns progresses, the formation of wiring patterns for each LSI is also called a so-called multilayer wiring such as a one-layer structure or a two-layer structure or a three-layer structure. Multilayer technology has been promoted, and this technology has also become very important, and this technology is also becoming essential for realizing future demands.

In particular, when the minimum circuit pattern size is 0.5
It is said that in an LSI that requires formation of a circuit pattern of about 0.6 μm or smaller, it is necessary to form a wiring pattern having a multilayer structure.

FIG. 5 shows a wiring pattern of a generally adopted multilayer structure. FIG. 5A is a top view, and FIG. 5B is a cross-sectional view. In each of the drawings, reference numeral 51 denotes a first interlayer film having, for example, a silicon oxide film (hereinafter abbreviated as SiO ₂ film) as a main component, and 52 denotes a metal film or a polycrystalline film on the first interlayer film 51, for example. It is a first wiring pattern formed of a silicon film.

Reference numeral 53 denotes a second interlayer film which is formed on the entire surface of the first interlayer film 51 and the first wiring pattern 52 and has, for example, a SiO ₂ film as a main component. Reference numeral 54 denotes a second wiring pattern formed of a thin film mainly containing a metal such as aluminum. In the example shown in this figure,
Although the second wiring pattern 54 is orthogonal to the first wiring pattern 52, there are a part where the same pattern is repeated and a part where a pattern with no regularity is arranged depending on the circuit pattern.

The thickness of the first wiring pattern 52 is, for example,
The thickness of the second wiring pattern 54 is, for example, about 4000 to 12000 °, and the thickness of the first interlayer film 51 is, for example, 150
The thickness is about 0-10000 °, and the thickness of the second interlayer film 53 is generally, for example, about 3000-15000 °.

By adopting such a multilayer wiring structure, when designing a circuit pattern, the degree of freedom in pattern layout is increased, and it is expected that this will greatly contribute to speeding up and high integration of LSI. At the same time, the design man-hours will be greatly reduced due to the increase in the degree of freedom. However, such a conventional multilayer wiring structure also has a technical problem described below.

[0009]

That is, in the multilayer wiring structure shown in FIG.
When the second interlayer film 53 is formed thereon, a surface step 53a is generated diagonally above the corner of the first wiring pattern 52. Then, when the second wiring pattern 54 is formed on the second interlayer film 53 in a state where the surface step 53a is generated,
At a portion corresponding to the surface step 53a, a surface step 54a having a larger step is formed.

The occurrence of such a step is caused by the wiring pattern 5
2, 54 are usually formed by a sputtering method or a CVD method, and the thin film formed by such a method is greatly affected by the shape of the base.
In part a, the film thickness is about 40
About 70%.

In particular, as shown in FIG. 5, in a portion where the distance between the first wiring patterns 52 is relatively large, two surface steps 53b are connected diagonally above the corners of the pattern 52, and this occurs. The second wiring pattern 54 formed on the upper portion becomes a considerably deep groove-shaped surface step 54b. At this surface step 54b, the film thickness is further reduced to about 2
This is about 0 to 60%, and such a decrease in the film thickness is further enlarged as the number of layers of the wiring structure increases.

As described above, when the film thickness of the wiring pattern is reduced, the electrical resistance increases at that portion, and this increase is relatively affected, for example, in an LSI in which the minimum dimension of the wiring pattern is about 0.8 μm. Is small, but the integration degree is increased, for example, the minimum dimension of the wiring pattern is 0.5 to 0.6.
For an LSI of about μm or less, a very serious problem occurs.

That is, when the electric resistance of the wiring pattern increases, the transmission speed of the electric signal decreases. In particular, since the wiring pattern having a fine size is usually used as a signal wiring, the local resistance increases. If there are multiple places,
Even if the delay at one location is small, if the delay occurs at multiple locations, it cannot be ignored.

To cope with such a problem of the surface step, for example, in Japanese Patent Laid-Open No. 2-128449, a dummy pattern having a thickness approximately equal to the wiring film thickness is provided in a region where no wiring is formed. A technique for flattening the upper layer side pattern has been proposed, but this solution is limited in the width between the wiring located on both sides of the dummy pattern and the width of the dummy pattern itself, and can be actually applied. Location is greatly restricted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to reduce the number of applicable parts and to reliably eliminate an increase in electric resistance. It is to provide a pattern structure in an apparatus.

[0016]

In order to achieve the above-mentioned object, according to the present invention, there are provided a plurality of parallel-arranged, different intervals.
The wiring width of the upper wiring crossing over the lower wiring is
In the inter-wiring area where the distance between lines is large, the distance between lower layer wirings is narrow.
It is formed wider than the area between the wirings.

[0017]

[0018]

[0019]

According to the present invention, the film thickness is significantly reduced locally.
Over the area where the distance between the lower wiring
Since the widened part is provided, the cross-sectional area of the upper layer wiring increases,
The increase in the resistance of the upper wiring can be reduced.

[0020]

[0021]

[0022]

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 1 and 2 show one embodiment of a wiring pattern structure in a semiconductor device according to the present invention. The semiconductor device shown in FIG. 1 has a first interlayer film 1 mainly composed of, for example, an SiO ₂ film as a base.
There are formed, on the upper, for example, a metal or polycrystalline silicon is deposited in a film form by a CVD method or the like, by an etching process, is provided first wiring pattern 2 ₁ to 2 ₃ formed in a predetermined shape Have been.

Further, I in the above the first interlayer film 1 and the first wiring pattern 2 ₁ to 2 _3, was Wataru on the entire surface, for example, S
A second interlayer film 3 mainly composed of an iO ₂ film is formed. Then, on the second interlayer film 3, in the same manner as the first wiring pattern 2, for example, a thin film-shaped second wiring pattern 4 mainly containing a metal such as aluminum is used.
_1, 4 ₂ are formed.

[0025] In this embodiment, the first wiring patterns 2 ₁ -
2 _3, a pair of pattern located on the left side in FIG. 2 _1, 2 ₂
Are formed in parallel at relatively small intervals, and the remaining pattern 2
₃ orthogonal, formed in parallel at a relatively large distance between the pattern 2 _2, a first wiring pattern 2 ₁ to 2 ₃ second wiring patterns 4 _1, 4 ₂ and is, across the second interlayer film 3 The basic part of the wiring structure is
This is the same as the conventional one shown in FIG.

In the multilayer wiring structure having such a positional relationship, the second wiring patterns 4 ₁ ,
4 _2, corresponding to the plan view, pattern intersect portion, such as (between pattern 2 ₂ and the pattern 2 ₃₎ the first wiring patterns 2 ₁ to 2 ₃ intervals is relatively large portion, above As described above, a portion where the film thickness is locally reduced occurs.

Therefore, in the embodiment shown in FIG.
The thickness of the second wiring pattern 4 ₁ so as to correspond to the locally thinner portion, widened portion 5a on both sides of the pattern 4 _1, to form a 5b. When such widened portions 5a and 5b are formed, the cross-sectional area of the second wiring pattern 41 is partially increased at these portions, and the electric resistance is reduced, and the increase in the electric resistance due to the surface step can be reduced. . Widening portion 5a,
The width and length of 5b are set to various sizes depending on the degree of the surface step that varies depending on, for example, the thickness of the first wiring pattern 2, the thickness of the second interlayer film 3, and the like.

The embodiment shown in FIG. 1 (b), the first wiring pattern 2 _2, 2 is relatively large spacing between _3, the surface level difference corresponding to the portion becomes deep groove, the electrical resistance since an increase that is more pronounced than the increase in other portions is predicted, the second wiring patterns 4 ₁ enlarged portion 5b on both sides only position corresponding to the portion ', 5b' provided to other portions forms a widened part 5a 'on only one side of the pattern 4 _1.

[0029] In the embodiment shown in FIG. 1 (c), are formed in parallel with the second wiring patterns 4 _1, 4 ₂ are close two orthogonally to the upper portion of the first wiring pattern 2 ₁ to 2 ₃ and which, widened portion 5 to each of the second wiring patterns 4 _1, 4 ₂ does not face portion
a '' and 5b '' are formed. In this case, the width and length of the wide section 5b '' is the second wiring patterns 4 _1, 4 ₂
It can be determined according to the interval between them.

[0030] Figure 2 shows another embodiment of the present invention, in this example, also forms the widened portion 6a and the deformed portion 6b to the first wiring pattern 2 ₁ to 2 _3, the first wiring pattern 2
By equalizing the distance between ₂₁ to _3, shows that reducing the degradation of the second wiring patterns 4 _1, 4 ₂ thick formed thereon.

[0031] In the embodiment shown in FIG. 2 (a), to form a widened portion 6a of the distance between the first wiring pattern 2 _2, 2 ₃ protrudes from both sides in a relatively large part. In this embodiment, although not shown in close proximity the other pattern is effective when the second wiring patterns 4 _1, 4 ₂ widened portion can not be formed on the second wiring patterns 4 _1, 4 ₂ .

[0032] In the embodiment shown in FIG. 2 (b), the first wiring pattern 2 _2, 2 ₃ interval is relatively large portion of, forming a deformation 6b of substantially the same width on one of the pattern 2 _3, deformable portion the by causing close to 6b in the other pattern 2 ₂ 1
To equalize the spacing between the wiring patterns 2 ₁ to 2 _3, to prevent this by lowering the thickness generated in the second wiring pattern 4 _1, 4 _2.

FIG. 3 shows yet another embodiment.
In this embodiment, as in the case shown in FIG. 2 (a), the second wiring pattern 4 _1, 4 ₂ and close the other pattern, the second wiring patterns _41, 42 widening portion ₂ is a example is effective if it can not form, the first wiring pattern 2 ₁
To form a trapezoidal shape widening 6c projecting outwardly, in the portion between the interval first wiring pattern 2 ₂ is relatively _large, 2 ₃ of the wiring pattern, close to the pattern 2 ₂ side to the pattern 2 ₃ A deformed portion 6d is formed.
And the portion where the original pattern 2 ₃ is connected, when adopting the pattern shape shown in FIG. 3 forming the second wiring patterns 4 _1, 4 ₂ and oblique widening portion 6e in plan view , the second wiring patterns 4 _1, 4 ₂ without providing a deformation such as widening portion, can be significantly reduced, reducing the thickness due to the surface step. Incidentally, not shown detailed drawing, the widened portion and the deformed portion of the above-described embodiment the first and second wiring patterns 2 ₁ -
When 2 _3, 4 _1, 4 ₂ in combination as appropriate, even if there is restriction on layout wiring pattern, since freedom in combination is extremely large, the effect of the present invention can be effectively exhibited.

FIG. 4 shows still another embodiment of the present invention. While each of the above embodiments were intended to provide a widened portion or deformation unit to either the first or the second wiring patterns 2 ₁ to 2 _3, 4 _1, 4 _2, in this embodiment, the wiring pattern This eliminates a decrease in the thickness of the pattern due to the surface step without changing the thickness of the pattern.

FIG. 4A is a top view of the wiring pattern of this embodiment, and FIG. 4B is a sectional view thereof. In this embodiment, the first wiring pattern 2 ₁ to 2 ₃ of the lower layer is formed in the usual way, the second interlayer film 3 is formed thereon. Next, a thin film having a thickness of, for example, about 1500 to 10000 degrees is formed by a sputtering method using a metal such as aluminum as a main component as a second wiring pattern, and a polycrystalline silicon film, tungsten, or the like is further formed thereon.
Titanium, molybdenum and other low-melting metal films with low resistance
For example, a thickness of about 1500-15000 mm is formed by the CVD method, and thereafter, an anisotropic etching process is performed on the entire surface, and an etch-back process is performed.

[0036] By the above processing, the second wiring pattern 4 _1, 4 ₂ which are formed, in the portion where the surface level difference occurs, sidewall-shaped or groove-shaped in the polycrystalline silicon film and a refractory metal film low The resistive substances 7a and 7b are left, and the low resistive substances 7a and 7b compensate for a decrease in the thickness of the pattern due to the surface step, thereby preventing an increase in electric resistance.

In the embodiment shown in FIG. 4, since the pattern is not changed, there is no restriction on the layout of the circuit pattern. In particular, in the case of a semiconductor device in which higher integration is more strictly required, the embodiment shown in FIG. The effect can be expected.

[0038]

According to the present invention, the film thickness locally decreases.
The upper layer on the area where the distance between the lower wiring lines becomes large
Since the widened part is provided in the wiring, the cross-sectional area of the upper wiring is large.
Therefore, an increase in the resistance of the upper wiring can be reduced.

[0039]

[0040]

[Brief description of the drawings]

FIG. 1 is a plan view showing one embodiment of a pattern structure in a semiconductor device according to the present invention.

FIG. 2 is a plan view showing another embodiment of the pattern structure.

FIG. 3 is a plan view showing another embodiment of the pattern structure.

FIG. 4 is a plan view and a cross-sectional view showing still another embodiment of the pattern structure.

FIG. 5 is a plan view and a cross-sectional view illustrating an example of a pattern structure in a conventional semiconductor device.

[Explanation of symbols]

1 first interlayer film 2 ₁ to 2 ₃ the first wiring pattern 3 and the second interlayer film 4 _1, 4 ₂ second wiring patterns 5a, 5a ', 5a''wide section 5b, 5b', 5b '' widened portion 6a, 6c, 6e Wide part 6b, 6d Deformed part 7a, 7b Low resistance material

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57) [Claims] A first direction extending in a first direction and arranged in parallel with each other;
The first to third lower wirings to be formed, and the first to third lower wirings
An insulating film formed on the layer wiring; and an insulating film disposed on the insulating film.
In the first direction above the first to third lower wiring layers.
And a first upper wiring extending in a second direction orthogonal to
In the obtained semiconductor device, the distance between the first lower layer wiring and the second lower layer wiring is
The distance is larger than the distance between the second lower wiring and the third lower wiring.
The upper part of the inter-wiring region between the first and second lower wirings.
The width of the first upper wiring is different from the width of the second and third lower wirings.
Wider than the width of the first upper wiring above the inter-wiring region between
A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1 , wherein said first upper wiring is formed on said insulating film.
A second upper layer wiring arranged in a row, wherein the first and second upper wirings are provided.
The second upper layer wiring above an inter-wiring area between the lower wiring and the lower wiring.
The width of the line is an inter-wiring area between the second and third lower wirings.
Being wider than the width of the second upper wiring above.
The semiconductor device according to claim 1.