JP3180966B2 - Digital hysteresis circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital hysteresis circuit which is used in a digital control temperature compensating circuit, a digital measuring circuit, etc., and which digitally generates hysteresis in order to eliminate flickering of a measured value due to a digital error.

[0002]

2. Description of the Related Art Recently, in various electronic devices, measured values are digitized and displayed, and devices are often controlled based on the digitized measured values.

For example, a digitally controlled temperature-compensated crystal oscillator whose oscillation frequency does not change in response to changes in environmental temperature is used as a reference oscillator used in communication equipment and the like.

As an example of a temperature compensation circuit used in this digitally controlled temperature-compensated crystal oscillator, an astable multivibrator whose oscillation frequency is sensitive to a temperature change is used as a gate pulse generator, and an astable multi-vibrator whose oscillation frequency does not change due to a temperature change. Using a multivibrator as a reference pulse generator
In some cases, the number of pulses corresponding to the temperature is counted from the pulse of the reference pulse generator by the gate of the gate pulse, and the count is used as temperature data. Based on the temperature data, compensation data corresponding to each temperature previously stored in the PROM is called, converted into an analog output through a D / A converter, and applied to a varicap diode of an oscillation circuit. Thereby, the oscillation frequency is controlled to be constant.

In this temperature compensation circuit, for example, there is a problem that the number of pulses used as temperature data fluctuates even if the environmental temperature does not actually fluctuate greatly. The cause is that when the reference pulse, which is the counted pulse, is cut off at the rise of the gate stop signal and counted, the rise of the gate stop signal changes from the HIGH state to the LOW state or from the LOW state to the HIGH state of the reference pulse. This is because if it is close to the above, a digital error will occur and one pulse will not be counted or not.

The present invention has been devised to solve the above-described problems, and has as its object to be used in a digital control temperature compensation circuit or a digital measurement circuit, and to measure a measurement value due to a digital error as described above. An object of the present invention is to provide a digital hysteresis circuit for digitally generating hysteresis in order to eliminate flicker.

[0007]

According to the present invention, a pulse to be counted (for example, a reference pulse in the figure) and a gate pulse having a gate period longer than the period of the pulse to be counted (for example, a temperature pulse in the figure) are provided. ) In each cycle of the gate pulse, and outputs a count stop signal for determining the number of pulses to be counted in each gate period, wherein (1) a predetermined gate period When the counted pulse is HIGH at the end of the period, the count stop signal is set at the time when the counted pulse goes to the next LOW state, and (2) the counted pulse is set to the LOW state at the end of the predetermined gate period. In this case, the number of pulses to be counted is compared with the even / odd number of pulses to be counted in the previous gate period, and if the numbers match, the count is synchronized with the end of the predetermined gate period. The door stop signal, if no match is odd, a count stop signal at the falling edge of the next object to be counted pulses, there is provided a digital hysteresis circuit, characterized in that each output.

[0008]

The operation of the present invention will be described below.

By using the digital hysteresis circuit of the present invention for a digitally controlled temperature-compensated oscillator or a digital measuring circuit, even if a phenomenon occurs in which the period of the fluctuation signal indicating the temperature data or the measured data fluctuates in a very small range, the counting is performed by this. The pulse count pulse number should not be directly changed.

That is, when a predetermined gate period for counting the counted pulses ends in the middle of the HIGH state of the counted pulses, the number of counted pulses up to the HIGH state is counted, and the time of the end of the gate period is counted. A count stop signal is generated so that even if the position slightly changes, the count pulse number does not change.

On the other hand, when the predetermined gate period ends in the middle of the LOW state of the counted pulse, if the count pulse number of the previous counted pulse coincides with the even number of the current counted pulse, there is no influence of the fluctuation. Judgment is made, the number of pulses to be counted up to immediately before is counted, and if they do not match, it is judged that there is an influence of fluctuation, and a count stop signal is not generated until another pulse is counted. As a result, it is possible to prevent the frequency of the oscillator from fluctuating and the display of the measured value from flickering.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. In the following embodiments, the case where the counted pulse is a reference pulse and the gate pulse is a fluctuating pulse will be described, and the opposite case will be omitted. However, it is needless to say that the present invention can be similarly implemented in the opposite case.

FIG. 1 is an example of a block diagram of a digital temperature compensated crystal oscillator using a digital hysteresis circuit of the present invention. In the figure, 1 is a reference pulse generator, 2 is a temperature pulse generator whose frequency varies depending on the ambient temperature, 3 is a digital hysteresis circuit, 4 is a timing pulse generator,
5 is a PROM circuit as a memory unit, 6 is an up / down counter, 7 is a latch circuit, and 8 is a voltage controlled crystal oscillator. Actually, the operation is stabilized by further using a constant voltage regulator, but is omitted here. The operation principle of this oscillator will be briefly described below.

The reference pulse ts generated by the reference pulse generator 1 and the temperature pulse TT generated by the temperature pulse generator 2
(A signal for setting a gate period) is input to the digital hysteresis circuit 3 at the same time. The digital hysteresis circuit 3 outputs a count stop signal OS for setting a counting period in which the reference pulse has been subjected to hysteresis processing. The timing pulse generator 4 corresponds to the ambient temperature from the reference pulse ts of the reference pulse generator 1. Select a number of pulses. The count stop signal OS is output at such a timing that minute fluctuations in the number of pulses to be selected are eliminated.

The PROM circuit 5 previously stores temperature compensation data (+1,-) in a differential memory system.
The data is multiplied by the pulse number corresponding to the temperature data, and the result is counted by the up / down counter 6. Next, the count value is converted into an analog voltage by the latch circuit 7, and the voltage is applied to the variable capacitance diode of the voltage-controlled crystal oscillator 8 to correct the oscillation frequency.

FIG. 2 is an example of a circuit diagram of a hysteresis circuit according to the present invention.

This hysteresis circuit includes three flip-flop (FF) circuits Q21 to Q23, EX-O
An R gate Q24, a NOR gate 25, and four NOT gates Q26 to Q29 are connected.

A reference pulse ts and a temperature pulse TT whose frequency varies depending on the temperature, for example, are input to this circuit and a count stop signal OS is output. The count stop signal OS is a count stop signal for setting a counting period including the hysteresis process. By outputting this signal, the number of pulses corresponding to the state of the temperature pulse TT of the temperature pulse generator 2 can be extracted. it can. That is, a gate period is generated in synchronization with the reference pulse ts and the temperature pulse TT, and a predetermined gate period based on the temperature pulse TT is set. A count stop signal OS for adjusting the number of pulses for actually counting the reference pulse ts is generated according to the pulse state of the reference pulse ts at the end of the gate period. Further, according to the pulse state of the reference pulse ts at the end of the gate period, the temperature pulse TT
The count stop signal OS is generated so as to directly derive the number of pulses counted in the gate period one cycle before.

First, the FF circuit Q21, the FF circuit Q22,
The FF circuit Q23 is generally called a data flip-flop circuit. In this example, the data flip-flop has a function of outputting the content of the data applied to the data terminal D of the FF circuit to the output terminals Q and Q 'when the input pulse rises. These circuits Q
21 to Q23, CP is a clock pulse input terminal, D is a data terminal, Q and Q 'are output and inverted output terminals,
RST is a reset terminal, and PR is a preset terminal.

Here, the output Q 'outputs a signal having a phase opposite to that of the output Q. When a signal in a HIGH (hereinafter, simply referred to as H) state is applied to the RST terminal, the output Q becomes zero (LOW (hereinafter, simply referred to as L) state) regardless of the clock pulse signal CP. On the other hand, when a signal in the H state is applied to the PR terminal, the output Q goes to the H state regardless of the clock pulse signal CP.

The FF circuit Q21 functions as a trigger flip-flop by connecting the Q 'terminal to the D terminal. The trigger flip-flop has a function of inverting the output state each time a rising edge of a pulse input to the circuit is detected. Therefore,
This FF circuit Q21 has a frequency dividing function, and outputs Q and Q 'have a frequency of 1/2 with respect to the input. Therefore, in this example, if the count number of the input pulse is even, the output is in the L state, and if the count number is odd, the output is in the H state, so that even / odd determination of the input pulse can be performed. The hysteresis circuit of the present invention counts and determines whether the number of reference pulses ts until the count stop signal OS rises is even or odd.

The FF circuit Q22 is a memory for storing the output of the FF circuit Q21 immediately before the count stop signal OS rises. The principle of this memory is as follows. That is, at the same time when the count stop signal OS rises,
The clock pulse CP of the FF circuit Q22 changes from the L state to the H state, and the output from the output terminal Q of the FF circuit Q21 is
In response to the data D of the F circuit Q22, the output of the original output terminal Q of the FF circuit Q21 is stored in the output terminal Q of the FF circuit Q22 (until the next time the count stop signal OS rises). Thereafter, a reset signal is applied to the FF circuit Q21 to clear the contents. NOT gate Q28, NO
The T gate Q29 is provided to delay the count stop signal OS signal from entering the RST terminal of the FF circuit Q21 so that the contents of the FF circuit Q21 are erased after being transferred to the FF circuit Q22. I have.

The EX-OR gate Q24 is connected to the FF circuit Q2
1 and the two input signals of the FF circuit Q22 match, the L-state signal is output, and if not, the H-state signal is output.

The NOR gate Q25 outputs an H state when all inputs are in an L state, and outputs an L state otherwise. Here, the reference pulse ts and the EX-OR gate Q2
When the signal 4 is in the L state, the output of the NOR gate Q25 becomes the H state at the moment when the temperature pulse TT pulse rises.

The FF circuit Q23 is a circuit that determines at which timing the count stop signal OS is issued after the rise of the temperature pulse TT. When the output of the NOR gate Q25 is in the L state, the FF circuit Q2 is turned on at the fall of the first reference pulse ts after the rise of the temperature pulse TT.
The output No. 3 (count stop signal OS) rises. NO
When the output of the R gate Q25 is in the H state, the FF circuit Q
When the PR terminal 23 goes high and the temperature pulse TT rises, the output (count stop signal OS) of the FF circuit Q23 rises immediately.

The signals passed through the NOT gates Q26 to Q29 are inverted in phase.

Next, the operation of the entire hysteresis circuit will be described with reference to some initial states.

When the reference pulse ts is in the H state and the temperature pulse TT rises from the L state to the H state, that is, when the predetermined gate period is completed.
The signal inverted from the H state to the L state by the OT gate Q27 is applied to the RST terminal to be in an operation state. At this time N
In the OR gate Q25, the input from the reference pulse ts is H
Because of the state, the L state is also applied to the PR terminal regardless of the state of the FF circuits Q21 and Q22. However, at this time, there is no output from the output terminal Q because the clock pulse CP is in the L state. Thereafter, when the reference pulse ts changes to the L state, the clock pulse CP changes to the H state, and the voltage applied to the D terminal is output to the output terminal Q. Therefore, the count stop signal OS rises from the L state to the H state. .

That is, in this case, the temperature pulse TT
Rises, the count stop signal OS does not rise immediately, but rises only when the reference pulse ts goes to the L state. This does not depend on the states of the FF circuits Q21 and Q22. This state is shown in the timing chart of FIG.

That is, the reference pulse ts changes from the H state to the L state.
When the temperature pulse TT rises from the L state to the H state before and after the state, if the temperature pulse TT itself is used as a count stop signal, a phenomenon that one pulse is counted or not occurs. Next, when the reference pulse ts is in the L state, the count stop signal O
Since S rises, the number of pulses until the reference pulse ts reaches H is counted.

When the reference pulse ts is in the L state, the FF circuit Q2
1 is in the L state, the FF circuit Q22 is in the L state, and the temperature pulse T
When T rises from the L state to the H state, that is, when the predetermined gate period ends, first, in the FF circuit Q23, from the temperature pulse TT to the L state from the H state by the NOT gate Q27.
The signal inverted to the state is applied to the RST terminal, and the operation state is set. At this point, since the FF circuits Q21 and Q22 are both in the L state, the EX-OR gate Q24 is in the L state and NO
Since all three inputs of the R gate Q25 are in the L state,
The H state is applied to the PR terminal, and the PR terminal enters a preset state. Therefore, the H state is output from the output terminal Q of the FF circuit Q23, and the count stop signal OS rises from the L state to the H state.

That is, in this case, the count stop signal OS rises at the same time as the rise of the temperature pulse TT.
This state is shown in the timing chart of FIG.

When the reference pulse ts is in the L state, the FF circuit Q21
Is in the H state, the FF circuit Q22 is in the H state, and the temperature pulse TT
Also rises from the L state to the H state, that is, when the predetermined gate period ends, the detailed description is omitted, but the timing of the rise of the count stop signal OS is the same as in this case. This state is shown in the timing chart of FIG.

As described above, in the case where the reference pulse ts is in the L state and the temperature pulse TT rises from the L state to the H state, the previous count stop signal OS indicates whether the pulse number of the reference pulse ts during the L state period is the same as that of the current pulse. If the pulse number of the reference pulse ts coincides with the pulse number, it is determined that there is no influence of the flicker of the temperature pulse TT, the count stop signal OS rises immediately, and the pulse number up to this point is counted. .

When the reference pulse ts is in the L state, the FF circuit Q2
1 is in the H state, the FF circuit Q22 is in the L state, and the temperature pulse T
When T rises from the L state to the H state, that is, when the predetermined gate period ends, first, in the FF circuit Q23, the temperature pulse TT changes from N to N.
When the signal inverted from the H state to the L state by the OT gate Q27 is applied to the RST terminal, the operation state is set. At this time, the FF circuit Q21 is in the H state and the FF circuit Q2
Since 2 is in the L state, the EX-OR gate Q24 is in the H state and one input to the NOR gate Q25 is in the H state, so that the L state is applied to the PR terminal. Therefore, in this state, the preset does not work, and no signal is output from the output terminal Q of the FF circuit Q23. From this state, when the reference pulse ts goes high next time, the output of the output terminal Q goes low because the clock pulse CP of the FF circuit Q23 is low.
It remains in a state.

The output from the output terminal Q of the FF circuit Q23 occurs when the output of the CP terminal of the FF circuit Q23 goes low next and the high state is applied to the CP terminal.

Since either the reference pulse ts or the EX-OR gate Q24 is always in the H state, the output of the NOR gate Q25 is always in the L state, so that the FF circuit Q23 is not preset and the FF circuit Q21 is not set. Does not adversely affect the above operation.

That is, in this case, the temperature pulse TT
Rises, the count stop signal OS does not rise immediately, but rises only when the reference pulse ts goes to the next L state. This state is shown in the timing chart of FIG.

When the reference pulse ts is in the L state, the FF circuit Q21
Is in the H state, the FF circuit Q22 is in the L state, and the temperature pulse TT
When the signal rises from the L state to the H state, detailed description is omitted, but the timing of the rise of the count stop signal OS is the same as in this case. This state is shown in FIG.
This is shown in the timing chart of FIG.

As described above, when the reference pulse ts is in the L state and the temperature pulse TT rises from the L state to the H state, the previous count stop signal OS indicates whether the pulse count of the reference pulse ts during the L state period is equal to the number of pulses of the reference pulse ts during the L state. If the pulse number of the reference pulse ts does not coincide with the evenness of the pulse number, it is determined that the influence of the temperature pulse TT flickers, and the count stop signal OS rises when the reference pulse ts goes to the next L state. Will be counted.

In the circuit of FIG. 2, the cycle of the temperature pulse TT needs to be relatively longer than the cycle of the reference pulse ts, but the temperature pulse TT is used as a reference pulse and the reference pulse ts is used to change the temperature. As described above, a pulse whose cycle changes according to the above can also function.

Further, in the circuit shown in FIG.
By connecting an inverter to a terminal to which s and TT are input, in the above description, the L state changes to the H state and the H state changes to the H state.
It is also possible to operate as the L state.

[0043]

As described above, according to the present invention, the rising timing of the pulse count stop signal is changed depending on the combination of the phase state of the reference pulse signal and the phase change of the pulse signal whose period fluctuates due to a change in temperature. A digital hysteresis circuit is obtained. By using this circuit, the pulse count can be prevented from flickering.

[0044]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital temperature-compensated crystal oscillator using a digital hysteresis circuit of the present invention.

FIG. 2 is a circuit diagram showing a digital hysteresis circuit according to the present invention.

FIG. 3 shows a count stop signal O when the temperature pulse TT rises from the L state to the H state when the reference pulse ts is in the H state.
6 is a timing chart showing a rise of an S signal.

FIG. 4 shows a count stop signal O when the temperature pulse TT rises from the L state to the H state when the reference pulse ts is in the L state.
FIG. 7A is a timing chart showing a rise of an S signal, FIG. 7A shows a state when the FF circuits Q21 and Q22 are in an L state, and FIG.
This shows when the circuit Q22 is in the H state.

FIG. 5 shows a count stop signal O when the temperature pulse TT rises from the L state to the H state when the reference pulse ts is in the L state.
FIG. 7A is a timing chart showing the rise of the S signal, and FIG. 7A shows the FF circuit Q21 in the H state and the FF circuit Q22;
Shows the state of the L state, and (b) shows the state of the FF circuit Q2.
1 indicates the L state and the FF circuit Q22 is in the H state.

[Explanation of symbols]

 1 ··· Reference pulse generator 2 ··· Temperature pulse generator 3 ··· Digital hysteresis circuit 4 ··· Timing pulse generator Q21 to Q23 ··· Flip-flop circuit Q24 ··· EX -OR circuit 25... NOR circuit Q26 to Q29... NOT gate

Claims (3)

(57) [Claims] The present invention compares a counted pulse with a gate pulse having a gate period longer than the period of the counted pulse for each period of the gate pulse, and determines the number of pulses of the counted pulse in each gate period. A digital hysteresis circuit for outputting a count stop signal for determining
At the end of the predetermined gate period, the counted pulse becomes HIG.
In the case of the H state, the count stop signal is output at the time when the counted pulse goes to the next LOW state. (2) When the counted pulse is in the LOW state when the predetermined gate period ends, the counted pulse is output. Is compared with the pulse count of the pulse to be counted in the previous gate period, and if the pulse counts match, the count stop signal is synchronized with the end of the predetermined gate period, If not, a digital hysteresis circuit outputs a count stop signal at the falling edge of the next counted pulse. 2. A pulse according to claim 1, wherein the counted pulse is a reference pulse whose cycle does not relatively fluctuate, and the gate pulse is a fluctuating pulse whose cycle relatively fluctuates.
Digital hysteresis circuit as described. 3. The pulse to be counted is a fluctuating pulse whose cycle relatively fluctuates, and the gate pulse is a reference pulse whose cycle does not fluctuate relatively.
Digital hysteresis circuit as described.