JP3189282B2 - Memory predictive access device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access method of a memory mechanism generally used in information processing equipment and the like, and more particularly, to a method of correlating specified addresses between consecutive requests for a memory accessed by specifying an address at random. The present invention relates to a memory prediction access device for improving the efficiency of memory access by predicting an address specified by a backward request using a relationship.

[0002]

2. Description of the Related Art Conventionally, in a memory access method in which an address is specified at random and accessed, at the time of reading a memory, a request source sends an address and other necessary request information to the memory to send the address from the memory. The reading was performed, the read data was determined, and these were returned to the request source. The request source was able to start the next memory access only after the data was returned to the request source.

FIG. 6 is a block diagram of a conventional example, and shows a device in which a request source 300 accesses a memory 330.

[0004] When the request source 300 writes, the line 302
The request address is sent from the line 303 as "1" as a write designation value, and the write data is sent out from the line 304. Also, the request source 300 reads the line 302
Then, the request address is transmitted as “0” as a write designation value from the line 303, and the read data is received from the line 351.

[0005] The write designation flag 320 is formed of a 1-bit register, receives a write designation value from the line 303, and relays it to the line 321. Write data register 325 receives write data from line 304 and relays it to line 326.

The memory unit 310 includes a memory 330, an address register 345, and a read data register 350. In the memory 330, an address is designated by a line 346, and read / write is designated by a line 321. At the time of reading, data is read from the designated address and output as read data to a line 331. At the time of writing, the write data received from the line 326 is designated. Write to the specified address. The address register 345 receives and holds the request address from the line 302, and specifies the address to the memory 330 via the line 346. Read data register 350
Receives read data from the line 331 and relays it to the line 351. The registers 320, 325, 345, 3
Numeral 50 operates in synchronization with a single-phase clock that specifies each timing.

Next, the operation of the conventional example shown in FIG. 6 will be described. Now, for example, as shown in FIG. 7, the request source 300 performs a read access to the address A, a read access to the address A + 1, a read access to the address A + 2, a write access to the address B, a write access to the address A + 4, It is assumed that read accesses to the address C are sequentially performed. At this time, the address, read / write, and access order of the access to be executed are as shown in FIG.

When this series of accesses is executed, each unit in FIG. 6 operates as shown in the timing chart of FIG. That is, at the timing t0, the request source 3
From 00, the address A is sent to the line 302, the write designation value "0" is sent to the line 303, and at the timing t1, "0" is held in the write designation flag 320 and the address A is held in the address register 345. At t2, the read data (A) is held in the read data register 350, and the read data (A) is taken into the request source 300 via the line 351. At the subsequent timing t3, the request source 300 sets the address A + 1 on the line 302 and “0” as the write designation value on the line 303.
Is sent. At the timing t4, "0" is held in the write designation flag 320, the address A + 1 is held in the address register 345, and at the timing t5, the read data (A + 1) is held in the read data register 350, and the held read is held. The data (A + 1) is taken into the request source 300. At the timing t7, the address A + 2 is sent from the request source 300 to the line 302, and “0” is sent to the line 303 as the write designation value. At the timing t8, the write designation flag 320 is set to “0”.
However, the address A + 2 is held in the address register 345, and at the timing t9, the read data register 3
The data (A + 2) is held in 50, and the held read data (A + 2) is taken into the request source 300.

At timing t10, the request source 300 sends the address B to the line 302, "1" as the write designation value to the line 303, and the write data W (B) to the line 304.
Is transmitted, and the write designation flag 320 holds “1”, the address register 345 holds the address B, and the write data register 325 holds the write data W (B). At timing t11, the write data W (B) is written to the address B of the memory 330, and
Address A + 4 from the request source 300 to the line 302,
“1” is sent as a write designation value to line 303, write data W (A + 4) is sent to line 304, “1” is written to write designation flag 320, address A + 4 is written to address register 345, and write data is written to write data register 325. W (A + 4) is held. At timing t12, the write data W to the address A + 4 of the memory 330 is written.
The writing of (A + 4) is performed, and the address C is transmitted from the request source 300 to the line 302 and “0” is transmitted to the line 303 as a write designation value. Subsequent timing t
At 13, “0” is held in the write designation flag 320, the address C is held in the address register 345, the read data (C) is held in the read data register 350 at the next timing t 14, and the read source 300 Capture (C). Here, it should be noted that the request source 300 can immediately start the next access at the time of a write access, but cannot start the next access at the time of a read access until read data is returned. The above is the description of the operation of the conventional example.

[0010]

In the above-described conventional example, in order to realize a function of performing an access by designating an address at random, a memory address supplied from a request source for each access is relayed through an appropriate route. The method used for memory addressing is adopted. On the other hand, in actual memory access, an access of a format in which consecutive addresses are sequentially read by the spread of the cache memory system, various DMA transfers, various block transfers, and the like occurs at a very high frequency. The correlation that becomes the next address of the address is very strong, and in that sense it can be said that the next address can be predicted with high probability.
However, in the above-described conventional method, although the next address can be predicted with a very high probability, it is necessary to deal with any address specification, so that in any case, it is necessary to wait for the arrival of the request address. After that, memory access was started using the request address. Here, as shown in the conventional example, the request source usually sends out the request address, and the process of moving to the next request process is generally performed at the earliest after the read data is received. Considering this, there is a problem that the access operation of the memory is always discrete as shown in the timing chart of FIG. 9, and it is difficult to increase the access speed. In order to cope with such a problem, it has been conventionally practiced to simply configure the memory section with a high-speed memory element to forcibly increase the speed, or to adopt a cache memory system. However, these methods face new problems in that the hardware is very expensive, requires a large amount of additional mechanisms, and is very difficult to control.

An object of the present invention is to make it possible to increase the access speed with a simple and inexpensive hardware configuration.

[0012]

SUMMARY OF THE INVENTION The present invention achieves the above object and , in order to speed up block reading, in a memory device of a type in which a memory address is randomly specified and accessed, a Address holding means having a function of holding the memory address of the memory address separately in an upper part and a lower part, and a function of incrementing the lower part of the held memory address , and a memory address held in the address holding means. Read data holding means for holding the read contents of the memory, and an address held by the address holding means
Matches the lower part of the address from the requestor.
Hit report if it matches the result of stepping up the corresponding part
Outputs tell, and <br/> comparison means in case of discrepancy of outputting the miss reports, read access, the read data holding means to said request source when outputting the comparison means Gahi Tsu preparative Report Fetching the held data, further causing the read data holding means to fetch the data indicated by the memory address held by the address holding means, and then reading the lower order of the memory address held by the address holding means. incrementing portion, when outputting the comparison means Gami Suhitto report was incorporated memory address from the request source to said address holding means, further, the address holding means to the read data holding means holds The data indicated by the memory address is fetched, and then the memory address held by the address holding means is read. Control increments the lower part of the less
Control means. Further, the present invention has a configuration in which the control means causes the address from the request source to be taken into the address holding means at the time of write access, and writes to the memory in accordance with the address taken by the address holding means .

[0013]

[Action] during a read access, which is held in the case (address holding means that outputs the comparison means Gahi Tsu door report A
The dress corresponds to the lower part of the address from the request source
In the case where the result coincides with the result obtained by incrementing the portion to be read, the data held by the read data holding means is fetched to the request source, and the read data holding means indicates the memory address held by the address holding means. The data is fetched, and then the content of the address holding means is incremented. Therefore, in the next read access, if the next address of the previously accessed memory address is accessed, the read data to be accessed this time is already held in the read data holding means.
Access can be speeded up. Here, the address holding means places the memory address from the request source in a higher order.
A part is held separately from a lower part, and when incrementing, only the lower part is advanced. Therefore, if the increment is performed when the address at the end of a certain block is held in the address holding means, the address holding means indicates the head address of the certain block. The comparing means outputs a hit report if the address held in the address holding means matches the result of incrementing the lower part of the address from the request source, and outputs a hit report if the address does not match. Print a report. Therefore, also in the case of performing a read access to the head address of the certain block next to the end address of the certain block, the read data holding unit stores the certain block at the time when the access to the end address of the block is completed. Since the data at the first address of the data is held, the access can be speeded up as in the case of accessing consecutive addresses.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 illustrates the technology underlying the present invention.
FIG. 2 is a block diagram illustrating a configuration of a device in which a request source 100 accesses a memory 130.

When the memory access is started, the request source 100 outputs "1" as the access start designation value from the line 101. At the time of writing, the request address is further set to “1” from line 102 as a write designation value from line 103.
Is transmitted from the line 104 via the write data. At the time of reading, the request address is further transmitted from the line 102 and “0” is transmitted as the write designation value from the line 103. Thereafter, when a hit report is received from the line 161, the read data is received from the line 151. When the access is not to be started, “0” is transmitted as an access start designation value from the line 101, and “0” is transmitted as a write designation value from the line 102.

The write designation flag 120 is made up of a 1-bit register, receives the write designation value from the line 103, and relays it to the line 121. Write data register 125
Receives write data from line 104 and relays to line 126. The write designation flag 120 and the write data register 125 are registers for adjusting timing.

The memory unit 110 includes a memory 130, an address register 140, and a read data register 15.
0, a comparator 160, a write designation history flag 170, and an OR gate 180.

Memory 130 receives the address from line 146,
Write / read designation is received from the line 121, and at the time of reading, reading is performed from the designated address and the line 131 is read.
The write data is output to the designated address at the time of writing.

The address register 140 has a line 14 inside.
6 has an address register 145 for holding an address designated to the memory 130 through the address register 6. And
When the access start instruction is received from the line 101 (when the designated access start value becomes “1”), “1” is received as the write designated value from the line 103 or the line 16
If a mishit report is received from 1, the request address is taken into the address register 145 from the line 102, and if a hit report is received from the line 161, the address register 145 is incremented. Further, when the access start instruction is received from the line 101,
Has not received “1” as the write designation value from
Address register 1 due to a mishit report from
When the request address from the line 102 is taken into 45, "1" is output from the line 147 as an address re-storage report at that timing, and the address register 145 is incremented at the next timing.

The read data register 150 is strobed by a memory read instruction from a line 181,
1 is relayed to the line 151. Comparator 1
60 compares the memory address on line 146 with the memory address on line 102, with a positive result as the memory address on line 146 is the next memory address after the memory address on line 102. Is detected, a hit report value “1” is used as the hit information, and if a negative result is detected, the hit report value “0” is used as the hit information.
61. However, when "1" is not input as enable information from the line 171, a value "0", that is, a mishit report is always output as hit information. The write designation history flag 170 is composed of a 1-bit register.
It is strobed by a memory read instruction from a line 181 and receives a write designation from a line 121, and outputs a value whose polarity is inverted to a line 171. The OR gate 180 outputs a memory read instruction from the line 181 when either the address re-storage report from the line 147 or the access start designation from the line 101 is validated. Therefore, when the address held in the address register 145 is the next address after the address where the data held in the read data register 150 is stored, the output of the write designation history flag 170 is enabled. The registers 120, 125, 145, 150, and 170 operate in synchronization with a single-phase clock that specifies timing.

[0021] to explain the operation to the next. Here, for comparison with the above-described conventional example, an operation in the case where the request source 100 sequentially performs the access shown in FIG. 7 will be described. At this time, the address, read / write, and access order of the access to be executed are as shown in FIG. 8 as described above.

When this series of accesses is executed, each section in FIG. 1 performs the operation shown in the timing chart of FIG. Incidentally, in the timing chart of FIG. 2, at the start of the above-described series of access execution, "0" is held in the write designation flag 120 and the address re-store Shall not be
Address register 145, read data register 150
The write designation history flag 170 is a read from the address A-1 in the previous access, takes over the value at the time of completion of the read, and holds the data (A) and “0” read from the address A + 1 and the address A, respectively. It is assumed that

First, when the request source 100 is at the timing t
At 0, reading from address A is started, and "1", address A, and "0" are output to lines 101, 102, and 103, respectively, as access start designation values, request address values, and write designation values. In response, the comparator 160
Compares the address held by the address register 145 on the line 146 with the request address from the line 102. In this case, the addresses on lines 146 and 102 are A + 1 and A, respectively, and the address on line 146 is
Since the address is the address next to the address on the line 2 and the enable information output from the write designation history flag 170 also indicates “1”, the comparator 160 outputs a hit report to the line 161. By outputting the hit report to the line 161, the request source 100 detects that the data held in the read data register 150 is the data read from the address A of the memory 130.

At the time of transition from timing t0 to timing t1, the request source 100 is synchronized with the single-phase clock.
Takes in the desired read data (A) from the line 151, and the read data register 150 outputs the memory read instruction to the line 181.
The read data (A + 1) that has been read from the address A + 1 of the memory 130 is fetched, and the write designation history flag 170 indicates that the memory read instruction has been output on the line 181, and thus the line that previously designated the memory 130 for the read was read. The value “0” on the line 121 is fetched and the write designation flag 12
0 takes in the write designation value “0” on the line 103, and the address register unit 140 increments the content of the address register 145 to A + 2 since the hit report is output on the line 161.

At timing t1, the request source 100 starts reading from the address A + 1 as the next access, and sets the lines 101, 102 and 10 as the access start designated value, the request address and the write designated value.
3 outputs "1", address A + 1 and "0", respectively. Thereby, the comparator 1 similar to the timing t0
60, and the comparison result is request source 1
Reported on line 161 to 00. Request source 100
Detects whether the content held in the read data register 150 is the data read from the address A + 1 of the memory 130 based on the report from the line 161. To detect.

At the time of transition from timing t1 to timing t2, the request source 100 is synchronized with the single-phase clock.
Fetches the read data (A + 1) for the access started at the timing t1, and the read data register 150 outputs the address A + 2 of the memory 130 since the memory read instruction is output on the line 181.
The read data (A + 2) that has been read from the memory 1 is fetched, and the write designation history flag 170 changes to the memory 1
The value “0” on the line 121 for which the read has been designated for the line 30 is fetched, and the write designation flag 120 is set for the line 103.
The upper write designation value "0" is fetched, and the address register unit 140 increments the content of the address register 145 to A + 3 since the hit report is output on the line 161.

At the next timing t2, since no access is made, the request source 100 sends "0" as the access start designation value to the line 101 and "0" as the write designation value to the line 103.

At the time of transition from timing t2 to timing t3, the access start designation value is "0".
The contents of the address register 145 and the contents of the read data register 150 do not change.

At timing t3, the same operation as at timings t0 and t1 is performed.

At the time of change from timing t3 to timing t4, the same operation as at the time of change from timing t0 to timing t1 is performed.

At timing t4, writing to the address B is started, and the request source 100 sets the access start designated value, the request address value, the write designated value, and the write data value to "1" on the lines 101, 102, 103 and 104. , B, “1”, W (B).

At the time of transition from the timing t4 to the timing t5, the address register unit 140 sets the address register 145 because the write designation value from the line 103 is "1".
Fetches the address B from the line 102. At the same time, the write designation flag 120, the write data register 125, and the write designation history flag 170 indicate the write designation value “1” from the line 103, the write data W (B) from the line 104, and the The write designation value “0” held by the designation flag 120 is stored.

At the next timing t5, the request source 100 writes the address B of the memory 130 while the address A is the next access.
Start writing to +4. That is, the request source 100 receives the lines 101 and 102 as the access start designated value, the request address, the write designated value, and the write data.
"1", A + 4, "1", W (A +
4) is output.

At the time of the transition from the timing t5 to the timing t6, the write register value from the line 103 is "1".
5 causes address A + 4 from line 102 to be fetched. At the same time, the write designation flag 120, the write data register 125, and the write designation history flag 170 respectively contain the write designation value from the line 103, the write data W (A + 4) from the line 104, and the write designation flag 120 up to that point. Is stored as the designated write value "1". Also, certain data is taken into the read data register 150.

At the timing t6, the request source 100 starts reading from the address C, and similarly to the timings t0, t1, and t3, the lines 101, 102, and 103 serve as the access start designation value, the read address, and the write designation value. Output “1”, C and “0”, respectively.
Comparator 160 outputs a miss hit report on line 161 since no enable information has been added from line 171.
At this time, the request source 100 reads the data (data fetched at the time of transition from the timing t5 to the timing t6) held in the read data register 150 from the address C of the memory 130 due to the mishit report from the line 161. When it is detected that the data is not the read data, the read data is not taken in, and the request address value C and the write designation value “0” are output to the lines 102 and 103 until the hit report is returned from the line 161. State.

At the time of transition from the timing t6 to the timing t7, the address register section 140
, The request address value C from the line 102 is taken into the address register 145 in synchronization with the single-phase clock. Since the fetch of the request address value C is caused by the mishit report, the address register unit 140 outputs “1” as the address re-storage report from the line 147 at the timing t7, and outputs the address at the next timing t8. It operates to increment the register 145.

At the timing t7, the request source 100 does not return a hit report from the line 161, so that the waiting state is continued. That is, the request source 100 sends “0”, C, “0” to the lines 101, 102, and 103 as the access start designated value, the request address value, and the write designated value.
Is sent. At this time, the write designation history flag 170
Is "0", and the comparator 160 outputs a mishit report. Therefore, the request source 100 determines that the data stored in the read data register 150 is invalid and does not take in the data.

At the transition point from the timing t7 to the timing t8, the address register section 140 operates to increment the address register 145 as described above as a series of procedures inherited from the previous timing. Also,
Since the address re-storage report output from the address register unit 140 to the line 147 is “1”, the read data register 150 and the write designation history flag 170 are changed according to the memory read instruction output from the OR gate 180. The read data (C) from the address C that has been strobed and read on the line 131 and the write designation value “0” output on the line 121 are fetched.

At the next timing t8, the request source 100 sets the access start designation value, the request address, and the write designation value to the line 10 in the same manner as at the timing t7.
"0", C and "0" are output to 1, 102 and 103, respectively. This state is the same as the state at timings t0, t1, and t3, and the same operation is performed after the comparison by the comparator 160. Thereafter, when the request source 100 captures the contents held in the read data register 150 when the timing changes from the timing t8 to the timing t9, a series of accesses shown in FIG. 7 is completed.

[0040] Next Figure 1, of the present invention with reference to FIGS. 3 to 5
The real施例described. FIG. 3 is a block diagram showing a configuration example of an address register 145 used when implementing the present embodiment, and FIG. 4 is a comparator 16 used when implementing the present embodiment.
0 is a block diagram showing a configuration example of FIG. 5, and FIG. 5 is an operation explanatory diagram of the present embodiment.

This embodiment assumes block reading in a cache memory system or the like. In the cache memory system, if a mishit occurs during reading,
A block including a mishit address is read from the main storage device. Here, depending on the method, there is a method in which a block is read not from the head of the block but cyclically from a mishit address as shown in FIG. This is to return necessary data to the request side as soon as possible. In the present embodiment, such block reading can be performed at high speed.

As shown in FIG. 3, the address register 145 is divided into an upper part 145-1 and a lower part 145-2. In the upper part 145-1, a block address E of a block to be read is stored. -1
Stores the address in the block. Then, at the time of increment, only the lower part 145-2 is advanced. The bit number n of the lower part 145-2 is determined by the block size of the cache memory. When the contents of the lower part 145-2 are advanced when the contents are all "1" (at the end address of the block), the contents are made all "0" (the head address of the block). The same reference numerals as those in FIG. 1 indicate the same parts.

As shown in FIG. 4, the comparator 160 includes a stepper 900 for adding 1 to the lower n bits of the request address sent from the request source 100 to the line 102 and outputting the result to a line 991, and an address on a line 911. When the address matches the address on the line 146 that is the output of the address register 145, the match detector 910 sets the output signal to "1".
And an AND gate 920 that ANDs the output signal of the match detector 910 and the enable information output from the write designation history flag 170 to the line 171 and outputs hit information to the line 161. In addition, the stepper 900
When the lower n bits of the request address on the line 102 are all "1", the lower n bits are all "0".

When a mishit occurs at the time of reading the cache memory, the request source 100 first receives the line 101,
The access start designation value, the request address, and the write designation value of “1”, the missed address α and “0” are output to 102 and 103, and the reading of data from the missed address α is started.

In response to this, when the comparator 160 outputs a hit report to the line 161, the read data register 15
Since the data read from the address α is stored in 0, the request source 100 reads the read data (α) from the line 151. The read data register 150 fetches the data (α + 1) read from the address α + 1 of the memory 130 in the same manner as described above, and the address register 140 stores the address register 1
The content of the lower part 145-2 of 45 is incremented to α + 2. Thereafter, the request source 100 sets the access start designation value, the request address,
“1”, α + 1, and “0” are output as the write specification values, and the address α + 1 next to the mis-hit address is output.
Start reading data from.

When the comparator 160 outputs a mishit report, the request source 100 determines that the data stored in the read data register 150 is not the data read from the address α, and does not take in the data. , Until line 161 returns a hit report
In the state where “0” is output as the request address α and the write designation value to the line 02 and the line 103, a wait state is set. Further, since the address register unit 140 has received the mishit report from the comparator 160, the address register unit 140 loads the request address α on the line 102 into the address register 145.
Since the fetch of the request address α is caused by the mishit report, the address register unit 140 outputs “1” as the address re-storage report from the line 147 at that timing, and the lower order of the address register 145 at the next timing. Operate to increment portion 145-2. When "1" is output from the line 147 as the address re-storage report, a memory read instruction is output from the OR gate 180, whereby the read data register 150 reads the line 131 from the address α of the memory 130.
And the read data (α) that has been read out. Thereafter, the address register unit 140 increments the lower part 145-2 of the address register 145 as a series of procedures inherited from the previous timing, and increments the content by α +
Set to 1. As a result, the comparator 160 outputs a hit report to the line 161, and upon receiving the hit report, the request source 100 fetches the read data (α) from the line 151, and then specifies access start to the lines 101, 102 and 103 “1”, α + 1, and “0” are output as the value, the request address, and the write designation value, respectively, and reading of data from the address α + 1 next to the mishit address is started.

The contents of the addresses α + 1, α + 2,... Are sequentially read from the memory 130 in the same manner as described above. Then, the request source 100 sets the access start designation value, the request address value, and the write instruction value to “1” on the lines 101, 102, and 103, respectively, and the end address β of the block including the mishit address.
Is output immediately before the address β-1 and “0”, and reading of data from the address β-1 is started.
Since the addresses on the lines 46 and 102 are β and β-1, respectively, if the address on the line 146 and the address on the line 911 obtained by adding +1 to the address on the line 102, the output signal is set to “1”. The coincidence detector 910 sets the output signal to “1”. That is, a hit report is output from the comparator 160.

When the hit report is output from the comparator 160, the request source 100 sends the address β-
Read the read data (β-1) read from No. 1. The read data register 150 fetches the read data (β) read from the address β of the memory 130 in the same manner as described above, and
0 increments the lower part 145-2 of the address register 145. Here, the address register 145 stores the lower part 1
When the data 45-2 is all "1", it is set to all "0" at the time of stepping.
Is the head address γ of the block including the address where the miss occurred.

Next, the request source 100 is the line 101, 10
"1", ".beta." And "0" are output as access start designation values, request addresses, and write instruction values to Nos. 2 and 103, respectively, and reading from address .beta. Is started. Also in this case, since the contents of the address register 145 are the head address γ of the block and the request address on the line 102 is the end address of the block, a hit report is output from the comparator 160 to the line 161 and the request source 100 is output. Captures the read data (β) read from the address β of the memory 130. The read data register 150 also takes in the read data (γ) read from the address γ of the memory 130 in the same manner as described above, and the address register section 140 steps down the lower part 145-2 of the address register 145. The content is γ
Set to +1.

Next, the request source 100 is the line 101, 10
2 and 103 are “1”, γ, and “0” as the access start designation value, request address, and write instruction value, respectively.
And starts reading data from the start address γ of the block. Also in this case, since the content of the address register 145 is γ + 1 and the request address on the line 102 is γ, a hit report is output from the comparator 160, and the request source 100 receives the address γ of the memory 130.
Is read via the line 151. Thereafter, the request source 100 performs the same operation as described above until the reading for the address β-1 immediately before the mishit address is completed. As described above, according to the present embodiment, the read access to the tail address is performed in the same manner as the read access to the continuous address when the read access is performed to the head address of the block after the tail address of the block. At the time of completion, the data of the first address to be accessed next is held in the read data register 150, so that the access can be speeded up.

[0051]

As described above, according to the present invention, during the read access, if you are outputs the comparison means Gahi Tsu theft report
(The address held in the address holding means is
Increment the part corresponding to the lower part of the address from the strike source
If the result matches the result), the request source reads the data held by the read data holding means, and further causes the read data holding means to read the data indicated by the memory address held by the address holding means. After that, the content of the address holding means is incremented, and when the next address of the memory address previously accessed is accessed, the read data to be accessed this time is already held in the read data holding means. Therefore, considering that there is a very high possibility that the subsequent read address will be the next address of the preceding read address, the apparent memory access time is set to almost 0 with a very high probability, and the speed of memory access is increased. There is an effect that can be. In addition, the present invention provides a comparison means for achieving a performance that approaches the conventional example of forcibly increasing the speed by configuring the memory unit with a high-speed memory element and forcibly increasing the speed or adopting a cache memory system, or in some cases, exceeding the performance. Or simple addition of hardware such as providing an increment function to the address holding means, so that the hardware can be implemented economically as compared with them and the control logic is simplified. There is an effect that can be. Here, the address holding means is a memory address from the request source.
Is divided into an upper part and a lower part, and at the time of increment, only the lower part is incremented. The comparing means walks the part where the address held in the address holding means corresponds to the lower part of the address from the request source. If it matches the result of the forward, it outputs a hit report, so when accessing the head address of the block next to the end address of a certain block, as in the case of accessing consecutive addresses, Apparently, there is an effect that the memory access time can be eliminated and high-speed access can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a technology which is a premise of the present invention and embodiments of the present invention.
It is a block diagram for explaining .

FIG. 2 is a timing chart showing the operation of FIG.

3 is a block diagram showing a configuration example of the address register used in implementing real施例of the present invention.

4 is a block diagram showing a configuration example of a comparator for use in carrying out the actual施例of the present invention.

FIG. 5 is an explanatory view of the operation of the real施例of the present invention.

FIG. 6 is a block diagram of a conventional example.

FIG. 7 is a diagram showing a series of accesses.

8 is a diagram expressing the access of FIG. 7 in an address space.

FIG. 9 is a timing chart of a conventional example.

[Explanation of symbols]

 100, 300 ... request source 110, 310 ... memory unit 120, 320 ... write designation flag 125, 325 ... write data register 130, 330 ... memory 140 ... address register section 145, 345 ... address register 150, 350 ... read data register 160 ... Comparator 170 ... Write designation history flag 180 ... OR gate 900 ... Step device 910 ... Match detector 920 ... And gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/00-12/10 G06F 13/16-13/18 G11C 7/00, 11/34 G11C 11 / 41,11 / 401

Claims (2)

(57) [Claims] 1. A method of randomly specifying a memory address
In a memory device that performs access, the memory address from the request source isUpper part and lower part
Divided into minutesFunction to be held and memory address to be held
The lower part ofAddress with the function of incrementing
Storage means, and a memory address stored in the address storage means.
Therefore, a read that holds the read contents of the memory
Data holding means;The address held in the address holding means is the address
Corresponds to the lower part of the address from the request source
If it matches the result of stepping up, issue a hit report
Output a mishit report if they do not match Comparison hand
StepWhen,  At the time of read access, the comparing meansButOutput a credit report
The read data holding means
Data stored in the
Address data holding means,
The data indicated by the memory address
The memory address held by the address holding meansof
Lower partAnd the comparing meansIsShit
When a report is output, the address is held in the address holding means.
Incorporate the memory address from the quest source,
The address holding means holds the read data holding means.
Fetch the data indicated by the memory address
Thereafter, the memory address held by the address holding means is stored.
dressThe lower part ofIncrementWith control means
DoMemory predictive access characterized by the following:apparatus. Wherein said control means, during a write access, the address from the request source incorporated into said address holding means, having a configuration in which writing to the memory according to the address captured by the said address holding means
Memory prospective access according to claim 1, wherein the that
Equipment .