JP3189951B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which operates with low power consumption.

[0002]

2. Description of the Related Art Today, in the design of a semiconductor integrated circuit, a semiconductor integrated circuit to be developed is represented by a function description at a register transfer level (hereinafter, referred to as RTL), and the logic is synthesized using the RTL description. ,
A top-down design for generating a semiconductor integrated circuit to be developed is employed.

FIG. 24 shows a conventional RTL description, and FIG. 25 shows a logic circuit (semiconductor integrated circuit) generated by logic synthesis using the RTL description.

[0004] The RTL description in FIG. 24 is a description clearly defining data transfer between a plurality of registers at a functional level. In the RTL description shown in the figure, r1, r2, r3, and r4 are registers, func1, func2, func3, and func4 are descriptions of the function of a combinational circuit between the registers. An assign statement and an always statement are for each register and each combinational circuit. It describes the connection relationship.

When synthesizing logic from the RTL description of FIG. 24, a circuit is determined on a trade-off curve of area and speed by giving constraints on area or speed.

In the logic circuit shown in FIG. 25 generated from the RTL description, 101, 103, 105, and 107 are flip-flops in which registers r1, r2, r3, and r4 specified in the RTL description are mapped by logic synthesis. 24, the registers r1 and r specified in the RTL description of FIG.
Corresponds directly to 2, r3, r4. 108 is the clock buffer, 10
0, 102, 104, and 106 are func1, func1, of the RTL description in FIG.
This is a combinational circuit corresponding to func2, func3, and func4. The combinational circuits 100, 102, 104 and 106 correspond to the RT shown in FIG.
It is mapped from the function description of L as one circuit on the curve of trade-off between area and speed.

[0007]

By the way, the power consumption P of the semiconductor integrated circuit can be expressed as follows: operating frequency f, load capacitance C,
As the voltage and V [Equation 1], represented by [Equation 1] P = f x C x V 2. Therefore, there are three methods for reducing the power consumption of the semiconductor integrated circuit: lowering the operating frequency, lowering the load capacity, or lowering the power supply voltage. The reduction effect due to the reduction in the power supply voltage is the largest.

However, when the power supply voltage is set low, the delay time of the critical path having the maximum delay time among many paths constituting the logic circuit also increases.

For example, Japanese Unexamined Patent Publication No. Hei 5-299624 discloses that, among many logic gates, a logic gate which operates at a low speed is driven by a low voltage source, and other logic gates requiring a high speed operation are driven by a high voltage source. Although a driving technique is disclosed, the use of two power sources of a low voltage source and a high voltage source taking a critical path into consideration is not disclosed.

An object of the present invention is to provide a semiconductor integrated circuit which operates with low power consumption without increasing the delay time of the critical path of each combinational circuit of the semiconductor integrated circuit to be developed.

[0011]

That is, the present invention utilizes the technique disclosed in Japanese Patent Application Laid-Open No. 5-299624,
Only the logic gates constituting the critical path are driven by a high voltage source, and the other logic gates are driven by a low voltage source, thereby reducing the current consumption of the entire semiconductor integrated circuit without increasing the maximum delay time of the critical path. Is reduced by using a low-voltage power supply to reduce power consumption. However, the present invention has room for further improvement.

The details of the improvements are as follows. As described above, when data is transmitted from a low-speed operation type logic gate driven by a low voltage source to a high-speed operation type logic gate driven by a high voltage source, for example, see Japanese Patent Application Laid-Open No. Hei 5-6796.
As disclosed in Japanese Unexamined Patent Application Publication No. 2003-163, a level conversion circuit for converting the output level of a logic gate driven by a low voltage source into a high level needs to be disposed between the two logic gates. However, since each of the combinational circuits shown in FIG. 25 is a circuit composed of a large number of logic gates as shown in, for example, FIG. 26 or FIG. Assuming that the path shown in FIG. 2 is driven by a high voltage source, the critical path is driven by a plurality of positions (in FIG.
It is determined that a level conversion circuit is required at eight locations in FIG. 6 and at twelve locations in FIG. In a highly integrated semiconductor integrated circuit, the number of combination circuits is extremely large, and the number of logic gates constituting each combination circuit is also extremely large. Therefore, in such a highly integrated semiconductor integrated circuit, the number of positions requiring a level conversion circuit in one combinational circuit having a critical path is large, and the number of combinational circuits having a critical path is large. The number of positions requiring a level conversion circuit in the entire circuit is enormous. As a result, in the design of a highly integrated semiconductor integrated circuit, it is possible to determine and arrange the position where the level conversion circuit is required as described above using a combination circuit that is only partially limited. In the whole, the determination of the arrangement position of the level conversion circuit is complicated and troublesome, and it takes a long time, and the design becomes complicated.

[0013] To achieve the above object, the present invention provides:
We focused on the following points. That is, first, the semiconductor integrated circuit is
As shown in FIG. 25, it is composed of a large number of registers and a large number of combinational circuits located between the respective registers. Therefore, if a level conversion circuit is arranged in the register, the plurality of combinational circuits have various locations, that is, critical paths. When driving with a high power supply, there is no need to arrange a level conversion circuit at each of a plurality of positions where the level conversion circuit is required, and the number of arrangement positions of the level conversion circuit can be reduced and reduced. If a conversion circuit is arranged, in a combinational circuit to which data is transmitted from this level conversion circuit, it is necessary to drive the combinational circuit with a high power supply, but in a semiconductor integrated circuit, the number of logic gates present on a critical path is According to statistics that are about 5% of the number of logic gates constituting the entire integrated circuit, a combination of combinational circuits having a critical path Ratio less for the entire circuit causes,
Therefore, attention was paid to the fact that even if a combinational circuit having a critical path is driven by a high power supply, power consumption does not increase so much.

That is, the semiconductor integrated circuit according to the first aspect of the present invention includes a plurality of combinational circuits having one signal propagation path.
And a stage preceding the at least one combinational circuit;
A semiconductor integrated circuit having a register arranged at a subsequent stage.
Thus, the signal of each combinational circuit is
As a result of estimating the signal propagation delay time of the propagation path,
Select a combinational circuit whose delay time is less than the design delay upper limit.
First combinational circuit generated using the low voltage source as a voltage source
As a result of the estimation, the signal propagation delay time is
A combinational circuit that exceeds the delay upper limit of
And a second combinational circuit generated by the
The output of the first combinational circuit is the input of the second combinational circuit.
Between the first combinational circuit and the second combinational circuit in the form
As a result of investigating the coexistence, the output becomes the input of the second combinational circuit.
A first combinational circuit serving as a power source includes the high voltage source as a voltage source.
Characterized in that it is replaced by a second combinational circuit .

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the first combination circuit is provided.
The circuit is entirely composed of a first logic gate driven by a low voltage source, and the second combinational circuit is driven by a high voltage source.
All of the second logic gates .

[0016] In addition, an invention according to claim 3, wherein, in the semiconductor integrated circuit of claim 2, wherein the second in combination circuit second logic gate outputs the received and the second of
A logic gate located outside the combinational circuit;
The logic gate receiving the output of the logic gate is driven by a low voltage source.
It is characterized by comprising a first logic gate to be operated .

[0017] In addition, the invention of claim 4, wherein, in the semiconductor integrated circuit of claim 2 wherein, outputs a signal to the second logic gate in the second combinational circuit and said
A logic gate located outside the second combinational circuit;
The logic gate that outputs a signal to the second logic gate is
It is characterized by comprising a second logic gate driven by a pressure source .

[0018]

[0019]

[0020]

[0021]

According to the above configuration, the semiconductor integrated circuit according to the first to fourth aspects has the following operations. That is, the signal transmission
The entire combinational circuit that has a critical path whose seeding delay time exceeds the design delay upper limit value uses a high voltage source as the voltage source.
It is driven at a high voltage Te, Shin of the critical path
The signal propagation delay time can be suppressed to be less than the delay upper limit value allowed by design. Moreover, having the critical path
Other combinational circuits that output signals to
Is replaced by a second combinational circuit that uses a pressure source as a voltage source.
Only the combinational circuit having the critical path
Required level conversion circuit compared to when driving with a pressure source.
The number of paths can be reduced, and the design of semiconductor integrated circuits is extremely
Becomes easier. On the other hand, the remaining combinational circuits are driven by a low power supply, so that power consumption is significantly reduced. As a result, low power consumption is achieved in the entire semiconductor integrated circuit.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of an image processing apparatus A having a semiconductor integrated circuit according to the present invention. In FIG. 1, reference numeral 10 denotes an A / D converter for converting an external signal from analog to digital, 11 denotes a general-purpose DRAM, and 12 denotes a semiconductor integrated circuit of the present invention, which takes out data from the DRAM 11 or stores data. A first semiconductor integrated circuit 13 for performing image processing, 13 is a general-purpose control microcomputer for controlling the first semiconductor integrated circuit 12, and 14 receives a signal from the first semiconductor integrated circuit 12 to further perform image processing. This is a second semiconductor integrated circuit to be performed.

Reference numeral 15 designates, for example, 3 V
The high-voltage source 16 is also a low-voltage source, for example 2 V, externally arranged. The image processing apparatus A shown in FIG. 1 includes a high-voltage line 17 connected to the high-voltage source 15 and the low-voltage source 1.
6 connected to the low-voltage wiring 18. In order to reduce the power consumption of the image processing apparatus A, the low voltage source 16 is used as a voltage source for the first and second semiconductor integrated circuits 12 and 14 for image processing. It is supplied only to the first and second semiconductor integrated circuits 12 and 14. On the other hand, the high voltage of the high-voltage wiring 17 is applied to other general-purpose circuits 10, 1
1, 13 are supplied. Since the interface voltage between the circuits 10 to 14 needs to be high, the high voltage wiring 17
High voltage is applied to two semiconductor integrated circuits 12, 1 for image processing.
4 as well.

The low voltage source 16 may be an internal low voltage source in which the voltage of the high voltage wiring 17 is reduced by an internal transistor by the threshold voltage. The configuration is described in, for example,
96369, the details of which are omitted. In this case, the low voltage source 16 arranged outside is unnecessary.

The first semiconductor integrated circuit 1 for image processing
FIG. 2 shows the internal configuration of No. 2. In the figure, reference numeral 20 denotes a chip, 21... Are a plurality of input / output pads arranged on the outer periphery of the chip 20, and 22 is the plurality of input / output pads 2.
The internal core portion 22 is provided with five functional blocks A to E except for the arrangement region of 1. The functional blocks A to D are arithmetic processing circuits that perform different arithmetic processing, and the functional block E is, for example, a ROM.
, A small-capacity memory cell such as a RAM.

The present invention is applied to the function blocks A to D other than the function block E including the memory cell section in the internal core section 22 in the first semiconductor integrated circuit 12 for image processing. .

FIG. 3 is a logic circuit diagram of an arbitrary one functional block (for example, A) of the first semiconductor integrated circuit 12.

The functional blocks (part of the semiconductor integrated circuit) shown in FIG. 14 show a logic circuit obtained by performing logic synthesis from the RTL description shown in FIG. In the figure, reference numerals 2, 4, 6, and 8 denote flip-flop circuits constituting registers r1, r2, r3, r4 described in the RTL of FIG. 24, respectively. Reference numerals 1, 3, 5 and 7 denote combination circuits func1, func2,
It is a combinational circuit that constitutes func3 and func4 and is located between the registers r1 to r4 or at the preceding stage. In FIG. 3, for the sake of simplicity, the output of each combinational circuit is input only to the flip-flop circuit at the next stage, but the signal may be transferred to another combinational circuit.

The flip-flop circuits 2, 6, and 8 are 2V systems using the 2V low voltage source 16 as a voltage source.
The remaining flip-flop circuit 4 has a voltage source of 2V / 3 using both power sources of a low voltage source 16 of 2V and a high voltage source 15 of 3V.
It is a V system. The 2V / 3V flip-flop circuit 4 has a level conversion circuit as described later, and the 2V flip-flop circuits 2, 6 and 8 do not have a level conversion circuit. Further, the combination circuits 1, 3 and 7 are 2V combination circuits (first circuit) using a 2V low voltage source 16 as a voltage source.
That is, the combinational circuit) is a combinational circuit in which all of the logic gates constituting the combinational circuit are driven at a low voltage of 2V. That is, a 3V-system combination circuit (second combination circuit), that is, a combination circuit in which all the logic gates constituting the combination circuit are driven by a high voltage of 3V.

In addition, 9 is a 2V system clock buffer (clock supply means) using the 2V low voltage source 16 as a voltage source.
Wherein the four flip-flop circuits 2, 4,.
Clock is supplied to 6 and 8.

FIG. 4 shows the configuration of the flip-flop circuits 2, 6, and 8 having no 2V-system level conversion circuit. In the figure, reference numeral 30 denotes a master latch for receiving one external signal D, and 31 denotes a slave latch which is connected in series to the output side of the master latch 30 and outputs two complementary signals. The slave latch 31 forms a temporary data storage unit 36. 32 is an output buffer connected to the output side of the slave latch 31, and 33 is an internal clock generation circuit (clock supply means) for generating complementary internal clocks CK and NCK from a clock CLK input from the outside. The circuits 30 to 33 are a 2V system using the 2V low voltage source 16 as a voltage source.

FIG. 5 shows the configuration of the flip-flop circuit 4 having the 2V / 3V system level conversion circuit. The flip-flop circuit 4 shown in FIG.
A master latch 30 and a slave latch 31 connected in series with the same configuration as the flip-flop circuit 2 of the system, an internal clock generation circuit 33, an output buffer 34 using the 3V high voltage source 15 as a voltage source, A level conversion circuit 35 is provided between the latch 31 and the output buffer 34. The level conversion circuit 3
Reference numeral 5 denotes a 2V / 3V system, in which the potential difference between complementary signals of the 2V system slave latch 31 is a low voltage (2V). Has a function of converting the level into a high voltage signal in which the potential difference between the signals is high voltage (3 V) and outputting the high voltage signal.

FIGS. 6A and 6B show a specific configuration of the level conversion circuit 35. FIG. In the level conversion circuit 35 of FIG. 3A, reference numerals 40 and 41 denote PMOS transistors, and reference numerals 42 and 43 denote NMOS transistors. One PMOS transistor 40 and one NMOS transistor 42 are connected in series. The other PMOS transistor 41 and the other NMOS transistor 43 are connected in series, and both series circuits are arranged between the high voltage source 15 of 3V and the ground. The gate of the one PMOS transistor 40 is connected to the NMO on the side not connected in series.
The drain of the S-type transistor 43 is connected to the drain of the NMOS transistor 42, and the gate of the other PMOS transistor 41 is connected to the drain of the NMOS transistor 42. The complementary output is taken from the drains of the NMOS transistors 42 and 43. With the above configuration, the PMOS transistor 40 and the NMOS transistor 42, and the PMOS transistor 41 and the NMOS transistor 43 each perform the function of an inverter. That is, when a low voltage of 2 V is supplied to the gate of one NMOS transistor 43 and 0 V is supplied to the gate of the other NMOS transistor 42 by the complementary output of the slave latch 31 in FIG. The NMOS transistor 43 is turned on and the other NMOS transistor 42 is turned off, and accordingly, one PMOS transistor 40 is turned on and the other PMOS transistor 41 is turned off. The drain is connected to the high voltage source 15 of 3V and the drain of the other NMOS transistor 43 is grounded, so that a complementary output having a high potential difference of 3V is obtained. FIG.
In the configuration of (a), the through current from the 3V high voltage source 15 to the 2V low voltage source 16 and the 3V high voltage source 15
The level of the complementary output of the slave latch 31 shown in FIG. 5 can be converted from a low voltage of 2V to a high voltage of 3V without passing through current to V (ground).

FIG. 6B shows a level conversion circuit 35 'having another specific configuration different from the above. The level conversion circuit 35 'shown in FIG.
Instead of the NMOS transistors 42 and 43, two NMOS inverters 45 and 46 are arranged. The two PMOS inverters 45 and 46 each have one
PMOS transistors 47 and 49 and one NMOS
It is formed by connecting the type transistors 48 and 50 in series. The input terminals of both the PMOS inverters 45 and 46, that is, both PMOS and NMOS transistors 47 and 4 connected in series.
The gates 8, 49 and 50 have the slave latch 31 of FIG.
Are output. An output terminal of one of the PMOS inverters 45, that is, a PMOS transistor 47
Is connected to the gate of the PMOS transistor 41 not connected in series with the PMOS inverter 45, and the output terminal of the other PMOS inverter 46 is connected to the PMOS transistor 40 not connected in series with the PMOS inverter 46. Are connected to the respective gates.
The outputs of the two PMOS inverters 45 and 46 are complementary outputs of the level conversion circuit 35 '. With the above configuration, 3V
The complementary output of the slave latch 31 shown in FIG. 5 is supplied from the low voltage of 2V without flowing a through current from the high voltage source 15 to the low voltage source 16 of 2V and a through current from the high voltage source 15 of 3V to the ground. The level can be converted to a high voltage of 3V. Further, P which constitutes the CMOS inverters 45 and 46
The MOS transistor is a 3V high voltage source 1 in a transient state.
5 to suppress the through current from flowing to ground.

As can be seen from the above description, the semiconductor integrated circuit shown in FIG.
3 is a low-voltage 2V system, has a 2V combination circuit 3 at its input, and has a 3V combination circuit 5 at its output.
Is a low-voltage / high-voltage system (2 V / 3 V system), and a flip-flop circuit 6 having a 3 V system combination circuit 5 at the input and a 2 V system combination circuit 7 at the output is a low voltage 2 V system. It is composed of a system.

In the above description, the registers r1, r2, r3, r4 are constituted by flip-flop circuits, but may be constituted by latch circuits instead of the flip-flop circuits. FIGS. 7 and 8 show a specific configuration of the latch circuit. FIG. 7 shows a low-voltage 2V-system latch circuit 51. A latch circuit 51 shown in FIG. 7 is a latch unit (temporary data storage unit) that receives and latches one signal D and obtains a complementary output.
52, an output buffer 53 connected to the output side of the latch unit 52, and an internal clock generation circuit 54 that generates an internal clock NG from the external clock G and outputs the internal clock NG to the latch unit 52. , An external clock G are also supplied to the latch unit 52. The above circuits 52 to 54 are 2V using the 2V low voltage source 16 as a voltage source.
System. FIG. 8 shows a low-voltage / high-voltage (2 V / 3 V) latch circuit 51 ′. The latch circuit 51 'in FIG.
Similarly to the configuration of the low-voltage 2V-system latch circuit, the latch unit 52 and the internal clock generation circuit 54 using the 2V low-voltage source 16 as a voltage source, and the output buffer 55 using the 3V high-voltage source 15 as a voltage source And an input signal interposed between the latch section 52 and the output buffer 55 to reduce the input signal to a low voltage (2 V).
Level conversion circuit 5 for converting the level from the high voltage (3V) to
6 is provided. The specific configuration of the level conversion circuit 56 is the same as the specific configuration shown in FIG. 6A or 6B.

Next, an algorithm of a logic synthesis method for logic-synthesizing the semiconductor integrated circuit shown in FIG. 3 based on the connection information of the logic cells will be described with reference to the logic synthesis apparatus of FIG. 9 and the flow charts of FIGS. Will be explained.

FIG. 9 shows the overall schematic configuration of the logic synthesis device 60. In the figure, 61 is a reading unit, 62 is a translation unit, 63 is an optimization processing unit, 64 is a cell allocation unit, 65 is a timing verification unit, 66 is a circuit diagram generation unit, and 67 is an output unit. The reading unit 61 is the same as that shown in FIG.
RTL description (hardware description language) shown in
A netlist shown in FIG. 11 in which the signal transmission relationship between registers is clearly defined based on the connection information level of the logic cell based on the L description, or a schematic shown in FIG. The translation unit 62 converts the RTL description read from the reading unit 61 into a state transition diagram, a Boolean expression, a timing diagram, and memory specifications such as a memory type, the number of bits and the number of words.

The optimization processing unit 63 includes a state transition diagram optimization processing unit 63a for optimizing the obtained state transition diagram and a state for generating a circuit (state machine) corresponding to the optimized state transition diagram. A machine generator 63b, a compiler 63c for compiling a timing diagram obtained for compiling the obtained timing diagram, a composing unit 63d for composing a memory based on the specification of the obtained memory, Combining unit 63 for combining the interface unit based on the stored memory
e. Further, the optimization processing unit 63 includes the reading unit 6
If the input to 1 is an RTL description, the logic is optimized based on the obtained state machine, the obtained Boolean expression and the synthesized interface unit, and the connection information of the optimized logic cell is obtained. While generating, the reading unit 61
In the case where the input to is a netlist or schematic, there is a logic optimization unit 63f that optimizes the logic of the input netlist or schematic and generates connection information of the optimized logic.

The output unit 67 outputs a netlist indicating the logic circuit shown in FIG. 3 or a logic circuit diagram (schematic) obtained by schematizing the netlist.

The present invention exists in the cell allocating section 64 shown in FIG. Next, based on the cell allocation (cell mapping) processing by the cell allocation section 64, ie, the cell connection information obtained by the logic optimization section 63f, FIG.
The algorithm for logically synthesizing the semiconductor integrated circuit shown in FIG. 1 will be described with reference to the flowchart of FIG. Note that FIG. 13 mainly illustrates features of the present invention.

Referring to FIG.
In 1 to S4 (first step), the combinational circuit whose signal propagation delay time is equal to or less than the designed delay upper limit value is combined with the first combinational circuit using the 2V low voltage source 16 as a voltage source, and vice versa. The combinational circuit whose signal propagation delay time exceeds the designed delay upper limit value is combined with the second combinational circuit using the 3V high voltage source 15 as a voltage source.

The first step is performed as follows in this embodiment. That is, first, after reading the cell connection information from the logic optimizing unit 63f, an arbitrary flip-flop is used in step S1 by using each signal propagation delay time of the low-voltage (2V) flip-flop circuit and the combinational circuit. The signal propagation delay time in the signal propagation path from the clock input of the flip-flop circuit to the data input of the next flip-flop circuit is estimated for each signal propagation path. The estimation of the signal propagation delay time is performed, for example, by using a logic (AND circuit, NOR
Circuit or NOT circuit), for example, the type of logic, the number of inputs, and the number of logic stages are extracted, and the signal propagation delay when each logic is mapped to a cell based on the logic-related information and the cell technology. This is done by calculating and estimating the time. Next, in step S2, it is determined whether or not the estimation result of the signal propagation delay time is equal to or less than the upper limit value of the designed delay. When the combinational circuit, which is an aggregate, is mapped to a combinational circuit (first combinational circuit) of a low-voltage (2 V) logic cell library (hereinafter, referred to as lib), and the estimation result exceeds the upper limit of the design delay. Sets the combinational circuit, which is an aggregate of logic gates arranged on the signal propagation path in step S4, to a high voltage (3
V) This is performed by mapping to a combinational circuit of lib (a second combinational circuit).

Subsequently, the following processing is performed in steps S5 and S6 (second step). That is, in step S5, the combination circuit of the 2V system and the combination circuit of the 3V system are mixed so that the output of the combination circuit of the low voltage system (2V system) becomes the input of the combination circuit of the high voltage system (3V system). It is checked whether or not there is a mixture of the above shapes. In step S6, among the 2V-system logic gates constituting the 2V-system combination circuit (first combination circuit), the 3V-system combination circuit Subsequent logic gates including input logic gates are
Mapping is performed again so as to be replaced by a 3V-system logic gate constituting the combination circuit (second combination circuit) of ib. If there is no mixture, 3V logic gates should be 3
There is no need to convert to V-based logic gates.

After that, since the voltage systems of the combinational circuits located on the input side and the output side of the register have already been determined by the above-described logic synthesis, steps S7 to S9 (third step) are performed.
In step (3), the following processing is performed. That is, it is checked whether or not each register converts the level of the potential from the input of the low voltage (2 V) to the output of the high voltage (3 V). If the level is to be converted, the register (the flip-flop circuit) that performs the level conversion in step S8. 4 is mapped to the 2V / 3V-system flip-flop circuit of FIG. 5 or the 2V / 3V-system latch circuit of FIG. 8, and if the level is not to be converted, the register whose level is not converted is replaced with the 2V / 3V of FIG. 7 is mapped to the flip-flop circuit of the system or the latch circuit of the 2V system in FIG.

FIG. 14 shows a modification of the logic synthesis method shown in FIG. In the logic synthesis method of FIG. 13, the signal propagation delay time is estimated in the first step, and the combinational circuit is mapped to a low-voltage (2V) combinational circuit or a high-voltage (3V) combinational circuit according to the estimation result. Instead of
In the present modified example, first, in step S10, mapping is performed on a 2V lib combinational circuit (first combinational circuit), and then, in step S11, it is determined whether or not the result of the combination is equal to or less than a design delay upper limit value. Only when the delay exceeds the upper limit value, mapping is performed again in step S12 so that the combined circuit of 2Vlib (first combined circuit) is replaced with a combined circuit of 3Vlib (second combined circuit). The second and third steps of this modified example are the same as the logic synthesis method of FIG. 13 described above, and a description thereof will be omitted.

FIG. 15 shows a modification in which a part of the logic synthesis algorithm shown in FIG. Hereinafter, the logic synthesis algorithm of FIG. 15 will be described with respect to portions different from FIG. In the first step, step S1
3 is added. This step S13 is equivalent to step S2
In the case where the estimation result of the signal propagation delay time exceeds the upper limit value, all the low voltages (2 V) li exceeding the upper limit value are set in advance.
b), and after this step S13, the extracted first combinational circuit is combined in step S4 with a high-voltage (3V) lib combinational circuit (the second combinational circuit). Circuit). In the second step, step S14 is added. This step S14 is a step of, in the case where the combination circuit of the 2V system and the combination circuit of the 3V system are mixed in step S5, extracting all of the mixed circuit (first combination circuit) of the 2V system in advance. After step S14, the extracted first combinational circuit is mapped again to the high-voltage (3V) lib combinational circuit (second combinational circuit) in step 6. Further, in the second step, after re-mapping to the second combinational circuit in the step 6,
An algorithm returning to step 5 is added. This algorithm takes into consideration that the combination of the 2V system combination circuit and the 3V system combination circuit may newly occur due to the mapping to the 3V system combination circuit in step 6 described above. This mixture is determined in step 5, and if there is this mixture, again in steps S14 and S6,
This is for repeating the extraction of the mixed circuit of the mixed 2V system and the re-mapping of the extracted first combination circuit to the combination circuit of the high voltage (3V) lib (the second combination circuit).

FIG. 16 shows a modification in which a part of the logic synthesis algorithm shown in FIG. As in the case of FIG. 15, in this modification, when the signal propagation delay time exceeds the upper limit (step S11), the combination circuit (the first combination) of all low-voltage (2V) libs exceeding the upper limit is used in advance. Step 15 for extracting the circuit
If the combination circuit of the 2V system and the combination circuit of the 3V system are mixed together (step S5), all of the mixed 2V system combination circuits (first combination circuits) are extracted in advance. Step 16 is added to the second step. In this second step, the 2V-system combination circuit and the 3V-system combination circuit are added due to the remapping to the 3V-system combination circuit (step 6). In consideration of the fact that a mixture of
An algorithm is added to return to step 5 for determining the presence or absence of the coexistence after the processing of.

Accordingly, in each algorithm of the logic synthesis method shown in FIGS. 15 and 16, for example, as shown in FIG. 17A, when the signal propagation delay time or the estimation result exceeds the design delay upper limit value. In the first combinational circuit having the critical path, four logic gates 5a, 5a,
The signal is mapped to a second combinational circuit 5 composed of b, 5c, and 5d so that the signal propagation delay time of the signal propagation path of the second combinational circuit 5 is equal to or less than the designed upper limit of the delay.

Thereafter, it is determined whether or not the output of the logic gate driven by the low voltage source is mixed with the input of the logic gate driven by the high voltage source. The mixed first logic gate 100b is remapped to a second logic gate driven by a high voltage source as shown by hatching in the figure, as shown in FIG. By this remapping, the first driven by the lower voltage source
In which the output of the logic gate 100a is input to the input of the second logic gate 100b driven by a high voltage source, the first logic gate 100a is similarly hatched in the figure. As shown in the above, remapping is performed to the second logic gate driven by the high voltage source. continue,
Due to the remapping, the output of the first logic gate 101a driven by the low voltage source is mixed with the input of the second logic gate 100b driven by the high voltage source. The mixed first logic gate 101a is remapped to a second logic gate driven by a high voltage source as shown by hatching in the figure as shown in FIG.

Then, when the mixture is eliminated,
When each flip-flop circuit converts the level of a potential from a low-voltage (2 V) input to a high-voltage (3 V) output, as shown in FIG. Is mapped to the 2V / 3V-system flip-flop circuit shown by.

[0053]

FIG. 18 shows an embodiment in which the logic synthesis method of FIG. 13 is applied to a semiconductor integrated circuit having a different configuration from the semiconductor integrated circuit of FIG.

FIG. 1 shows a semiconductor integrated circuit using a scan test flip-flop circuit as a register.
Scan flip-flop circuits 80, 81, 82, 83
And 84 are 2V / 3V scan flip-flop circuits, and the other scan flip-flop circuits are 2V scan flip-flop circuits.

FIG. 19 shows the configuration of a 2V-system scan flip-flop circuit. The scan flip-flop circuit shown in the figure includes a multiplexer 90 in addition to the configuration of the low-voltage (2 V) flip-flop circuit shown in FIG. The multiplexer 90 uses the low voltage source 16 of 2V as a voltage source, and receives two data D and DT by a control signal SE.
Is selected and output. The data selected by the multiplexer 90 is input to the master latch 30. About the other structure, the same code | symbol is attached | subjected to the same part as the structure of the flip-flop circuit shown in FIG. 4, and the description is abbreviate | omitted.

FIG. 21 shows a 2V-system scan flip-flop circuit having another configuration. The 2V-system scan flip-flop circuit shown in FIG. 9 includes a data input selection circuit 91 in addition to the configuration of the flip-flop circuit shown in FIG. The data input selection circuit 91 is connected to the master latch 30
When the data D is input by the external clock CLK, the input of the other data DT is inhibited. When the master latch 30 inhibits the input of the data D, the other data DT is input by the other clock CLKT. Output to the master latch 30. In the figure, reference numeral 92 denotes an internal clock generation circuit which receives the two types of external clocks CLK and CLKT to generate two types of internal clocks CK and NCK, and applies the internal clocks CK and NCK to a master latch 30 and a slave. Latch 31
Output to

FIG. 20 shows a 2V / 3V scan flip-flop circuit. 19 includes the same circuits as the master latch 30, slave latch 31, internal clock generation circuit 33, and multiplexer 90 of the 2V-system scan flip-flop circuit in FIG. It has an output buffer 95 as a source and a level conversion circuit 96 of a 2V / 3V system. The 2V / 3V system level conversion circuit 96 is interposed between the slave latch 31 and the output buffer 95. The specific configuration of the 2V / 3V system level conversion circuit 96 is the same as that shown in FIG. 6A or 6B.

FIG. 22 shows another 2V / 3V scan flip-flop circuit. The scan flip-flop circuit shown in FIG. 21 includes the master latch 30, the slave latch 31, and the scan flip-flop circuit of the 2V system shown in FIG.
Internal clock generation circuit 92 and data input selection circuit 91
And an output buffer 97 using a 3V high voltage source as a voltage source, and a 2V / 3V system level conversion circuit 98. The 2V / 3V level conversion circuit 98 is interposed between the slave latch 31 and the output buffer 97. The specific configuration of the 2V / 3V level conversion circuit 98 is the same as that shown in FIG. 6A or 6B.

A method of logically synthesizing the semiconductor integrated circuit of FIG. 18 will be described. Assume that combinational circuits 86, 87 and 88 have a critical path. According to the algorithm of the logic synthesis method shown in FIG. 13, the combination circuits 86 and 8 are mapped in the first mapping stage (first step) of the combination circuit.
7 and 88 are mapped to a 3V lib combinational circuit (second combinational circuit), and the other combinational circuits are mapped to a 2V lib combinational circuit (first combination circuit).

Next, at the stage of remapping the combinational circuit (second step), the combinational circuit 89 is remapped to a combinational circuit of 3 Vlib. Then, at the stage of register (flip-flop circuit) mapping (third step), the flip-flop circuits 80, 81, 82, 83 and 84 are formed.
Is mapped to a 2V / 3V flip-flop circuit,
Another flip-flop circuit is mapped to a 2V-system flip-flop circuit.

In the semiconductor integrated circuit of FIG. 18 generated as described above, a low-voltage logic lib of 2V and a high-voltage logic lib of 3V coexist, but the voltage source of each combinational circuit is 2V. Of the low voltage source 16 or the high voltage source 15 of 3V, and the level conversion of the voltage from the low voltage of 2V to the high voltage of 3V is performed by a level conversion circuit in a scan flip-flop circuit of a 2V / 3V system. Done.

The semiconductor integrated circuit of FIG. 18 has eight scan chains indicated by broken lines in the figure, in which signals are transmitted only through a plurality of scan flip-flop circuits without passing through combinational circuits in the scan test mode. For example, input
In the scan chain connected to Si3, the scan flip-flop circuit 81 of the 2V / 3V system performs level conversion from a low voltage of 2V to a high voltage of 3V as in the normal mode, and the next stage scan flip-flop circuit of the scan flip-flop circuit 81 Circuit 99 from 3V high voltage to 2
Level conversion is performed to a low voltage of V. Therefore, even when the scan flip-flop circuit shown in FIG. 20 or FIG. 22 is used, even in the scan test mode in which the signal transmission path is different from the normal path (that is, the path passing through the combinational circuit), 2V
The scan test of the semiconductor integrated circuit of the present invention in which the low-voltage system and the 3V high-voltage system coexist is possible.

In the above description, the present invention has been applied to the function block A constituting the memory cell section E other than the memory cell section E formed in the internal core section 22 of the chip 20, but to the other function blocks BD. It goes without saying that a plurality of functional blocks A to
Needless to say, the present invention can be similarly applied between D.

Therefore, according to the semiconductor integrated circuit of this embodiment, in the combinational circuit having a critical path, logic is synthesized so that the logic gates 5a to 5d on the critical path are driven by a high voltage system of 3V. The signal propagation delay time of the critical path can be suppressed to less than the delay upper limit allowed by design.

Further, in the other combinational circuits 110 and 111 including the logic gates 5b and 5d driven by the high voltage system on the signal propagation path, the logic gates driven by the low voltage system or other high voltage systems are used. Although the number of the combinational circuits including the driven logic gates is extremely small compared to the number of the combinational circuits provided in the semiconductor integrated circuit, the increase in the current consumption can be suppressed, while the remaining Is driven by the low voltage source 16 of 2 V, the current consumption can be reduced as a whole of the semiconductor integrated circuit, and the power consumption can be reduced.

The semiconductor integrated circuit of the present embodiment shown in FIG.
5 is compared with the conventional semiconductor integrated circuit of FIG. In the conventional semiconductor integrated circuit of FIG. 25, each of the combinational circuits 100, 102,.
Signal propagation delay times of 104 and 106 are 6 ns and 12 n as shown in the figure.
s, 18 ns, and 8 ns, and the delay time from the clock input to the data output of the flip-flop circuit is 2 ns. Since the maximum delay of the combinational circuit is 18 ns of the combinational circuit 104, the maximum delay of the circuit of FIG. The operating frequency is 1000 / (2 + 18) = 50MH.

On the other hand, in the semiconductor integrated circuit of this embodiment shown in FIG. 3, the delay time of the combinational circuit 5 having a critical path is the same as the conventional voltage system (3 V). is there. The delay time of the combinational circuits 1, 3 and 7 having no critical path increases as the delay of the logic cell increases, since the power supply voltage is reduced from the high voltage of 3V to the low voltage of 2V. FIG.
Of semiconductor integrated circuits, the upper limit of the design delay time is 20 ns
It is assumed that the delay time of a cell is 1.5 times as large as that of a low voltage source of 2 V with respect to a high voltage source of 3 V. The maximum of the delay times of the combination circuits 1, 3 and 7 having no critical path is 18 ns of the combination circuit 3.

A low voltage source 16 of 2V and a high voltage source 15 of 3V
As a result, the maximum delay of the combinational circuit is 18 ns for the combinational circuit 3 having no critical path and the combinational circuit 5 having the critical path. Since each signal propagation delay time from the clock input to the data output of the flip-flop circuits 2 and 4 is 2 ns, and the delay time of each of the combinational circuits 3 and 5 is 18 ns, the maximum operating frequency of the semiconductor integrated circuit of this embodiment is Is 1000 / (2 + 18) = 50MH, and the combinational circuits 1 and 3 having no critical path
And 7 are driven by the low voltage source 16 of 2 V, the same maximum operating frequency as that of the conventional semiconductor integrated circuit can be obtained.

FIG. 23 shows the delay between the clock input of the flip-flop circuit and the data input of the next-stage flip-flop circuit in the semiconductor integrated circuit of this embodiment of FIG. 3 and the conventional semiconductor integrated circuit of FIG. That is, the distribution of the signal propagation delay time obtained by adding the delay times of the register and the combinational circuit is shown. FIG. 3A shows the delay distribution of a conventional 3 V voltage semiconductor integrated circuit, and FIG. 3B shows the delay distribution of a 2 V and 3 V mixed semiconductor integrated circuit of the present embodiment. In a conventional semiconductor integrated circuit, when only the power supply voltage is changed from a high voltage system of 3V to a low voltage system of 2V, the maximum delay time is 20 ns.
In contrast, the delay time of the critical path exceeds the upper limit of the designed delay of 20 ns, whereas the semiconductor integrated circuit of this embodiment shown in FIG. Is changed to a high voltage system of 3V, and the other combinational circuits having no critical path are set to a low power system of 2V.
20ns can be satisfied. FIG. 11B shows the delay distribution at this time.

Next, the power consumption of the conventional semiconductor integrated circuit is compared with that of the semiconductor integrated circuit of the present invention. The power consumption of the conventional semiconductor integrated circuit is P, the power supply is a dual power supply of a high voltage source of 3 V and a low voltage source of 2 V, the ratio of the critical path in the entire circuit is 10%, and the 2V / 3V flip-flop of the present invention. Assuming that the power consumption of the flip-flop circuit is different from that of the conventional flip-flop circuit by 10%,
As shown in the following equation, the power consumption of the semiconductor integrated circuit of the present invention is [Px (2/3)] ² x 0.9 + Px 1.1 x 0.1 = Px 0.51, and the power consumption is reduced by 49%.

Further, assuming that the ratio of the critical path to the entire circuit is 5% under the above conditions, the power consumption of the semiconductor integrated circuit of the present invention is expressed by the following equation: [Px (2/3)] ² x 0.95 + Px 1.1 x 0.05 = P x 0.48, and the power consumption is reduced by 52%.

Next, the circuit scale of the conventional semiconductor integrated circuit is compared with that of the semiconductor integrated circuit of the present invention.

The circuit scale of the conventional semiconductor integrated circuit is S, the proportion of the flip-flop circuit in the semiconductor integrated circuit is 20%, and the proportion of the flip-flop circuit having the level conversion circuit in the whole flip-flop circuit is 10%.
%, And if the 2V / 3V flip-flop circuit of the present invention has an area increase of 10% due to a difference in circuit configuration from the conventional flip-flop circuit, the circuit scale of the semiconductor integrated circuit of the present invention is expressed by the following equation. Then, S x 0.8 + S x 0.18 + S x 1.1 x 0.02 = S x 1.002, and the increase in the circuit scale is limited to 0.2%.

Further, assuming that the ratio occupied by the flip-flop circuit having the level conversion circuit in the whole flip-flop circuit under the above-mentioned conditions is 5%, the circuit scale of the semiconductor integrated circuit of the present invention is expressed by the following equation. , S x 0.8 + S x 0.19 + S x 1.1 x 0.01 = S x 1.001, and the increase in the circuit scale remains at 0.1%.

[0076]

As described above, according to the semiconductor integrated circuit of the first to fourth aspects of the present invention, signal propagation is achieved.
The entire combinational circuit having a critical path whose delay time exceeds the design delay upper limit value is driven by a high voltage using a high voltage source as a voltage source, so that the signal propagation delay time of the critical path is allowed by design. It can be kept below the upper limit. And the union with the critical path
Other combinational circuits that output signals to the
Since the second combinational circuit as a voltage source has been replaced,
Only combinational circuits with a critical path are driven by a high voltage source
The number of required level conversion circuits is lower than
Design of semiconductor integrated circuits
You. On the other hand, since all the remaining combinational circuits are driven by the low voltage source , the current consumption can be reduced as a whole of the semiconductor integrated circuit, and the power consumption can be reduced.

Further, in another combinational circuit including a logic gate driven by a high-voltage system on the critical path in a signal propagation path, the logic gate is driven by a low-voltage system or driven by another high-voltage system. Although including logic gates, the number of such combinational circuits is extremely small compared to the number of combinational circuits provided in the semiconductor integrated circuit, so that the increase in current consumption can be kept small, while all the remaining combinational circuits are included. Is driven by the low voltage source 16 of 2 V, the current consumption can be reduced as a whole of the semiconductor integrated circuit, and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is an overall schematic configuration diagram of an image processing system.

FIG. 2 is an overall schematic configuration diagram of a semiconductor chip.

FIG. 3 is a diagram illustrating a connection relationship between a plurality of registers and a plurality of combinational circuits of the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 4 is a configuration diagram of a flip-flop circuit having no level conversion circuit.

FIG. 5 is a configuration diagram of a flip-flop circuit having a level conversion circuit.

FIG. 6 is a diagram showing a specific configuration of a level conversion circuit.

FIG. 7 is a configuration diagram of a latch circuit having no level conversion circuit.

FIG. 8 is a configuration diagram of a latch circuit having a level conversion circuit.

FIG. 9 is a diagram showing an overall schematic configuration of a logic synthesis device.

FIG. 10 is a diagram illustrating a hardware description language.

FIG. 11 is a diagram showing a net list.

FIG. 12 is a diagram showing a schematic.

FIG. 13 is a diagram illustrating a logic synthesis method of a semiconductor integrated circuit.

FIG. 14 is a diagram illustrating another logic synthesis method of the semiconductor integrated circuit.

FIG. 15 is a diagram showing a modification of the logic synthesis method of FIG.

FIG. 16 is a diagram illustrating a modification of the other logic synthesis method in FIG. 14;

FIG. 17 is an explanatory diagram of mapping to a flip-flop circuit having a second combinational circuit and a level conversion circuit.

FIG. 18 is a diagram showing another semiconductor integrated circuit to be developed.

FIG. 19 is a configuration diagram of a scan flip-flop circuit having no level conversion circuit.

FIG. 20 is a configuration diagram of a scan flip-flop circuit having a level conversion circuit.

FIG. 21 is a configuration diagram of another scan flip-flop circuit having no level conversion circuit.

FIG. 22 is a configuration diagram of another scan flip-flop circuit having a level conversion circuit.

FIG. 23 is a diagram showing a signal propagation delay time of a semiconductor integrated circuit according to a conventional example and an example of the present invention and a distribution of the number of combinational circuits having the delay time.

FIG. 24 is a diagram showing a description of a register transfer level.

FIG. 25 is a diagram showing a logic circuit of a conventional semiconductor integrated circuit.

FIG. 26 is a diagram showing an arrangement position of a level conversion circuit when only a critical path is driven by a high voltage source in an arbitrary semiconductor integrated circuit.

FIG. 27 is a diagram showing an arrangement position of a level conversion circuit in a case where only a critical path is driven by a high voltage source in another arbitrary semiconductor integrated circuit.

[Explanation of symbols]

1, 3, 7 First combination circuit 5 Second combination circuit 2, 4, 6, 8 Flip-flop circuit (register) 9 Clock buffer (clock supply means) 15 High voltage source 16 Low voltage source 22 Internal core unit 30 Master latch 31 Slave latch 33, 33 54, 92 Internal clock generation circuit 35, 35 56, 96, 98 Level conversion circuit 36 Data temporary storage unit 40, 41 PMOS transistor 42, 43 NMOS transistor 45, 46 CMOS inverter 47, 49 PMOS transistor 48, 50 NMOS transistor 51, 51 'Latch circuit (register) 52 Latch section 65 Timing verification section 80-84 Scan test flip-flop circuit (register) 90 Multiplexer 91 Data input selection circuit

Claims (4)

(57) [Claims] 1. A combination circuit having one signal propagation path
A plurality of the at least one combinational circuit
Semiconductor integration with registers arranged at the front and rear stages
A circuit, wherein a low voltage source is used as a voltage source,
As a result of estimating the signal propagation delay time of the
The combinational circuit whose interval is equal to or less than the design delay upper limit
A first combinational circuit generated using a voltage source as a voltage source, and a signal propagation delay time as a result of the estimation,
Combination circuits that exceed the upper limit
And a generated second combinational circuit, and the output of the first combinational circuit is the output of the second combinational circuit.
First combination circuit and second combination circuit in input form
As a result of investigating the coexistence of
The first combinational circuit which is an input of
A semiconductor integrated circuit, wherein the semiconductor integrated circuit is replaced by a second combinational circuit serving as a source . 2. The first combinational circuit is driven by a low voltage source.
All it consists of a first logic gate being dynamic, the second combinational circuit, a second driven by a high voltage source
2. The semiconductor device according to claim 1, wherein the logic gates are all comprised.
A semiconductor integrated circuit as described in the above. Wherein the second logic gate in the second combinational circuit
Receive the output of the second combinational circuit and located outside the second combinational circuit.
A logic gate receiving the output of the second logic gate.
3. The semiconductor integrated circuit according to claim 2 , comprising a first logic gate driven by a voltage source . 4. A second logic circuit in the second combinational circuit.
And outputs a signal to the outside of the second combinational circuit.
A logic gate that outputs a signal to the second logic gate,
3. The semiconductor integrated circuit according to claim 2 , comprising a second logic gate driven by a high voltage source .