JP3192282B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a circuit block for outputting a predetermined output signal in response to an input signal.

[0002]

2. Description of the Related Art ASIC (Application Specific IC)
In the design, a cell which is an arbitrary circuit block is selected from a cell library prepared in advance and connected to each other, whereby a semiconductor device having a desired function can be realized. In the above ASIC design, in order to reduce the feedback at the design stage, shorten the development period, and reduce the development cost, it is necessary to grasp the performance and reliability of each cell. As an evaluation of the performance of each cell, one of the important evaluation items is a timing evaluation of measuring a signal transmission time until an input signal is input and an output signal responsive to the input signal is output.
In this case, in order to measure the timing characteristic unique to the cell, it is necessary to evaluate by removing the influence of the delay generated in the circuit around the cell, for example, the input buffer and the output buffer.

Hereinafter, a conventional semiconductor integrated circuit for performing timing measurement without the influence of a delay in a circuit around a cell will be described with reference to the drawings. FIG. 4 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

FIG. 4 shows a conventional semiconductor integrated circuit 21.
Is a circuit block 1 which is a cell for performing timing measurement; latches 6 to 8 for timing measurement;
, Input pins 10a and 10b for inputting the strobe signals STB for controlling the latches 6 to 8, and input pins 16 to 18 for outputting the output signals of the latches 6 to 8, respectively. .

The input signals input from the input pins 10a and 10b are input to the terminals 1a and 1b of the circuit block 1, respectively. The circuit block 1 outputs a predetermined output signal from the terminal 1c to the latch 6 in response to the input signals input to the terminals 1a and 1b. The latch 6 latches the output signal of the circuit block 1 at the timing when the strobe signal STB input from the input pin 15 falls from “H” to “L”, and outputs the output signal to the output pin 16. The input signal input from the input pin 10a is input to the latch 7, and the input signal input from the input pin 10a is input at the timing when the strobe signal STB input from the input pin 15 falls from "H" to "L". Latch and output to output pin 17.
The input signal input from the input pin 10b is input to the latch 8, and the input signal input from the input pin 10b at the timing when the strobe signal STB input from the input pin 15 falls from "H" to "L". Is latched and output to the output pin 18.

Next, a method of measuring the timing of the circuit block 1 will be described. When one output signal is output in response to two input signals as in the circuit block 1,
The delay time, which is the signal transmission time of the circuit block 1, includes a delay time D1 from when an input signal is input from a terminal 1a to an output signal is output to a terminal 1c, an input signal is input to a terminal 1b, and There is a delay time D2 until the output signal is output, and the later one of the two delay times is the delay time of the circuit block 1. Therefore, in order to measure the delay time of the circuit block 1, the terminal 1a
Delay time D1 from terminal 1c to terminal 1c and terminal 1b to terminal 1
c, and both delay times D2 to c are measured.
Is measured.

First, the circuit block 1 is input from the input pin 10a.
Of the delay time D3 up to the terminal 1a will be described. When an input signal is input to the input pin 10a and then a strobe signal STB is input to the input pin 15, the latch 7
Latches the input signal input from the input pin 10a at the timing when the strobe signal STB falls from "H" to "L", and outputs it to the output pin 17. For example, when a rising signal that changes from "L" to "H" is input to input pin 10a, and when the rising timing of the input signal is later than the falling timing of strobe signal STB, latch 7 is in the "L" state. When the input signal rises earlier than the fall timing of the strobe signal STB, the latch 7 outputs a signal in an "H" state. Therefore, by measuring from the rising timing of the input signal to the falling timing of the strobe signal at which the output signal of the latch 7 changes from "L" to "H", the input pin 10a is connected to the terminal 1 of the circuit block 1.
The delay time D3 up to a can be measured.

Next, the circuit block 1 is input from the input pin 10a.
Of the delay time D4 to the terminal 1c will be described. Input pin 10a from the input signal is input to the terminal 1a of the circuit blocks 1, after the circuit block 1 performs a predetermined operation and outputs an output signal from the terminal 1 c to the latch 6.
The latch 6 latches the output signal output from the terminal 1 c of the circuit block 1 at the timing when the strobe signal STB falls from “H” to “L”, and outputs the output signal to the output pin 16. When the circuit block 1 responds to the input signal, for example,
When outputting a signal from “L” to “H”, the falling timing of the strobe signal STB is changed in the same manner as described above, so that the output of the latch 6 changes from “L” to “H”. Adjust the timing. Therefore, by measuring from the timing when the input signal input to the input pin 10a rises to the falling timing of the strobe signal STB when the output signal of the latch 6 changes from "L" to "H", the input pin is measured. 10
The delay time from “a” to the terminal 1 c of the circuit block 1 can be measured.

As a result, the delay time D1 from the terminal 1a to the terminal 1c, which is the delay time of the circuit block itself, can be obtained by subtracting the delay time D3 from the delay time D4.

Similarly to the above, by using the latches 8 and 6 to adjust the fall timing of the strobe signal STB, the input pin 10b is connected to the terminal 1b of the circuit block 1.
The delay time D5 from the input pin 10b to the terminal 1c of the circuit block 1 is measured, and the delay time D2 from the terminal 1b to the terminal 1c of the circuit block 1 can be obtained.

As described above, the terminal 1a of the circuit block 1
Delay time D1 from terminal 1c to terminal 1c and terminal 1b to terminal 1
The delay time D2 up to c is obtained, and a large value of the two can be specified as the delay time of the circuit block 1 itself, and the timing of the circuit block 1 can be measured.

[0012]

As described above, in the conventional semiconductor integrated circuit, the delay time of the input signal from the input pin for inputting the input signal to the input terminal of the circuit block is determined by the delay time of the wiring for transmitting each input signal. Since it cannot be made uniform due to differences in wiring length, input capacitance, etc., it is necessary to measure the delay time for each input signal and find the delay time only for the circuit block, and the number of measurements increases. there were. In addition, it is necessary to provide a latch means for latching the input signal and an output terminal for outputting the latched signal for each input signal, so that high integration cannot be achieved. Further, there is a problem that the delay time of the circuit block cannot be specified with high accuracy due to variations in the characteristics of the wiring connecting each input terminal and each latch.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit which can easily and accurately specify a delay time of an arbitrary circuit block and is suitable for high integration. Aim.

[0014]

A holding means for holding and outputting an externally input signal in response to a first timing signal, an output signal of the holding means being input, and outputting a predetermined output signal A second timing signal and an output signal of the holding unit are input, and a predetermined first signal is output based on the output signal of the holding unit being input before the input of the second timing signal. One logical means;
Second logic means for receiving the third timing signal and the output signal of the circuit block, and outputting a predetermined second signal based on the input of the output signal of the circuit block before the input of the third timing signal; Including.

[0015]

The input signal input from the outside is temporarily input to the holding means, and is output to the circuit block in response to the first timing signal by the holding means. Therefore, the input signal is sent to the circuit block based on the first timing signal. Can be entered. Therefore, by measuring the time from the first timing signal to the second timing signal, the delay time from the output of the holding means to the input to the circuit block can be specified. By measuring the time until the signal, it is possible to specify the delay time from the output of the holding unit to the output of the circuit block. As a result, the time between the second timing signal and the third timing signal becomes the delay time of the circuit block, and the delay time of the circuit block can be specified.

[0016]

Next, a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention.

In FIG. 1, a semiconductor integrated circuit 20 includes a circuit block 1 for performing timing measurement, latches 2 and 3 for latching an external input signal, a latch 4 for latching an output signal of the circuit block 1, and a circuit block 1. , An input pin 10a, 10b for inputting an external input signal, and an input pin 1 for receiving a clock signal CLK for controlling the latch operation of the latches 2, 3.
1, an input pin 12 for inputting a strobe signal STB for controlling the latch operation of the latches 4 and 5, an output pin 13 for outputting the output signal of the latch 4, and an output pin 14 for outputting the output signal of the latch 5.

The input pins 10a and 10b are connected to the latches 2 and 3, respectively, and an input signal input from the outside via the input pins 10a and 10b is once input to the latches 2 and 3. The latches 2 and 3 are connected to the input pin 11 to which the clock signal CLK is input, and the clock signal CLK is “L”.
The input signal is latched at the timing of rising from "H" to "H", and the latched input signal is output to the terminals 1a and 1b of the circuit block 1 as output signals. At this time, since the same clock signal CLK is input to the latches 2 and 3, the latch operation is performed at the same timing, and the two input signals input via the input pins 10a and 10b are simultaneously input to the circuit block 1. Input can be made to terminals 1a and 1b. The terminal 1c of the circuit block 1 is connected to the latch 4. The circuit block 1 performs a predetermined operation when an input signal is input from the latches 2 and 3 to the terminals 1a and 1b, and outputs a predetermined output signal from the terminal 1c. , Latch 4
Output to Here, the circuit block 1 includes, for example, a ROM (Read
This is a predetermined cell such as a Only Memory (RAM) or a Random Access Memory (RAM). In order to simplify the description, an example of two inputs and one output is described. Latch 4 is connected to input pin 12 to which strobe signal STB is input, and latches an output signal output from terminal 1c of circuit block 1 at the timing when strobe signal STB falls from "H" to "L". The output signal thus output is output to the output pin 13. Latch 5 is connected to the output side of latch 2 and latch 2
Is output. The latch 5 is connected to the input pin 1
2 and, like the latch 4, the strobe signal ST
At the timing when B falls from “H” to “L”, the input signal is latched and output to the output pin 14. Here, the latch 5 is connected to the output side of the latch 2, but the latches 2 and 3 may output the output signal simultaneously at the rising timing of the clock signal CLK.

Next, a test system for performing timing measurement will be described. FIG. 2 is a diagram illustrating a configuration of a test system that performs timing measurement.

In FIG. 2, the test system includes a semiconductor integrated circuit 20 and a test apparatus 30. The test apparatus 30 outputs a predetermined input signal to the input pins 10a and 10b of the semiconductor integrated circuit 20. The test apparatus 30 includes the semiconductor integrated circuit 2
A clock signal CLK for controlling the latch operations of the 0 latches 2 and 3 is input to the input pin 11. As a result, the test apparatus 30 controls the timing of the clock signal CLK, and controls the timing at which the input signal is input to the circuit block 1. Output signals output from the output pins 13 and 14 of the semiconductor integrated circuit 20 are input to the test apparatus 30. The test apparatus 30 inputs a strobe signal STB for controlling the latch operation of the latches 4 and 5 of the semiconductor integrated circuit 20 to the input pin 12.
Enter As a result, the test apparatus 30 controls the timing of the strobe signal STB, and identifies the timing of the strobe signal STB from which a predetermined output is output by observing the state of the output signal output from the output pins 13 and 14. be able to.

Next, the operation of the semiconductor integrated circuit 20 will be described. FIG. 3 is a timing chart illustrating the operation of the semiconductor integrated circuit 20.

First, input signals a and b are input from input pins 10a and 10b, for example, rise from "L" to "H". The input signals a and b are delayed by different delay times due to differences in the wiring length and input capacitance of the connection lines connecting the latches 2 and 3 and the input pins 10a and 10b.
d is input to the latches 2 and 3, respectively. The latches 2 and 3 receive the clock signal C input from the input pin 11.
State before LK rises (here "L" state)
, The input signals c and d are not output from the latches 2 and 3. Next, when the clock signal CLK rises, the latches 2 and 3 latch the input signals c and d and output their states. Here, at the timing when the clock signal CLK rises, the input signals c and d are in the “H” state, so that the latches 2 and 3 output the output signals in the “H” state to the terminals 1 a and 1 b of the circuit block 1. Output at the same time. As a result, the input signals e and f rising from "L" to "H" are simultaneously input to the terminals 1a and 1b of the circuit block 1.
Therefore, the input signals a and b input from the input pins 10a and 10b are output to the circuit block 1 after being latched simultaneously at the rising timing of the clock signal CLK, even if the delay times to the latches 2 and 3 are different. Therefore, it is possible to simultaneously input a plurality of input signals to the circuit block 1. The circuit block 1 to which the input signals e and f have been input performs a predetermined operation, and outputs a predetermined output signal g to the latch 4 from the terminal 1c.

With the above operation, a plurality of input signals are simultaneously input to the circuit block 1, and a predetermined output signal can be output.

Next, a method for measuring the timing of the circuit block 1 to be measured will be described. As described above, since the input signals e and f are input to the input terminals 1a and 1b of the circuit block 1 at the same time, the circuit is specified by specifying from one input timing of the terminal 1a or 1b to the output timing of the terminal 1c. The delay time of block 1 can be obtained. Therefore, in the present embodiment, the delay time D8 from the rising time t0 of the clock signal CLK input to the latches 2 and 3 to the time t1 when the input signal is input to the terminal 1a of the circuit block 1 is input to the latch 2. Time t at which an output signal is output from terminal 1c of circuit block 1 from rising time t0 of clock signal CLK
By measuring the delay time D9 up to 2, and calculating the difference between the two, the delay time D7 of the circuit block 1 can be specified.

First, measurement of the delay time D8 from the rising time t0 of the clock signal CLK to the time t1 when the input signal is input to the terminal 1a of the circuit block 1 will be described. Input signals are input to the latches 2 and 3 from the input pins 10a and 10b, and the latches 2 and 3 latch the input signals c and d at the rising timing of the clock signal CLK, and input signals to the terminals 1a and 1b of the circuit block 1. e and f are input. At this time, the strobe signal STB1 input from the input pin 12 is input to the latch 5, and the latch 5 outputs the signal of the circuit block 1 output from the latch 2 at the timing when the strobe signal STB1 falls from "H" to "L". Terminal 1
Latch the input signal e to a and output the state of the input signal e to the output pin 14. While the strobe signal STB1 is swept near time t1, the timing at which the output signal output from the output terminal 14 changes from "L" to "H" is measured, and the timing is specified as time t1. As a result, the delay time D8 from the output of the latch 2 to the input to the circuit block 1 can be measured from the time from the rising time t0 of the clock signal CLK to the falling time t1 of the strobe signal STB1.

Next, the measurement of the delay time D9 from the rising time t0 of the clock signal CLK to the time t2 when the output signal is output from the terminal 1c of the circuit block 1 will be described. After the input signals c and d input from the input pins 10a and 10b are latched at the rising timing of the clock signal CLK and input to the terminals 1a and 1b of the circuit block 1, the circuit block 1 performs a predetermined operation and outputs an output signal. Output to the latch 4 from the terminal 1c. At this time, the strobe signal STB2 is input from the input terminal 12 to the latch 4, and the latch 4 latches the output signal output from the terminal 1c of the circuit block 1 and outputs it to the output pin 13. The strobe signal STB2 is swept near time t2, and the output signal of the latch 4 changes from “L” to “H” at time t2.
To identify. As a result, the delay time D9 from the rising time t0 of the clock signal CLK to the time t2 from when the output signal is output from the terminal 1c of the circuit block 1 can be measured.

The delay times D8 and D9 measured as described above
Is the delay time D7 of only the circuit block 1, and the delay time D7 of only the circuit block 1 can be specified.

As described above, in this embodiment, the inputted input signal is once inputted to the latches 2 and 3, and the clock signal CLK is inputted.
Can be simultaneously input to the circuit block in response to
By measuring the delay time from the rising timing of the clock signal CLK to the input of one input signal to the circuit block 1, the delay time of only the circuit block 1 can be measured. The number of time measurements is greatly reduced. Further, since the input timing to the circuit block 1 can be measured by using only one latch, it is less affected by variations in latch characteristics and the like and can be measured with high accuracy than when measuring by using a plurality of latches. Time can be measured. further,
Since the input timing is measured using one latch, only one output pin is required to output the measurement result to the outside, and the number of output pins can be reduced and high integration can be easily achieved.

In this embodiment, application to a circuit block having two inputs and one output has been described. However, the present invention can be similarly applied to circuit blocks having other inputs and outputs, and similar effects can be obtained.

[0030]

According to the semiconductor integrated circuit of the present invention, since the input signal input from the outside is temporarily held in response to the first timing signal and then output to the circuit block, there are a plurality of input signals. Even in this case, each input signal is simultaneously input to the circuit block, and the circuit block delay time can be specified by measuring the input timing of one of the plurality of input signals. Therefore, the delay time of an arbitrary circuit block can be measured with high accuracy and simply, and high integration can be easily achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a test system that performs timing measurement.

FIG. 3 is a timing chart illustrating the operation of the semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit block 2-5 Latch 10a, 10b, 11, 12 Input pin 13, 14 Output pin 20 Semiconductor integrated circuit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshio Mizokawa 4-61-5 Higashino, Itami-shi, Hyogo Mitsubishi Electric Engineering Co., Ltd. LSI Design Center (56) References JP-A-4-204274 ( JP, A) JP-A-57-130156 (JP, A) JP-A-64-23549 (JP, A) JP-A-63-142657 (JP, A) JP-A-63-16276 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/82 H01L 21/822

Claims (1)

(57) [Claims] 1. A holding unit for holding and outputting an input signal input from the outside in response to a first timing signal; and a circuit block receiving an output signal of the holding unit and outputting a predetermined output signal. A second timing signal and an output signal of the holding unit are input, and a predetermined first signal is output based on the output signal of the holding unit being input before the input of the second timing signal. 1 logic means, a third timing signal and an output signal of the circuit block are input, and a predetermined second signal is generated based on the output signal of the circuit block being input before the input of the third timing signal. And a second logic means for outputting.