JP3197061B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates, as a by-CMOS integrated circuit, a method of manufacturing a semiconductor equipment which a bipolar transistor and a MOS transistor are formed on the same substrate.

[0002]

2. Description of the Related Art A general configuration of a conventionally used bi-CMOS integrated circuit is shown in FIG. In a region on the P-type semiconductor substrate 1, a bipolar portion 101 in which a bipolar transistor is formed, and a CMOS in which a P-type MOS transistor and an N-type MOS transistor are formed.
The unit 102 is provided.

In the bipolar portion 101, an N-type epitaxial layer 3 is formed on a P-type semiconductor substrate 1, and this N-type epitaxial layer 3 is separated into regions for each element by a P-type element isolation layer 4. . N-type epitaxial layer 3
An N ⁺ -type buried layer 5 for reducing the collector resistance is provided at the boundary between the substrate 1 and the substrate 1. In a region near the surface of the epitaxial layer 3, a P-type active base layer 6 formed by impurity diffusion is formed. An N ⁺ -type emitter layer 7 formed by diffusing another impurity is formed in a region in the active base layer 6, and an emitter electrode 8 is formed in the emitter layer 7 through a contact hole 15. In contact. The region in the active base layer 6 further includes P ⁺
A mold external base layer 9 is formed. The external base layer 9 connects the active base layer 6 and the base electrode 10 with low resistance. 16 is a contact hole.

On the surface of the epitaxial layer 3 in a region outside the active base layer 6, a collector electrode extraction portion 11 made to be N ⁺ type by impurity diffusion is formed. The collector electrode extraction portion 11 has a contact hole. The collector electrode 12 is connected via 17. The collector electrode extraction section 11 is connected to the buried layer 5 via an N ⁺ type deep collector 13 for reducing the collector resistance.

[0005] The surface of the epitaxial layer 3 is covered and protected by an oxide film 14. The oxide film 14 also prevents a short circuit between the electrodes. Oxide film 14 is also used as a mask for ion implantation. Step 21 corresponds to an opening formed at the time of ion implantation for forming active base layer 6, and step 22 forms emitter layer 7. Corresponding to the opening formed during ion implantation for
The step 23 corresponds to an opening formed at the time of ion implantation for forming the collector electrode extraction portion 11.

On the other hand, in the CMOS section 102 separated from the bipolar section 101 by the P-type element isolation layer 4, the N-type epitaxial layers 103 A and P
A type epitaxial layer 103B is formed. At the boundary between the epitaxial layers 103A and 103B and the substrate 1,
Each has an N ⁺ type buried layer 105A and a P ⁺ type buried layer 105B.

On the surfaces of the epitaxial layers 103A and 103B, gate electrodes 106A and 106B are formed with oxide films 104A and 104B interposed therebetween. A P ⁺ -type source layer 107A and a P ⁺ -type drain layer 108A formed by diffusing impurities at a high concentration are formed in a region within the epitaxial layer 103A sandwiching the gate electrode 106A. In the region, a P-channel MOS transistor is formed.

Similarly, in the epitaxial layer 103B, an N ⁺ type source layer 107B and an N ⁺ type drain layer 108B are formed with the gate electrode 106B interposed therebetween.
An S-type transistor is formed. Oxide film 14 described above
Indicates that the epitaxial layer 1
The oxide film 14 also has an element isolation function of electrically isolating the active region on the surface from the surface such as 03A or 103B to a predetermined depth.

Source contact holes 109A and 109B and drain contact holes 110A and 110B are formed on the source layers 107A and 107B and the drain layers 108A and 108B, respectively. These contact holes 109A, 109B, 110A, and 110B have source layers 107A and 107B and drain layers 108A and 108A, respectively.
Metal electrodes 111 in ohmic contact with each other
A, 111B, 112A, 112B are formed.

[0010]

In the bipolar portion 101, the distance x between the steps 21 and 22 is different from that of the active base layer 6.
Are determined in consideration of the mask alignment allowance at the time of formation of the emitter layer 7 and the formation of the emitter layer 7. That is, the emitter layer 7
Since the emitter and the collector are short-circuited when they come into contact with the epitaxial layer 3, the emitter layer 7 must be surely formed in the internal region of the active base layer 6. Therefore, it is necessary to take the distance x in consideration of the mask alignment margin.

In order to prevent contact between the active base layer 6 and the emitter electrode 8, it is necessary to provide a distance y between the step 22 and the contact hole 15 in consideration of a mask alignment margin. Similarly, the active base layer 6 and the base electrode 1
In order to prevent direct contact with zero, a distance w is required in consideration of the mask alignment margin. On the other hand, if the emitter layer 7 and the external base layer 9 come into contact with each other, the withstand voltage deteriorates. However, this distance z is
Since it depends on the lateral extent of each of the diffusion layers constituting the emitter layer 7 and the external base layer 9, control is difficult. Therefore, the distance z has to be somewhat large.

Further, in the CMOS section 102, in order to prevent the metal electrodes 111A, 111B, 112A, 112B from directly contacting the epitaxial layers 103A, 103B, the source layers 107A, 107B and the drain layers 108A, 108B are formed. And contact holes 109A, 109B, 110A, 110B
Distances v1, v2, v3, and v4 are required to allow for a mask alignment margin with a mask for forming.

As described above, the distances x, y, w, z, and v1 to v4 in consideration of the margin for mask alignment and the like need to be sufficiently set, so that there is a problem that each element becomes large. When the element becomes large in this way, the cell area becomes large, which leads to an increase in the size of the integrated circuit and an obstacle to high integration. Moreover, as the size of the element increases, it becomes impossible to obtain good high-frequency characteristics.

Further, if the distance z between the emitter layer 7 and the external base layer 9 is too large, the base resistance rbb 'increases and the noise characteristics deteriorate. For this reason, the distance z needs to be adjusted to an optimum value. However, in the above-described configuration in which the distance z depends on the lateral spread of the diffusion layer, the intended element characteristics cannot always be obtained. There is.

Further, in the above configuration, metal wiring must be connected to the electrodes 8, 10, and 12 formed on the emitter layer 7, the external base layer 9, and the collector electrode extraction portion 11, respectively. Because the location is limited,
There is also a problem that the degree of freedom of wiring is small. This has also been an obstacle to miniaturization of the device. Therefore, an object of the present invention is to solve the above-mentioned technical problems, to reduce the size of the element and contribute to miniaturization and integration, and to reduce the base resistance without deteriorating the breakdown voltage. it is to provide a method for manufacturing equipment.

[0016]

SUMMARY OF THE INVENTION According to the present invention,
A semiconductor device manufactured by the method includes a bipolar portion in which a bipolar transistor is formed on the same substrate,
In a semiconductor device provided with a MOS portion on which an S-type transistor is formed, the bipolar portion protrudes by a predetermined height from a surface of a first semiconductor layer of a first conductivity type provided on the substrate. And an active base layer controlled to a second conductivity type different from the first conductivity type by impurity diffusion, and the first base provided on the active base layer.
And the second semiconductor layer formed in the first semiconductor layer surrounding the active base layer in a self-aligned manner with respect to the emitter layer and containing impurities at a higher concentration than the active base layer. An external base layer of the conductivity type, and a collector electrode extraction portion of the first conductivity type provided on a surface of the first semiconductor layer outside a region where the external base layer is formed. The third substrate provided on the substrate
A gate electrode formed by interposing an insulating film on the surface of the second semiconductor layer of the conductivity type described above, and by diffusing impurities into a region near the surface of the second semiconductor layer, Source and drain layers of a fourth conductivity type different from the third conductivity type formed in a self-aligned manner ;
A polycrystalline silicon formed to contact the emitter layer
Look including an emitter electrode made of Con film, the emitter layer
Is formed by impurity diffusion from the emitter electrode.
It is characterized in that it is .

According to the above configuration, in the bipolar portion, the active base layer and the emitter layer are laminated, so that the element formation region can be reduced. Further, since the external base layer is formed in a self-aligned manner with respect to the emitter layer, this can also contribute to the reduction of the element formation region. Further, since the active base layer is interposed between the emitter layer and the semiconductor layer, a short circuit between the emitter and the collector can be reliably prevented.

On the other hand, the emitter layer and the external base layer are separated from each other by an active base layer projecting from the semiconductor layer by a predetermined height.
It is formed so as to be shifted along the stacking direction of the emitter layer and the active base layer. Therefore, the emitter layer and the external base layer can be reliably separated from each other, and a sufficient withstand voltage can be obtained. Moreover, the so-called vertical distance between the emitter layer and the external base layer can be controlled with high precision by controlling the thickness of each of the emitter layer and the active base layer. Therefore, by sufficiently shortening the distance between the emitter layer and the external base layer, while having a sufficient withstand voltage,
Base resistance can be significantly reduced.

Further, in the MOS section, since the source / drain layers are formed in a self-aligned manner with respect to the gate electrode, the area of the MOS section is reduced .

Further , since the emitter layer is formed by diffusing impurities from the polycrystalline silicon film, the thickness of the emitter layer can be made sufficiently small. For this reason, a shallow junction can be formed, and the emitter injection efficiency can be increased, thereby improving high-frequency characteristics.
According to the first aspect of the present invention, a bipolar transistor is provided on the same substrate.
A bipolar part in which a transistor is formed, and a MOS type transistor.
And a MOS section in which a transistor is formed.
A method of manufacturing a bipolar device, wherein
Forming a conductive-type first semiconductor layer;
Impurities are diffused at a low concentration into predetermined regions on the surface of the semiconductor layer.
The vicinity of the surface of the first semiconductor layer in the predetermined region is defined as the first conductive layer.
Controlling the second conductivity type different from the first conductivity type;
Step of forming second semiconductor layer of third conductivity type in OS section
Forming a first insulating film on the surface of the second semiconductor layer.
And an impurity for controlling the first conductivity type.
Forming a first polycrystalline silicon film including the entire surface,
The first polycrystalline silicon film and the first insulating film are anisotropically
The first semiconductor is patterned by reactive etching.
From the first polycrystalline silicon film to the predetermined region on the layer
An emitter electrode is formed on the second semiconductor layer.
Forming a gate electrode made of a first polycrystalline silicon film;
And at the same time,
The first semiconductor layer in the constant region is connected to the emitter electrode.
To a predetermined depth in a self-aligned manner.
And a protrusion protruding from the surface of the first semiconductor layer after etching.
Forming a portion under the emitter electrode;
By diffusing the impurities in the
Controlling the conductivity type near the surface to the first conductivity type,
As the emitter layer and the lower part of the emitter layer
Using the second conductivity type portion as an active base layer;
The second conductive layer is provided in the predetermined region of the first semiconductor layer.
By diffusing the impurity for controlling the mold to a high concentration
External base layer in a self-aligned manner with respect to the emitter layer.
Forming the first region and the predetermined region of the first semiconductor layer
The impurity is diffused to a high concentration near the outer surface, and the first
Forming a conductive type collector electrode extraction portion;
Impurities are diffused in high concentration near the surface of the second semiconductor layer
As a result, the source is self-aligned with the gate electrode.
Forming a source layer and a drain layer.
This is a method of manufacturing a semiconductor device. Like this
Then, the first polycrystalline silicon film is
The semiconductor device with the above configuration is manufactured using the same
Is done. In this case, it protrudes from the surface of the first semiconductor layer.
The height of the protrusion and the height of the emitter formed near the top surface of this protrusion
By controlling the thickness of the emitter layer and the external base,
The distance between the layers can be controlled. From polycrystalline silicon film
The depth direction control well in the diffusion of impurities?
Thus, the thickness of the emitter layer can be controlled well. Also,
Since the depth of the chin can be controlled accurately,
The distance between the data layer and the external base layer can be controlled with high precision.
You. Further, in the present invention, the first polycrystalline silicon film
And anisotropic etching for patterning the first insulating film
At the time of this patterning.
The first semiconductor layer is simultaneously etched to form the protrusion.
We are going to make it. In this method, the second portion of the MOS section
That the first semiconductor layer is covered with the first insulating film.
And the first insulating film and the first half in the anisotropic etching.
Using the difference in the selectivity with the conductor layer, the first
Patterning the polycrystalline silicon film and the first insulating film,
And the formation of parts. This simplifies the manufacturing process
The semiconductor device is of has a source electrode comprising a base electrode comprising a polycrystalline silicon film formed in contact with the external base layer, a polycrystalline silicon film formed in contact with the source layer A drain electrode including a polycrystalline silicon film formed so as to be in contact with the drain layer, wherein the external base layer is formed by impurity diffusion from the base electrode, and the source layer is And the drain electrode is preferably formed by diffusing impurities from the drain electrode. The drain electrode is preferably formed by diffusing impurities from the drain electrode.

In this configuration, a polycrystalline silicon film used for forming an external base layer, a source layer, and a drain layer is used as an electrode. For this reason, it is not necessary to form a special contact hole in order to form an electrode in contact with each impurity diffusion layer, so that a mask alignment margin between the contact hole and the impurity diffusion becomes unnecessary. For this reason, the element formation region can be further reduced.

Furthermore, since the polycrystalline silicon film is in contact with each diffusion layer, there is no occurrence of an ohmic defect such as a spike or a nodule unlike the case where a metal electrode is used. The semiconductor device having the above-described configuration is configured as described in claim 2.
As described above, the step of forming the external base layer includes the first step.
Contacts the area around the emitter layer on the surface of the semiconductor layer
At the same time, impurities for controlling the first conductivity type are increased.
Forming a second polycrystalline silicon film containing the concentration;
Impurities in the second polycrystalline silicon film are removed from the first half.
Diffusing into the conductor layer.
Forming the drain and drain layers,
In each area where the source and drain layers on the surface are to be formed
Contact and control for the fourth conductivity type.
Forming a third polycrystalline silicon film containing a pure substance at a high concentration;
And the step of removing impurities in the third polycrystalline silicon film
Diffusing into the second semiconductor layer.
According to the invention of the method for manufacturing a semiconductor device according to claim 1,
Can be manufactured. Further, the invention according to claim 3 is characterized in that
Forming the second polycrystalline silicon film and the third
The step of forming a polycrystalline silicon film is performed by using one polycrystalline silicon film.
Forming a silicon film on the entire surface,
In the membrane, the part of the bipolar part can be selectively
A step of adding an impurity for controlling the first conductivity type;
In the above-mentioned one polycrystalline silicon film, the MO
The portion of the S portion is selectively controlled to the fourth conductivity type.
And a step of adding impurities for
A method for manufacturing a semiconductor device according to claim 2. using this method
Individually controls the conductivity type of each part of one polycrystalline silicon film.
Controlling the second and third polycrystalline silicon
Have gained. As a result, the polycrystalline silicon
The manufacturing process can be simplified as compared with the case where a capacitor film is formed. Up
Serial semiconductor device, the base electrode, a source electrode and a drain electrode, and the polycrystalline silicon film, it is preferably composed of a laminated film of a silicide film is laminated on the polysilicon film.

In this way, since the laminated film of the polycrystalline silicon film and the silicide film can have a sufficiently low resistance, this laminated film can be used as it is as a good electrode. The semiconductor device having the configuration described above
As described in 4, the second polycrystalline silicon film and
Form silicide film covering third polycrystalline silicon film
Performing the second polycrystalline silicon film and the silicon
The laminated film with the id film is in contact with the external base layer.
Patterning, leaving the part
Using the layer film as a base electrode and the third polycrystalline silicon
The laminated film of the silicon film and the silicide film is
And leave the part in contact with the drain layer
The laminated film after patterning and patterning is used as a source electrode and
And forming a drain electrode.
A method for manufacturing a semiconductor device according to claim 2 or 3, wherein
Can be manufactured by Ming. The semiconductor device includes a first side spacer made of an insulating material and attached to a sidewall of a structure including the emitter layer and the active base layer protruding from a surface of the first semiconductor layer; A second side spacer made of an insulating material adhered to a side wall of a gate structure including the gate electrode protruding from a layer surface, wherein the external base layer is provided with respect to the first side spacer. It is formed in a self-aligned manner,
The source layer and the drain layer are preferably formed in a self-aligned manner with respect to the second side spacer.
New

In this configuration, the function of the first side spacer prevents the external base layer from being formed so as to extend to a position immediately below the emitter layer. Therefore, the contact between the external base layer and the emitter layer is further improved. It is surely prevented. Also,
The spacing between the gate electrode and the source / drain electrode can be accurately controlled by the function of the second side spacer, so that punch-through can be effectively prevented.

Further, since the first and second side spacers are both made of an insulating material, the base electrode and the source / drain electrodes are formed with the side spacers interposed therebetween, so that the emitter and the emitter can be formed. Each short circuit between the base, between the gate and the source, and between the gate and the drain can be prevented. The semiconductor device having the above configuration is
Item 6. A step of forming the external base layer as described in Item 6.
Forming a third insulating film on the entire surface before
3 is etched back to form the first semiconductor
The emitter layer and the active base layer protruding from the layer surface
A first side spacer attached to a side wall of the structure including:
And the gate electrode protruding from the second semiconductor layer.
A second side deposited on the sidewall of the gate structure including the pole
Forming a pacer.
A method of manufacturing the semiconductor device according to claim 1.
It can be manufactured by a method. In this case, the first
The second side spacer and the second side spacer can be formed in the same step.
Further, in the semiconductor device, in the bipolar portion,
It is preferable that an insulating film is further formed on the emitter layer, on the collector electrode take-out portion, and on the surface of the first semiconductor layer outside the formation region of the external base layer.

According to this structure, the base electrode formed to be in contact with the external base layer is insulated from the emitter and the collector by the insulating film. Therefore, the base electrode can be freely routed, and the connection position between the base electrode and the metal wiring can be arbitrarily arranged. As a result, the degree of freedom of wiring increases. If the first side spacer is formed, the first side spacer also contributes to insulation between the base electrode and the emitter.

The semiconductor device having the above configuration is described in claim 5.
As described above, a process for forming the second polycrystalline silicon film is performed.
Before the process, the upper part of the emitter layer and the collector electrode
On the top of the protrusion and outside the area where the external base layer is formed
A second insulating film is formed on the surface of the first semiconductor layer.
4. The method according to claim 2, further comprising the step of:
Or 4) according to the invention of the method of manufacturing a semiconductor device described in 4.
Can be built. The base is formed on the formed second insulating film.
Wiring flexibility is increased by routing the electrodes
Is as described above. 8. A method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is provided with a bipolar portion on which a bipolar transistor is formed and a MOS portion on which a MOS transistor is formed on the same substrate. Forming a first semiconductor layer of a first conductivity type in the bipolar portion; and diffusing an impurity at a low concentration into a predetermined region on the surface of the first semiconductor layer to form a first semiconductor layer in the predetermined region. Controlling the vicinity of the surface of the semiconductor device to a second conductivity type different from the first conductivity type, forming a second semiconductor layer of a third conductivity type in the MOS portion, Forming a first insulating film on the surface of the layer;
Forming a first polycrystalline silicon film including an impurity for controlling the first conductivity type over the entire surface, and patterning the first polycrystalline silicon film and the first insulating film to form the first polycrystalline silicon film and the first insulating film; Forming an emitter electrode made of the first polycrystalline silicon film in the predetermined region on one semiconductor layer, and forming a gate electrode made of the first polycrystalline silicon film on the second semiconductor layer; The first region of the predetermined area
Forming a protrusion protruding from the etched first semiconductor layer surface below the emitter electrode by etching the semiconductor layer to a predetermined depth in a self-aligned manner with respect to the emitter electrode; By diffusing impurities in the emitter electrode, the conductivity type near the top surface of the projection is controlled to the first conductivity type, and this portion is used as an emitter layer, and the second conductivity type portion below the emitter layer is formed. Forming a conductive type portion as an active base layer; and diffusing an impurity for controlling the second conductive type into the predetermined region of the first semiconductor layer at a high concentration. Forming an external base layer in a self-aligned manner, and diffusing impurities at a high concentration in the vicinity of the surface of the first semiconductor layer outside the predetermined region, so as to extract the first conductive type collector electrode. The shape A step of, by diffusing an impurity in a high concentration near the surface of the second semiconductor layer, seen including a step of forming a self-aligned manner source layer and the drain layer to said gate electrode, furthermore, Above external ba
Forming a third insulating film on the entire surface before the step of forming a semiconductor layer
And etching back the third insulating film.
The emitter protruding from the surface of the first semiconductor layer
Layer on the side wall of the structure including the layer and the active base layer.
From the first side spacer and the second semiconductor layer
Cover the side wall of the gate structure including the protruding gate electrode.
Forming the attached second side spacer .

[0028]

[0029]

[0030]

The invention according to claim 8 is that, in the step of forming the external base layer, the step of contacting the region around the emitter layer on the surface of the first semiconductor layer and controlling the surface to the first conductivity type. Forming a second polycrystalline silicon film containing impurities at a high concentration, and diffusing impurities in the second polycrystalline silicon film into the first semiconductor layer. Forming the drain layer and the source and drain regions on the surface of the second semiconductor layer.
Forming a third polycrystalline silicon film containing a high concentration of impurities for controlling to a conductivity type of, and diffusing impurities in the third polycrystalline silicon film into the second semiconductor layer 8. The semiconductor according to claim 7 , comprising:
It is a manufacturing method of a body device .

[0032] Claim9StatedinventionIs the second polycrystalline
Forming a silicon film and forming the third polycrystalline silicon
In the step of forming a capacitor film, one polysilicon film is entirely
And forming a polycrystalline silicon film on the surface.
And the first portion is selectively connected to the bipolar portion.
A step of adding an impurity for controlling the conductivity type;
In one polycrystalline silicon film, the above MOS portion
And an impurity for selectively controlling the fourth conductivity type.
And a step of addingClaim 8
Semiconductor device manufacturing method.

[0033] Claim10StatedinventionIs the second polymorphism
The polycrystalline silicon film and the third polycrystalline silicon film
Forming a silicide film; and forming the second polycrystalline silicide
The laminated film of the capacitor film and the silicide film is
Pattern, leaving the part in contact with the
Using the laminated film as a base electrode after cleaning.
Lamination of the third polycrystalline silicon film and the silicide film
The film is placed in a portion in contact with the source layer and the drain layer.
Patterning, leaving the layer
A step of using the film as a source electrode and a drain electrode.
Is characterized by includingA semiconductor according to claim 8 or 9.
Device manufacturing method.

[0034] Claim11StatedinventionIs the second polymorphism
Before the step of forming a polycrystalline silicon film, the emitter
Above the layer, above the collector electrode outlet and above
On the surface of the first semiconductor layer outside the formation region of the base layer,
Each further including a step of forming a second insulating film.
Characterized by11. The semiconductor device according to claim 8, 9 or 10.
Manufacturing method.

[0035]

[0036]

[0037]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing a configuration of a bi-CMOS integrated circuit which is an embodiment of the semiconductor device of the present invention. On a P-type semiconductor substrate 30, a bipolar portion 201, which is a region where a bipolar transistor is formed,
CMOS part 2 which is a region where an OS transistor is formed
02 is provided.

In the bipolar portion 201, an N ⁺ type buried layer 31 for reducing collector resistance is formed on a P type semiconductor substrate 30, and an N type epitaxial layer 32 constituting a first semiconductor layer is further formed. Is formed.
The element formation region is separated from other element formation regions by a P-type separation layer 33. In the element formation region,
The epitaxial layer 32 other than the region where the active region is to be formed
An oxide film 34 obtained by selectively thermally oxidizing the surface of the epitaxial layer 32 is formed on the surface of.

Some regions of the epitaxial layer 32 are partially
Etched by a constant depth ΔD (0.3-0.4 μm)
The surface of the epitaxial layer 32 after this etching
A projection 54 projecting from the surface by a height ΔD is formed.
You. Formed near the surface of the projection 54 by impurity diffusion
N⁺Type emitter layer 36 is provided.
The lower portion of the cutter layer 36 is an active base layer 35. D
On the mitter layer 36, N ⁺Type polycrystalline silicon film
The formed emitter electrode 37 is formed.

On the surface of the emitter electrode 37, a silicon oxide film 38 is formed by lamination. This silicon oxide film 3
8, a first side spacer 40 made of a silicon oxide film is adhered to a side of a structure 39 composed of an emitter electrode 37, an emitter layer 36, and an active base layer 35 and protruding from the surface of the epitaxial layer 32. I have. In the vicinity of the surface of the epitaxial layer 32 around the active base layer 35, an external base layer 41 in which impurities are diffused at a high concentration is self-aligned with the emitter layer 36 (more precisely, self-aligned with the side spacer 40). ) Is formed. The tungsten silicide (WSi ₂ ) film 421 and the polycrystalline silicon film 422 are in contact with the external base layer 41.
And a base electrode 42 made of a laminated film of the above.

On the other hand, on the surface of the epitaxial layer 32 outside the region where the external base layer 41 is formed, an N ⁺ -type collector electrode extraction portion 43 formed by impurity diffusion is provided. A collector electrode 44 made of an N ⁺ -type polycrystalline silicon film is in contact with the surface of the collector electrode extraction portion 43, and a silicon oxide film 4 is formed on the collector electrode 44.
5 are formed. Also, the collector electrode take-out part 43
Are connected to the N ⁺ -type buried layer 31 via the N ⁺ -type deep collector 46, thereby reducing the collector resistance.

On the other hand, in the CMOS section 202, an N-type epitaxial layer 73A and a P-type well 73B are formed on the P-type semiconductor substrate 1. At the boundary between the epitaxial layer 73A and the substrate 1, an N ⁺ type buried layer 75A is provided. Epitaxial layer 73A and P-type well 73
B corresponds to the second semiconductor layer. Gate electrodes 76A and 76B are formed on the surfaces of the epitaxial layer 73A and the P-type well 73B with the gate oxide films 74A and 74B interposed therebetween. This gate electrode 76
A and 76B are made of a polycrystalline silicon film whose resistance is reduced by adding phosphorus.

On the gate electrodes 76A and 76B, silicon oxide films 85A and 85B are stacked. Oxide film 74
A, 74B, gate electrodes 86A, 76B and gate structures 86A, 8 composed of silicon oxide films 85A, 85B.
The second side spacers 87A and 87B are attached to the side wall of 6B. In a region within the epitaxial layer 73A sandwiching the gate electrode 76A, a P ⁺ -type source layer 77A and a P ⁺ -type drain layer 78A formed by diffusing impurities at a high concentration are self-aligned with respect to the gate electrode 76A ( To be precise, it is formed (self-aligned with the side spacer 87A). Thus, a P-channel MOS transistor is formed in the region of the epitaxial layer 73A.

Similarly, in the P-type well 73B, the N ⁺ -type source layer 77B and the N ⁺ -type drain layer 78B are self-aligned with the gate electrode 76B (more precisely, with respect to the side spacer 87B) with the gate electrode 76B interposed therebetween. In the region of the P-type well 73B, an N-channel type MOS transistor is formed.

A low concentration impurity diffusion region is formed in a portion of the source layer 77B and the drain layer 78B which faces the channel region immediately below the gate electrode 76B, and has a so-called LDD (Lightly Doped Drain) structure. As a result, the change in the impurity concentration between the channel region and the source layer 77B and the drain layer 78B becomes slow, so that the withstand voltage in this portion is improved and punch-through can be prevented well.

The above-described oxide film 34 is also formed in the CMOS portion 202, and penetrates to a predetermined depth from the surfaces of the epitaxial layer 73A and the P-type well 73B to achieve isolation between elements. Source layers 77A, 7
The source electrode 81A, 81B and the drain electrode 82A,
82B are formed. These electrodes 81A, 81
B, 82A, 82B are the source / drain layers 77A, 7B.
Polycrystalline silicon film 81 in contact with 7B, 78A, 78B
1A, 811B, 821A, 821B and a tungsten silicide film 812A, 812B, 822A, 822B.

In the configuration of the present embodiment as described above, since the emitter layer 43 and the active base layer 35 are laminated in the bipolar portion 201, when the semiconductor substrate 30 is viewed in a plan view, the element of the bipolar portion 201 The area of the formation region is significantly reduced as compared with the related art. In addition, the emitter layer 43 and the epitaxial layer 32 are
5, there is no danger of short circuit between the emitter and collector.

On the other hand, the etching depth ΔD and the layer thickness ΔDe (for example, 0.2 μm) of the emitter layer 36 are:
The distance between the emitter layer 36 and the external base layer 41 is defined. The etching depth ΔD can be accurately controlled by appropriately selecting the etching conditions, and the control of the layer thickness ΔDe can also be performed with high accuracy by controlling the impurity diffusion depth. Therefore, the distance between the emitter layer 36 and the external base layer 41 can be controlled with good accuracy. As a result, the emitter layer 36 and the external base layer 41 are reliably separated from each other and a sufficient withstand voltage is obtained, while the distance between the emitter layer 36 and the external base layer 41 is sufficiently reduced to reduce the base resistance rbb '. Thereby, noise characteristics are improved.

Further, in this embodiment, the emitter electrode 37
And collector electrode 43 are formed of a polycrystalline silicon film.
A, 81B and drain electrodes 82A, 82B are formed on the external base layer 41 and the source / drain layers 77A, 77B, 78.
The lower layer film in contact with A, 78B is formed of a polysilicon film. Therefore, there is an advantage that ohmic defects such as spikes and nodules do not occur as in the case of using a metal electrode.

In the bipolar portion 201, the base electrode 42 can be electrically connected only to the external base layer 41, and the side spacer 40, the silicon oxide films 38 and 45, and the oxide film 34 All parts other than the layer 41 are electrically insulated. For this reason, the base electrode 42 can be freely routed on the substrate to some extent.
Can be freely arranged on the substrate. As a result, the degree of freedom of wiring can be remarkably increased, and high-density wiring can be realized, which can contribute to miniaturization of an integrated circuit.

Further, in the CMOS section 202, the source
The drain layers 77A, 77B, 78A, 78B are formed in a self-aligned manner by using the side spacers 87A, 87B attached to the sides of the gate structures 86A, 86B and the oxide film 34 as a mask. For this reason, there is no need for a margin for mask alignment as in the related art.
In this case, the element area can be reduced.

Further, since the side spacers 87A and 87B are provided, the channel region immediately below the gate electrodes 76A and 76B and the source / drain layers 77A, 77B and 78 are provided.
Since it is possible to reliably control the distance between A and 78B, there is an advantage that punch-through can be prevented. The side spacers 87A and 87B also prevent short circuits between the gate and the source and between the gate and the drain. 2, 3, 4 and 5 are cross-sectional views showing a method for manufacturing the above-mentioned bi-CMOS integrated circuit in the order of steps. First, as shown in FIG. 2A, an N ⁺ buried layer 31 and an N ⁺ type 75A are formed on a P type semiconductor substrate 30, and an N type epitaxial layer 32,
An N-type epitaxial layer 73A is grown. The P-type well 73 is formed in the N-type epitaxial layer formed thereafter.
B is formed. At this time, the impurity concentration on the surface of the P-type well 73B is equal to the threshold voltage required for the N-channel MOS transistor (eg, 1
It is adjusted to a value corresponding to V).

Thereafter, the LOs for selectively thermally oxidizing the surfaces of the epitaxial layers 32 and 73A and the P-type well 73B are formed.
The oxide film 34 is formed by the COS (LOCal Oxidation of Silicon) method. From this state, the external base layer 41
In the region 55 for forming the P-type active base layer 3
Impurity ions are implanted at a concentration required for 5 (for example, 1 × 10 ¹⁸ cm ⁻³ ).

Next, after a thin oxide film (not shown) is grown on the entire surface, ions are implanted into the surface of the N-type epitaxial layer 73A in order to adjust the threshold voltage of the P-channel MOS transistor. . Thereafter, the thin oxide film is removed, and as shown in FIG.
Oxide film 56 as a first insulating film corresponding to 4A, 74B
Is formed, and portions other than the regions on the epitaxial layer 73A and the P-type well 73B of the CMOS section 202 are removed. From this state, a first polycrystalline silicon film 57 is formed on the entire surface, and phosphorus is diffused into the first polycrystalline silicon film 57. Thus, a low-resistance polycrystalline silicon film 57 is obtained.

Oxide films 38 and 85 of FIG. 1 are formed on polycrystalline silicon film 57 by CVD (chemical vapor deposition).
A silicon oxide film 58 corresponding to A and 85B is formed, and the state shown in FIG. This silicon oxide film 5
8 corresponds to a second insulating film. From this state, FIG.
As shown in (c), the oxide film 5 is formed by anisotropic etching such as RIE (reactive ion etching).
6. The polycrystalline silicon film 57 and the silicon oxide film 58 are etched to form a structure 39 in the bipolar portion 201 and a gate structure 86 in the CMOS portion 202.
A, 86B and the like are formed.

At this time, since oxide film 56 is not formed on the surface of epitaxial layer 32 of bipolar portion 201, the surface of epitaxial layer 32 has a depth ΔD (for example, about 0.3 μm; see FIG. 1). It is etched away. That is, since the selectivity between silicon and the silicon oxide film in the anisotropic etching is 10 or more, the epitaxial layer 32 is etched to a relatively large depth while the oxide film 56 is removed by etching.
In this manner, the protrusions 54 projecting from the etched surface by the height ΔD are formed in the epitaxial layer 32.

Next, as shown in FIG.
Phosphorus ions are implanted at a low concentration only in the region 73B,
This makes the gate structure 86B self-aligned.
And N ^-Formed impurity diffusion layer 59 is formed. Furthermore, the figure
As shown by the imaginary line in FIG.
Silicon oxide not containing impurities as a third insulating film on the entire surface
A film 60 is deposited. Then, heat treatment is performed,
It is obtained by patterning the first polycrystalline silicon film 57.
Phosphorus in the emitter electrode 37 and the collector electrode 44
It is diffused into the epitaxial layer 32. This allows
N near the top surface of the projection 54⁺Type emitter layer 36 is formed.
The lower portion of the emitter layer 36 becomes the active base layer 35.
You. In addition, under the collector electrode 44, N⁺Type collection
The electrode extraction portion 43 is formed.

Thereafter, the silicon oxide film 60 is etched back by anisotropic etching, whereby the first side spacer 40 attached to the side wall of the structure 39 of the bipolar portion 201 and the gate structure in the CMOS portion 202 are formed. Second side spacers 87A and 87B are formed on the side walls of the bodies 86A and 86B. Thus, the first and second side spacers 40, 87A, 8
7B are formed in the same step.

Next, as shown in FIG. 4E, a polycrystalline silicon film 61 is deposited on the entire surface. Then, a mask is applied to the polycrystalline silicon film 61 so as to cover a region other than the P-type well 73B where the N-channel MOS transistor is to be formed, and arsenic ions or phosphorus ions are implanted at a high concentration. . As a result, arsenic or phosphorus as an N-type dopant is added to the region 612 of the polycrystalline silicon film 61.

Similarly, bipolar unit 201 and N
Regions 611 and 613 in the portion of the type epitaxial layer 73A
The polycrystalline silicon film 61 is doped with boron as a P-type dopant. As described above, the polycrystalline silicon film 61 in the region 611 corresponds to the second polycrystalline silicon film, and the polycrystalline silicon films 61 in the regions 612 and 613 correspond to the third polycrystalline silicon film.

Although a polycrystalline silicon film containing necessary impurities may be individually formed in each of the regions 611, 612, and 613, such a method is required unless the polycrystalline silicon film is formed a plurality of times. Therefore, it is preferable to apply the above-described method of selectively adding an impurity to each region of one polycrystalline silicon film 61. Next, FIG.
As shown in FIG. 7, a tungsten silicide film 62 is deposited on a polycrystalline silicon film 61 by, for example, a sputtering method. Since the laminated film of the tungsten silicide film 62 and the polycrystalline silicon film 61 has a sufficiently low resistance value (about one-tenth that of the polycrystalline silicon film 61 alone), this laminated film The electrode can be used as it is.

Next, a resist is applied to the entire surface, etched back, and flattened to obtain a state shown in FIG. 5 (g). 63 is a resist. In the state shown in FIG. 5G, the upper portions of the structure 39 of the bipolar portion 201 and the gate structures 86A and 86 in the CMOS portion 202 are formed.
The polycrystalline silicon film 61 and the tungsten silicide film 62 above B are removed.

From this state, as shown in FIG. 5H, the resist 63 is removed, and the polycrystalline silicon film 61 and the tungsten silicide film 62 are patterned to form the base electrode 42, the source electrodes 81A and 81B, and the drain electrode. 82A and 82B are formed. Thereafter, an interlayer insulating film 64 made of phosphorus glass or the like to which boron is added (FIG. 1)
The illustration is omitted in FIG. ) Is formed. afterwards,
Heat treatment is performed, and the base electrode 42, the source electrode 81A,
81B and polycrystalline silicon films 421, 811A, 811B, 8 which are lower layers of the drain electrodes 82A, 82B.
Impurities in 21A and 821B (see FIG. 1) are diffused into epitaxial layers 32 and 73A and P-type well 73B.

Thus, the external base layer 41 is formed in a self-aligned manner with respect to the emitter layer 36, and the gate electrode 76 is formed.
A and 77B in a self-aligned manner with respect to the source layers 77A and 77B.
B and the drain layers 78A and 78B are formed. It should be noted that boron in the polycrystalline silicon film 42B is diffused into the epitaxial layer 32 to form the P ^{+ type} external base layer 41.
When boron is formed, the lateral diffusion spread of boron depends on the width of the side spacer 40 (for example, 2000 to 3000).
Ii) It is preferable to control so as to be approximately. This is to prevent contact between the P-type external base layer 41 and the emitter layer 36. When diffusing impurities, the diffusion speed in the lateral direction is about half of the diffusion speed in the depth direction of the substrate. Therefore, by controlling the diffusion depth, the diffusion of the diffusion layer in the lateral direction can be controlled.

5H, a contact hole (not shown) is further opened in the interlayer insulating film 64, and the base electrode 42, the emitter electrode 37, the collector electrode 44, and the source electrode 81A are formed through the contact holes. , 81B and drain electrodes 82A, 82B are formed respectively. Thus, an NPN transistor is formed in the bipolar unit 201, and the CMOS
In the S section 202, an N-channel MOS transistor and a P-channel MOS transistor are formed.

In the above manufacturing method, the bipolar part 201
In this case, the external base layer 41 is formed in a self-aligned manner with respect to the emitter layer 36 and the like.
A, 76B in a self-aligned manner with the source layers 81A, 81B.
B and drain layers 82A and 82B are formed. Therefore, the element can be manufactured by a simple manufacturing process.
Specifically, the number of masks can be reduced.

The operation of the side spacer 40 and the like allows the base electrode 42 and the emitter layer 36 to be insulated from each other without any special process such as opening a contact hole. External base layer 41
You can get in contact with. Similarly, the source / drain electrodes 81A, 81A are formed by the side spacers 87A, 87B.
81B, 82A, 82B and the gate electrodes 76A, 76B are insulated from each other and the source / drain layers 77
Contact with A, 77B, 78A, 78B is obtained. This also simplifies the manufacturing process.

Further, a tungsten silicide film 422 is laminated on a polycrystalline silicon film 421 containing impurities for forming the external base layer 35 to form a low-resistance laminated film, and this laminated film is used as the base electrode 42. . That is, the polycrystalline silicon film 42A used for forming the external base layer 35 is used as a part of the base electrode 42. Source / drain electrodes 81A, 81B, 82A, 8
The same applies to 2B. This also simplifies the manufacturing process.

Further, in the above-described electrode forming method, since there is no possibility that the positions of the respective electrodes and the impurity diffusion layers are shifted, a mask for forming the source / drain layers and a contact hole are formed as in the prior art. There is no need to consider the margin for ask alignment with the mask for this purpose. Thus, in both the bipolar unit 201 and the CMOS unit 202, the element area can be reduced.

As can be seen from FIG. 4E, the surface of the bipolar portion 201 before the formation of the polycrystalline silicon film 61 as the lower layer film of the base electrode 42 has a region where the external base layer 41 is to be formed. Except for insulating films (oxide films 34, 38, 4)
5 and side spacers 40). For this reason, the base electrode 42 can be freely routed on the substrate to some extent, whereby a contact hole for wiring connection can be arranged at an arbitrary position. As a result, the degree of freedom of wiring is significantly increased. As a result, the wiring can be formed at a high density, which can contribute to downsizing of the device.

Further, as shown in FIGS. 3C and 3D, the emitter layer 36 is
An emitter electrode 37 made of a polycrystalline silicon film doped with phosphorus is laminated on the convex portion 54 protruding from the surface of the second electrode 2, and the phosphor in the emitter electrode 37 is diffused near the top surface of the convex portion 54. . In this forming method, the emitter layer 3
6 can be formed thinly to form a shallow junction, so that the emitter injection efficiency is increased and the high frequency characteristics are significantly improved.

As shown in FIGS. 2B and 3C, an oxide film 56 is formed in the MOS portion 202, and a similar oxide film is formed in the bipolar portion 201. Utilizing the fact that the gate structures 86A, 86
The formation of B and the convex portion 34 are performed in the same step. This simplifies the manufacturing process. The description of the embodiments of the present invention is as described above, but the present invention is not limited to the above embodiments. For example, in the above manufacturing method, the external base layer 41 is formed by thermal diffusion from the boron-doped polycrystalline silicon film 421.
For example, the P-type external base layer 41 may be formed by performing ion implantation after forming a polycrystalline silicon film to which no impurity is added.

In the above embodiment, the base electrode 42
Although the tungsten silicide film 42A is used as the silicide film constituting the above, a molybdenum silicide film, a titanium silicide film, or the like can be applied to the silicide film. Further, in the above embodiment, the case where the NPN transistor is formed in the bipolar unit 201 has been described as an example. It can be easily applied to other cases. Specifically, in the region where the PNP transistor is formed, the emitter electrode 37
As the external base layer 41, a polycrystalline silicon film to which boron is added is used instead of the polycrystalline silicon film to which phosphorus is added.
May be used instead of the boron-added polysilicon film for forming the silicon film.

In the above embodiment, a bi-CMOS integrated circuit in which both an N-channel MOS transistor and a P-channel MOS transistor are formed together with a bipolar transistor on the same substrate is taken as an example. The invention can be applied to a semiconductor device such as another integrated circuit in which only an N-channel type or P-channel type MOS transistor is formed on the same substrate together with a bipolar transistor.

In addition, various changes can be made without changing the gist of the present invention.

[0076]

As described above, according to the present invention, in the bipolar portion, the active base layer and the emitter layer are laminated, and the external base layer is formed in a self-aligned manner with respect to the emitter layer. Therefore, the element area can be significantly reduced. Further, since the source / drain layers are formed in the MOS portion in a self-aligned manner with respect to the gate electrode, the size of the MOS portion can be reduced. As a result, high integration can be achieved in a semiconductor integrated circuit or the like.

On the other hand, the emitter layer and the external base layer are surely separated from each other in the stacking direction. In addition, since the thickness of each layer in the stacking direction can be controlled with high precision, the distance between the emitter layer and the external base layer is made sufficiently short so that the base resistance is significantly increased while having a sufficient withstand voltage. Can be reduced. As a result, noise characteristics can be significantly improved.

In the bipolar portion, the first side spacer is attached to the side wall of the structure protruding from the surface of the semiconductor layer including the active base layer and the emitter layer, so that the contact between the external base layer and the emitter layer is achieved. Can be more reliably prevented. Further, in the MOS portion, if a second side spacer is provided on the side wall of the gate structure and a source / drain layer is formed in self-alignment with the second side spacer, the gate electrode and the source Since the distance to the drain layer can be accurately controlled, punch-through can be favorably suppressed.

Further, an emitter layer is formed by forming a polycrystalline silicon film on the top surface of the protrusion protruding from the semiconductor layer surface and diffusing impurities from the polycrystalline silicon film to the vicinity of the top surface of the protrusion. For example, a shallow junction can be formed by forming the emitter layer thin. As a result, the emitter injection efficiency is increased, and the high frequency characteristics can be significantly improved.

Further, in the case where the external base layer is formed by diffusing impurities in a polycrystalline silicon film formed so as to be in contact with the surface of the semiconductor layer around the emitter layer into the semiconductor layer, the above poly base is formed. A silicide film is stacked on a crystalline silicon film, and this stacked film can be used as a base electrode. In this case, the base electrode can be formed without a step of forming a contact hole. The same processing can be applied to the source / drain in the MOS section.

An insulating film is formed on the emitter layer, on the collector electrode lead-out part, and on the surface of the semiconductor layer of the MOS part outside the region where the external base is formed.
With a configuration in which a base electrode is formed on the insulating film, the base electrode can be freely routed to some extent.
For this reason, since the connection position between the metal wiring and the base electrode can be set arbitrarily, the degree of freedom of wiring can be increased. This makes it possible to form the wiring at a high density, which can contribute to downsizing of the device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the embodiment in the order of steps.

FIG. 3 is a cross-sectional view showing a method of manufacturing the semiconductor device of the embodiment in the order of steps.

FIG. 4 is a cross-sectional view showing a method of manufacturing the semiconductor device of the embodiment in the order of steps.

FIG. 5 is a sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment in the order of steps.

FIG. 6 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

[Explanation of symbols]

32 N-type epitaxial layer (first semiconductor layer) 34 Oxide film 35 P-type active base layer 36 N ⁺ -type emitter layer 37 Emitter electrode 38 Silicon oxide film 39 Structure 40 First side spacer 41 P ⁺ -type external base layer 42 Base electrode 421 Polycrystalline silicon film 422 Tungsten silicide film 43 N ⁺ type collector electrode lead-out part 44 Collector electrode 45 Silicon oxide film 54 Convex part 56 Oxide film (first insulating film) 57 First polycrystalline silicon film 58 Oxidation Silicon film (second insulating film) 60 Silicon oxide film (third insulating film) 61 Polycrystalline silicon film (second and third polycrystalline silicon films) 62 Tungsten silicide film 73A N-type epitaxial layer (second Semiconductor layer) 73B P-type well (second semiconductor layer) 74A, 74B Gate oxide film 76A, 7 B Gate electrode 77A, 77B Source layer 78A, 78B Drain layer 81A, 81B Source electrode 82A, 82B Drain electrode 811A, 811B Polycrystalline silicon film 812A, 812B Tungsten silicide film 86A, 86B Gate structure 87A, 87B Second side spacer 201 Bipolar section 202 CMOS section

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/06 H01L 21/8249 H01L 29/73 H01L 21/331

Claims (11)

(57) [Claims] 1. A bipolar transistor on the same substrate.
Is formed, and the MOS transistor is
Manufacturing a semiconductor device provided with a MOS portion to be formed.
Forming a first semiconductor layer of a first conductivity type in the bipolar portion.
And a step of reducing the concentration of impurities in a predetermined region on the surface of the first semiconductor layer.
The first semiconductor layer in the predetermined region is diffused upward.
Controlling to a second conductivity type different from the first conductivity type
When, to form a second semiconductor layer of the third conductive type to the MOS portion
And that step, engineering of forming a first insulating film on a surface of the second semiconductor layer
And a first process including an impurity for controlling the first conductivity type.
Forming a polycrystalline silicon film over the entire surface; and forming the first polycrystalline silicon film and the first insulating film anisotropically.
The first semiconductor is patterned by reactive etching.
From the first polycrystalline silicon film to the predetermined region on the layer
An emitter electrode is formed on the second semiconductor layer.
Forming a gate electrode made of a first polycrystalline silicon film;
And at the same time,
The first semiconductor layer in the constant region is connected to the emitter electrode.
To a predetermined depth in a self-aligned manner.
And a protrusion protruding from the surface of the first semiconductor layer after etching.
Forming a portion below the emitter electrode, and diffusing impurities in the emitter electrode to form an upper portion.
Control the conductivity type near the top surface of the projection to the first conductivity type.
This part is used as the emitter layer, and
The portion of the second conductivity type below the data layer is referred to as an active base layer.
Performing the second conductive process in the predetermined region of the first semiconductor layer.
By diffusing the impurity for controlling the mold to a high concentration
External base layer in a self-aligned manner with respect to the emitter layer.
Forming a first semiconductor layer and an impurity near the surface of the first semiconductor layer outside the predetermined region.
The substance is diffused to a high concentration and the collector of the first conductivity type is charged.
Forming a pole extraction portion and diffusing impurities in a high concentration near the surface of the second semiconductor layer
By doing so, the gate electrode is self-aligned
Forming a source layer and a drain layer
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the step of forming the external base layer comprises:
Contact the area around the emitter layer on the surface of the first semiconductor layer
And impurities for controlling the first conductivity type.
Of forming second polycrystalline silicon film containing high concentration of silicon
And impurities in the second polycrystalline silicon film with the first polycrystalline silicon film.
Forming a source layer and a drain layer in the semiconductor layer.
Forming source and drain layers on the surface of the second semiconductor layer;
It comes into contact with each area to be formed and
Third polycrystalline silicon containing a high concentration of impurities for controlling
Forming a silicon film and the third polycrystalline silicon film
Diffusing impurities therein into the second semiconductor layer;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising:
Construction method. 3. A process for forming said second polycrystalline silicon film.
Forming the third polycrystalline silicon film
It includes the steps of forming a single polycrystalline silicon film on the entire surface, in this single polysilicon film, the bipolar
To selectively control the first conductivity type in the part
Adding the impurity of the MOS portion in the one polycrystalline silicon film.
In some parts, there is no need to selectively control the fourth conductivity type.
3. A step of adding a pure substance.
The manufacturing method of the semiconductor device described in the above. 4. The second polycrystalline silicon film and a third polycrystalline silicon film.
Forming silicide film to cover polycrystalline silicon film
And degree, product of the second polycrystalline silicon film and the silicide film
Layer, leaving the part in contact with the external base layer
Patterned and based on the laminated film after patterning
A step of forming an electrode, and a product of the third polycrystalline silicon film and the silicide film
The layer film is in contact with the source layer and the drain layer
Leaving the portion is patterned, the product after patterning
The step of using the layer film as a source electrode and a drain electrode.
The semiconductor according to claim 2 or 3, wherein
Manufacturing method of body device. 5. A process for forming said second polycrystalline silicon film.
Before the process, the upper part of the emitter layer and the collector electrode
On the top of the protrusion and outside the area where the external base layer is formed
A second insulating film is formed on the surface of the first semiconductor layer.
4. The method according to claim 2, further comprising the step of:
Or the method of manufacturing a semiconductor device according to 4. 6. The method according to claim 1 , wherein before the step of forming the external base layer,
Forming a third insulating film over the entire surface;
The film is etched back to remove the surface of the first semiconductor layer.
Including the emitter layer and the active base layer protruding from
A first side spacer attached to a side wall of the structure, and
Including the gate electrode protruding from the second semiconductor layer
A second side spacer attached to the side wall of the gate structure;
2. The method according to claim 1, further comprising the step of forming.
6. The method of manufacturing a semiconductor device according to any one of claims 1 to 5. 7. A method of manufacturing a semiconductor device in which a bipolar portion on which a bipolar transistor is formed and a MOS portion on which a MOS transistor is formed are provided on the same substrate, wherein the bipolar portion has a first portion. Forming a first semiconductor layer of the conductive type described above, and diffusing impurities at a low concentration into a predetermined region on the surface of the first semiconductor layer. Controlling a second conductivity type different from the first conductivity type, forming a second semiconductor layer of a third conductivity type in the MOS portion, and forming a first semiconductor layer on the surface of the second semiconductor layer. A step of forming an insulating film; a step of forming a first polycrystalline silicon film including an impurity for controlling the first conductivity type on the entire surface; a step of forming the first polycrystalline silicon film and the first insulating film By patterning the film, the first Forming an emitter electrode made of the first polycrystalline silicon film in the predetermined region on the conductor layer, and forming a gate electrode made of the first polycrystalline silicon film on the second semiconductor layer; The first semiconductor layer in the predetermined region is etched by a predetermined depth in a self-aligned manner with respect to the emitter electrode, so that a protrusion protruding from the etched first semiconductor layer surface is formed below the emitter electrode. And controlling the conductivity type near the top surface of the projection to the first conductivity type by diffusing an impurity in the emitter electrode. This portion is used as an emitter layer. Using the portion of the second conductivity type below the active region as an active base layer; and diffusing the impurity for controlling the second conductivity type into the predetermined region of the first semiconductor layer at a high concentration. A step of forming an external base layer in a self-aligned manner with respect to the emitter layer; and a step of: diffusing impurities at a high concentration near the surface of the first semiconductor layer outside the predetermined region; Forming a conductive-type collector electrode extraction portion; and forming a source layer and a drain layer in a self-aligned manner with respect to the gate electrode by diffusing impurities at a high concentration near the surface of the second semiconductor layer. look including the step of, further, before the step of forming the external base layer, the third
Forming an insulating film on the entire surface; and forming the third insulating film
Etch back to project from the surface of the first semiconductor layer.
Structure including the emitted emitter layer and active base layer
A first side spacer attached to the side wall of
A gate including the gate electrode protruding from the second semiconductor layer;
Forming a second side spacer attached to the side wall of the gate structure
A method of manufacturing a semiconductor device. 8. The step of forming the external base layer includes: contacting a region around an emitter layer on a surface of the first semiconductor layer with a high concentration of impurities for controlling the first conductivity type; Forming a second polycrystalline silicon film including the first polycrystalline silicon film, and removing the impurities in the second polycrystalline silicon film from the first polycrystalline silicon film.
The step of forming the source layer and the drain layer, wherein the step of forming the source layer and the drain layer contacts the respective regions on the surface of the second semiconductor layer where the source layer and the drain layer are to be formed, and Forming a third polycrystalline silicon film containing a high concentration of impurities for controlling the conductivity type to 4; and diffusing the impurities in the third polycrystalline silicon film into the second semiconductor layer. 8. The method of manufacturing a semiconductor device according to claim 7 , comprising the steps of: 9. The step of forming the second polycrystalline silicon film and the step of forming the third polycrystalline silicon film include: forming one polycrystalline silicon film over the entire surface; A step of selectively adding an impurity for controlling to the first conductivity type to a portion of the bipolar portion in the polycrystalline silicon film, and a portion of the MOS portion in the one polycrystalline silicon film. to, claim, characterized in that it comprises a step of adding an impurity for controlling selectively the fourth conductive type 8
The manufacturing method of the semiconductor device described in the above. 10. The second polycrystalline silicon film and a third polycrystalline silicon film.
Forming a silicide film covering the polycrystalline silicon film, and patterning a laminated film of the second polycrystalline silicon film and the silicide film while leaving a portion in contact with the external base layer; A step of using the laminated film after patterning as a base electrode; and patterning the laminated film of the third polycrystalline silicon film and the silicide film except for a portion in contact with the source layer and the drain layer, the method according to claim 8 or 9, wherein the multilayer film further comprising a step of the source and drain electrodes after the patterning. 11. The method according to claim 1, wherein the step of forming the second polycrystalline silicon film includes the step of forming the first semiconductor layer on the upper part of the emitter layer, the upper part of the collector electrode take-out part, and outside the formation region of the external base layer. 9. The method according to claim 8 , further comprising the step of forming a second insulating film on each of the surfaces.
11. The method for manufacturing a semiconductor device according to 9 or 10 .