JP3198235B2 - Liquid crystal display panel drive device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a liquid crystal display panel which performs display by a simple dot matrix system.

[0002]

2. Description of the Related Art A liquid crystal display device can be formed to have a small depth irrespective of the size of a display screen, and can be reduced in weight, as compared with a display device using a conventional CRT (cathode ray tube). is there. Further, since display driving can be performed at a low voltage, there is an advantage that power consumption can be reduced. In particular, a simple dot matrix type liquid crystal display device is used in many electronic devices such as calculators and word processors because it has a simple structure and can reduce the manufacturing cost as compared with an active matrix type liquid crystal display device. .

FIG. 9 is a block diagram showing the configuration of a common driver 51 in a general simple matrix type liquid crystal display device, and FIG. 10 is a block diagram showing the configuration of a segment driver 56.

The common driver 51 includes selectors SA1,
SA2, SA3,..., SAm-1, SAm (the reference numeral SA is used when collectively referred to) and a D flip-flop FB
, FB2,..., FBm (the reference numeral FB is used when collectively referred to) and an inverter 52. m
Indicates the number of common electrodes connected to the common driver 51. The selector SA has a power supply 2 shown in FIG.
3, drive voltages V0, V1, V4, and V5 are input.

A signal obtained by inverting a latch pulse signal LP by an inverter 52 is input to a clock terminal CK of each D flip-flop FB. The D flip-flop FB1 is
At the falling timing of the latch pulse signal LP, the vertical synchronization signal DI01 input to the input terminal D is latched and output from the output terminal Q as a signal Z1. Signal Z1
Is input to the terminal SEL of the selector SA1 and the input terminal D of the D flip-flop FB2.

The D flip-flops FB2 to FBm latch the signals Z1 to Zm-1 input to the input terminal D at the falling timing of the latch pulse signal LP, and output the signals from the output terminal Q as signals Z2 to Zm. Signals Z1 to Zm
Are referred to by the reference sign Z.

[0007] The selectors SA1 to SAm output the AC signal M
And the driving voltages V0, V1,
V4 and V5 are selected and output from the output terminal O. Table 1 shown below is a truth table for the selector A of the common driver 51.

[0008]

[Table 1]

As shown in Table 1, when the value of the signal Z input to the terminal SEL is "0" and the value of the alternating signal M is "0", the output voltage becomes V4, If "1", the output voltage is V1. The value of signal Z is "1"
When the value of the AC signal M is "0", the output voltage is V0, and when the value is "1", the output voltage is V5.

The output terminals O of the selectors SA are connected to common electrodes of the liquid crystal panel, respectively, and the driving voltage selected by the selectors SA is sequentially supplied to each selector. One vertical scanning period is from when the selector SA1 outputs the driving voltage to when the selector SAm finishes outputting the driving voltage. After the one vertical scanning period, the driving voltage is output again from the selector SA1. You.

The segment driver 56 includes a selector G
1, G2, G3,..., Gp (the reference number G is used when collectively referred to), the D flip-flop H0, and the D flip-flops H1, H2, H3,. ) And an inverter 57. p is selected to be に of the number of segment electrodes connected to the segment driver 56.

The selector G receives driving voltages V0, V2, V3, and V5 from a power supply 23 shown in FIG. 3, which will be described later, and further converts an AC signal M, display data D0 to D3, and an inverted signal XCK. And the signal EN which is the output of each D flip-flop H is input.

The D flip-flop H0 receives a signal EI01 at an input terminal D and a signal XC at a clock terminal CK.
K is input, and a latch pulse signal LP is input to a terminal E. The D flip-flop H0 latches the signal level of the signal EI01 when the signal XCK rises while the latch pulse signal LP input to the terminal E is at the high level. Output terminal Q of D flip-flop H0
Is input to the input terminal D of the flip-flop H1, latched at the rising timing of the signal XCK, and output as the signal EN1. Signal E
N1 is the terminal EN of the selector G1 and the flip-flop H
2 input terminal D. Flip-flop H2
Thereafter, the output of the preceding flip-flop H is set to the signal XCK.
Latched at the rising timing of, and output as a signal EN.

The selectors G1 to Gp provide a signal obtained by inverting the signal XCK by the inverter 57 and display data D0 to D3.
, And the driving voltages V0, V2, V3, and V5 are selectively output based on the AC conversion signal M and the signals EN1 to ENp.

Table 2 below shows the segment driver 56
Is a table showing the relationship between signals at the time of data capture in Table 1. Table 3 is a truth table in the segment driver 56.

[0016]

[Table 2]

[0017]

[Table 3]

As shown in Table 2, when the value of the signal EN is "0", the latched data does not change regardless of the value of the display data D0 to D3. When the value of the signal EN is "1", the values of the display data D0 to D3 are latched data values.

As shown in Table 3, when the latched data is "0" and the value of the AC signal M is "0", V3 is output as the driving voltage, and when the value is "1", the driving voltage is V3. Is output as V2. When the latched data is "1" and the value of the alternating signal M is "0", V5 is output as the drive voltage, and when the value is "1", V0 is output as the drive voltage.
Is output. Outputs S1 to S4 of the selector G are connected to segment electrodes in the liquid crystal display panel, respectively, and supply a drive voltage. The selector G supplies a drive voltage during one horizontal scanning period while one selector A in the common driver 51 outputs a drive voltage.

As described above, display is performed by the common driver 51 and the segment driver 56 applying a drive voltage to each electrode of the liquid crystal display panel.

In an electronic device including a liquid crystal display device as described above, power is supplied to the liquid crystal display device or the entire electronic device when no operation is performed for a certain period of time to save power. Control called so-called auto power-off for shutting off is performed.

Another prior art for achieving power saving is disclosed in Japanese Patent Laid-Open No. 4-115288. In the prior art, when no operation is performed for a predetermined time, data of an image displayed on a display unit is compressed by a predetermined method, and a display is performed based on the compressed image data. By compressing image data, the power required for data transfer has been reduced. further,
Since the image data is compressed, the area required for display is reduced, and the power required for display is reduced.

[0023]

In the conventional auto power-off control, when the power of the entire electronic device is turned off, a process such as initialization is required when the electronic device is used again, and the electronic device becomes ready for use. It takes time to become.

When the power supply of the liquid crystal display device is turned off, it is easy to determine whether the power supply to the electronic device is turned on or the liquid crystal display device is turned off to reduce power consumption. For example, there is a possibility that a cable for connecting the electronic device to an external device is accidentally disconnected, and a continuous operation cannot be performed.

Further, in the prior art disclosed in the above publication, the power consumed when transferring image data from the display controller to the display driver is reduced by reducing the amount of image data. Since the display driver consumes the most power when performing this operation, the power saving effect is low. Further, in a display driver that performs display using a VRAM (Video RAM), the above-described data transfer is not required, so that power saving cannot be achieved by using the prior art.

An object of the present invention is to provide a driving apparatus for a liquid crystal display panel which can realize two driving modes and can drive one of the driving modes with less power consumption than the other driving mode.

[0027]

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display panel in which a plurality of common electrodes and a plurality of segment electrodes are arranged so as to be perpendicular to each other with a liquid crystal interposed between the electrodes. In a driving device for driving, a first drive mode in which a selection voltage is applied to common electrodes one by one in accordance with an arrangement order, and a selection voltage is applied to each common electrode group configured by grouping common electrodes in an arrangement direction. A common electrode driving unit that switches and executes the second driving mode to be applied, and applies a display voltage based on display data supplied from the outside to the segment electrode in synchronization with the application timing of the selection voltage by the common electrode driving unit. And a common electrode driving unit that is provided separately for each common electrode and applies a selection voltage to the common electrode. Comprising a number of selection means, in any of the driving modes of the first drive mode and the second drive mode,
A driving device for a liquid crystal display panel, wherein selection waveforms having the same selection width are individually applied from respective selection means to a common electrode. According to the present invention, a driving device for a liquid crystal display device drives a liquid crystal display device in which a plurality of common electrodes and a plurality of segment electrodes are interposed with a liquid crystal between the electrodes and arranged so as to be orthogonal to each other. In the first driving mode, the common electrode driving means applies a selection voltage to the common electrodes one by one in accordance with the arrangement order, and in the second driving mode, the common electrode driving means arranges the common electrodes. A selection voltage is applied to each common electrode group formed by grouping along the direction. The segment electrode driving means performs a display on the liquid crystal display device by applying a display voltage based on externally applied display data to the segment electrodes in synchronization with the application timing of the selection voltage by the common electrode driving means. Therefore, in the case of the second drive mode, the selection voltage is applied to each of the common electrode groups constituted by the plurality of common electrodes, and the power required to drive the common electrodes in the liquid crystal display device is reduced. Can be reduced. In addition, the first drive mode and the second drive mode
In any one of the driving modes, a selection waveform having the same selection width is applied to the common electrode. Therefore,
In the second drive mode, the vertical scanning cycle becomes shorter as the number of common electrodes driven simultaneously increases, so that the next charge can be performed before the charge stored in the liquid crystal is discharged, and a sufficient contrast is obtained. be able to. Also,
Since the vertical scanning cycle is short, even when displaying a moving image, it can be smoothly displayed. Further, even when a selection voltage is applied to the common electrode group in the second drive mode,
One common electrode is driven by one selection unit. Therefore, the burden on each selection means can be dispersed.

Further, the present invention is characterized in that display data generating means for providing predetermined display data to the segment electrode driving means when the second driving mode is being executed by the common electrode driving means. According to the present invention, when driving the liquid crystal display device, the segment electrode driving unit is configured to output predetermined display data provided from the display data generating unit when the second driving mode is executed by the common electrode driving unit. The segment electrode is driven based on the signal. Therefore, even a person other than the operator of the electronic device including the liquid crystal display device can easily determine that the liquid crystal display device is operating in the second drive mode.

Further, according to the present invention, the segment electrode driving means is configured such that the segment electrodes are grouped along the arrangement direction when the second driving mode is executed by the common electrode driving means. The same display voltage is applied to each electrode of the group. According to the present invention, when driving the liquid crystal display device, the segment electrode driving means divides the segment electrodes into groups along the arrangement direction when the second driving mode is executed by the common electrode driving means. The same display voltage is applied to each electrode of the configured segment electrode group. Therefore, in the case of the second drive mode, both the common electrode driving means and the segment electrode driving means apply the same voltage to a plurality of electrodes for each electrode, and display on the liquid crystal display device. It is possible to reduce the power required for performing the operation.

Further, in the present invention, when the liquid crystal display panel has m common electrodes and the common electrode group includes n (n <m) common electrodes, a pulse generation means comprising m flip-flops for sequentially generating a clock signal defining the application timing of the selection voltage, and a pulse generation means provided corresponding to the common electrode, and selected for each common electrode in synchronization with the clock signal A pulse generator comprising: m selection means for applying a voltage; and m switching means for providing any one of the signals input to the input terminals to the selection means in accordance with the drive mode. The output of the i-th (i is 1 to m / n) -th flip-flop in the generating means is supplied to the first input terminal of the i-th switching means and the second input of the (ni-n + 1) th to the ni-th switching means. Is input to the terminal, the m / n + 1
The outputs of the flip-flops from the (m) -th to (m) -th are input to the first input terminals of the (m / n + 1) -th to (m) -th switching means. A clock signal input to one input terminal is output, and in the second drive mode, a clock signal input to a second input terminal is output. According to the present invention, when the liquid crystal display device is provided with m common electrodes, the common electrode driving means includes a pulse comprising m selection means, m switching means, and m flip-flops. And generating means. Assuming that a common electrode group is formed by n common electrodes, the outputs of the first to m-th flip-flops in the pulse generating means are output from the first to m-th switching means of the first to m-th switching means. The outputs of the i-th (i is 1 to m / n) -th flip-flops input to the input terminals are input to the second input terminals of the switching means from the (ni-n + 1) th to the (ni) th switching means. When the common electrode driving unit operates in the first driving mode, the switching unit supplies a clock signal input to the first input terminal to the corresponding selecting unit, and when the common electrode driving unit operates in the second driving mode, the switching unit supplies the clock signal. , The switching means inputs the clock signal input to the second input terminal to the corresponding selection means. Therefore, in the second driving mode, the clock signal output from the i-th flip-flop is supplied to the ni-n-th flip-flop via the switching means.
The signals are input to the + 1st to the nith selection means, and the n selection means apply the selection voltage to the corresponding common electrodes at the same time, which is required when driving the common electrodes while performing display. Power can be reduced.

Further, according to the present invention, when the liquid crystal display panel has u segment electrodes, and the segment electrode group is composed of v (v <u) segment electrodes, a pulse generating means comprising u flip-flops for sequentially generating a clock signal defining the application timing of the selection voltage, and a pulse generating means provided corresponding to the segment electrode, and displayed on each segment electrode in synchronization with the clock signal U selecting means for applying a display voltage based on data, u switching means including two input terminals, and outputting any signal input to the input terminal to the selecting means according to the drive mode; And the output of the j-th (j is 1 to u / v) -th flip-flop in the pulse generation means is connected to the first input terminal of the j-th switching means and vj-v + Is input to a second input terminal of the switching means until the vj th from th, the output of the flip-flop from the u / v + 1 th to the u th, u-th / v + 1
The first input terminal of the first to the u-th switching means, the switching means outputs a clock signal input to the first input terminal in the first drive mode,
In the second drive mode, a clock signal input to a second input terminal is output. According to the present invention, if the segment electrode driving means is provided with u segment electrodes in the liquid crystal display device, a pulse comprising u selecting means, u switching means, and u flip-flops is provided. And generating means. Assuming that a segment electrode group is constituted by v segment electrodes, the outputs of the first to u-th flip-flops in the pulse generation means are as follows:
The outputs of the j-th (j is 1 to u / v) -th flip-flops are input to the first input terminals of the first to u-th switching means, respectively, and output from the vj-v + 1-th to v-th
The signals are input to the second input terminals of the switching means up to j-th. When the segment electrode driving unit operates in the first driving mode, the switching unit supplies a clock signal input to the first input terminal to the corresponding selecting unit, and when the segment electrode driving unit operates in the second driving mode, the switching unit supplies the clock signal. , The switching means inputs the clock signal input to the second input terminal to the corresponding selection means. Therefore, the control of the segment electrode driving means can be performed in the same manner as the common electrode driving means, and the control of each electrode driving means in the liquid crystal display device can be simplified.

[0032]

FIG. 1 is a block diagram showing a configuration of a common driver 31 according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a part of the common driver 31. FIG. 3 is a block diagram illustrating a configuration of the electronic device 1 provided with the common driver 31. FIG. 4 is a block diagram illustrating a configuration of the liquid crystal display device 2 in the electronic device 1.

The electronic device 1 includes a liquid crystal display device 2 and a CPU
(Central processing unit) 10 and ROM (Read Only Memory)
12, RAM (Random Access Memory) 13, RT
C (Real Time Clock) 14, tablet control circuit 15, A / D (analog / digital) converter 1
6, tablet 17, VRAM (Video RAM) 21
, A liquid crystal controller 22, and a power supply device 23. The liquid crystal display device 2 includes a liquid crystal display panel 18.
, Common drivers 31 and 32 and segment driver 3
3 and 34.

The CPU 10 controls the entire electronic device 1 via a system bus 11. The ROM 12 has a CPU
Ten control programs and the like are stored, and the RAM 13 stores data related to the programs to be executed. The RTC 14 performs a timing operation, and the electronic device 1
Is used to perform a clock function, a calendar function, and the like.

The tablet 17 is controlled by a tablet control circuit 15, and the detected coordinates are converted into digital signals by an A / D converter 16 and sent to the CPU 10 via the system bus 11. The power supply device 23 supplies a circuit voltage for operating a circuit such as the CPU 10 and a liquid crystal driving voltage for driving the liquid crystal of the liquid crystal display panel 18.

The VRAM 21 is supplied with data for display via the system bus 11 and stored therein. The data is read out by the liquid crystal controller 22 as appropriate and supplied to the segment drivers 33 and 34. In addition, the liquid crystal controller 22 transmits a signal serving as a reference for performing display to the common drivers 31 and 32 and the segment driver 3.
3, 34. The liquid crystal controller 22 supplies a shift pulse signal LP, an alternating signal M, a start signal S, and a power save signal PS to the common drivers 31 and 32, and the display data D to the segment drivers 33 and 34.
0 to D3, a shift pulse signal LP, an alternating signal M, a signal XCK, and a power save signal PS. When the value of the power save signal PS is “0”, a normal display operation is performed as the first drive mode, and when the value is “1”, the power save signal PS is consumed as the power save mode as the second drive mode. The display operation is performed so that the power is reduced.
The alternating signal M is a signal for inverting the polarity of the liquid crystal driving voltage input to the liquid crystal display panel 18 at predetermined intervals.

The liquid crystal display device 2 includes a common driver 31,
If the number of common electrodes provided on the liquid crystal display panel 18 is, for example, 240,
The common driver 31 performs, for example, scanning for 120 lines. In this embodiment of the present invention, the description will be made on the assumption that the number of common electrodes is 240. Referring to FIGS. 1 and 2, common driver 31 includes selector SL
1 to SL120 (when collectively referred to, use the reference sign SL)
, Power save circuits J1 to J120 (the reference numeral J is used when collectively referred to), and D flip-flops DF1 to DF
F121 (a reference numeral DF is used when collectively referred to) and an inverter NT1. Although the configuration and operation of the common driver 31 will be described in this embodiment of the present invention, the same applies to the common driver 32.

A vertical synchronizing signal DI01 is input to an input terminal D of the D flip-flop DF1, and is latched based on a signal obtained by inverting a shift pulse signal LP by an inverter NT1. The latched signal level is output from output terminal Q of D flip-flop DF1 as signal q1. Signal q1 is input to terminals A and B of power save circuit J1 and terminals A of power save circuits J2 to J4. The signal q1 is a D flip-flop DF2
Is input to the input terminal D. The signal q2 is input to the terminal B of the power save circuit J2. The signal q2 is input to each terminal A of the power save circuits J5 to J8.

The D flip-flops subsequent to the D flip-flop DF2 latch on the basis of the shift pulse signal LP obtained by inverting the output of the preceding D flip-flop and output it as a signal q.

Therefore, the D flip-flop DFr
The signal qr, which is the output of (r is an integer of 1 to 30), is input to the terminal B of the power save circuit Jr and the terminals A of the 4r-3rd to 4rth power save circuits J. The output of the D flip-flop DF121 is provided to the common driver 32 as a vertical synchronization signal DI02.

The power save circuit J is provided with terminals A, B, and PS for signal input, and a terminal O for signal output.
Is provided. A signal q which is an output of the corresponding D flip-flop DF is input to a terminal B of the power save circuit J. Further, to the terminal A, the signal q is sequentially input from the first set as a set of four power save circuits J in order from the power save circuit J1. The power save signal PS is input to the terminal PS. The output terminal O of the power save circuit J is connected to the terminal SEL of the selector SL.
The power save circuit J outputs signals JO1 to JO120 from an output terminal O based on signals input to terminals A, B and PS.
(The reference numeral JO is used when collectively referred to).

Table 4 shown below is a truth table in the power save circuit J.

[0043]

[Table 4]

When the value of the signal PS is "0", the output value of the output terminal O is "1" when the value input to the terminal B is "1" regardless of the value input to the terminal A. Becomes When the value input to the terminal B is “0”, the output value of the output terminal O is “0”. When the value of the signal PS is “1”, the output value of the output terminal O is “1” when the value input to the terminal A is “1” regardless of the value input to the terminal B. When the value input to the terminal A is “0”, the output value of the output terminal O is “0”.

The selector SL selectively outputs the driving voltages V0, V1, V4 and V5 based on the signal JO input to the terminal SEL and the AC signal M input to the terminal M. The output terminal O of the selector SL has a liquid crystal display panel 1
8 are connected to each other.

FIG. 5 is a timing chart of each signal in the common drivers 31 and 32. The period T1 from the rise of the vertical synchronization signal DI01 shown at (1) at time t0 to the rise of time t11 again is one vertical scanning period. For example, when the common drivers 31 and 32 drive the liquid crystal display panel 18 shown in FIG. 4, 240 pulses of the shift pulse signal LP shown in FIG. 5B are output during one vertical scanning period, and 1/240 duty driving is performed. Will be

The shift pulse signal LP is at a high level during a period from time t1 to time t2 included in a period during which the vertical synchronizing signal DI01 is at a high level from time t0 to time t3. When shift pulse signal LP falls at time t2, signal JO1 shown in FIG. 5 (3) rises from time t2, and then at time t4 when shift pulse signal LP subsequently falls.
Up to the high level. Also, at time t4, FIG.
The signal JO2 shown in (5) rises and goes high until time t5. At time t5 when signal JO2 falls, signal JO3 shown in FIG. 5 (6) rises. Signal JO
3 falls at time t6 when the shift pulse signal LP falls. The signal JO4 shown in FIG.
To a high level from time t7. The signal JO5 shown in FIG. 5 (8) is at a high level from time t7 to time t8. Thereafter, the signal JO sequentially goes high, and at time t9, the signal JO240 shown in FIG. 5 (9) goes high.

Time t1 at which the subsequent vertical scanning period starts
In 1, when the power save signal shown in FIG. 5C rises from the low level to the high level, the common drivers 31 and 32 enter the power save mode. Therefore,
When shift pulse signal LP falls at time t12, all of signals JO1 to JO4 attain a high level. Subsequently, when shift pulse signal LP falls at time t13, signals JO1-JO4 attain a low level, and signal JO1
5 becomes high level. Although not shown in FIG. 5, signals JO6 to JO8 are the same as signal JO5. That is, signals JO5 to JO8 are at the high level from time t13 to time t14.

After time t14, shift pulse signal LP
Each time the signal falls, four consecutive signals JO become high level. Since four common electrodes are simultaneously scanned by four consecutive signals JO, scanning of all common electrodes is completed when the shift pulse signal LP falls 60 times.

When the power save signal PS is at the high level in the power save mode, when the signal qr is at the high level, the outputs of the 4r-3rd to 4rth power save circuits J are at the high level, and the liquid crystal is displayed. The duty ratio of the display panel 18 is changed from 1/240 to 1/60.

Generally, the liquid crystal drive voltage VDSP is as follows: when the duty is D, the bias is B, and the liquid crystal lighting voltage is VON, VDSP = (VON × B) {(B ² + D−1) / D} .. (1). The bias B is determined based on the number of common electrodes provided on the liquid crystal display panel 18 and indicates a ratio between a liquid crystal lighting voltage and a liquid crystal non-lighting voltage at which an optimum contrast ratio can be obtained.

When the driving voltage VDSP of the liquid crystal is calculated by substituting the bias B = 9 and the liquid crystal lighting voltage VON = 2 V into the equation (1), it is 15.59 in the case of 1/240 duty.
(V), and 11.78 for 1/60 duty
(V). Therefore, by changing the duty from 1/240 to 1/60, the drive voltage can be reduced by about 3.8V.

The conditions for shifting the control to the power save mode include, for example, when no input has been made to the electronic device 1 for a predetermined time or when an operator performs a predetermined operation.

As described above, according to the embodiment of the present invention, when the power save signal PS is at a low level, the common driver 31 applies a voltage to each common electrode in accordance with the rising timing of the sequentially generated signal q. Drive voltage is being applied. When the power save mode is set and the power save signal PS goes high, the signal qr is supplied to the 4r-3rd to 4rth power save circuits J, and one type is simultaneously applied to the four common electrodes. Is applied. Therefore, 1
In the vertical scanning period, the apparent number of electrodes scanned by the common driver 31 becomes １ ／, and the common driver 31
Can reduce the power consumed.

FIG. 6 is a block diagram showing a configuration of a segment driver 33 according to a second embodiment of the present invention. Assuming that the number of segment electrodes provided on the liquid crystal display panel 18 is, for example, 320, the segment drivers 33 and 34 scan, for example, 160 each. In this embodiment of the present invention, the description will be made on the assumption that the number of segment electrodes is 320.
Since the segment driver 33 has the same configuration as the segment driver 34, the segment driver 33 will be described in this embodiment of the present invention.

The segment driver 33 has a selector SN
1 to SN40 (use the reference number SN when collectively referred to)
, Power save circuits JS1 to JS40 (the reference numeral JS is used when collectively referred to), and a D flip-flop FF1
To FF40 (the reference numeral FF is used when collectively referred to)
It is configured to include a flip-flop EF1 and an inverter NT2. In FIG. 6 and FIG. 7, display data D0 to D3 are such that 1-bit information is represented by four signal lines.
The bits are simultaneously supplied to the selector SN.

In the segment driver 33, a signal EI01 is input to the input terminal D of the flip-flop EF1. Signal EI01 is equal to voltage VCC supplied to segment driver 33. A shift pulse signal LP is input to an input terminal E, and a clock terminal C
The signal XCK is input to K.

The flip-flop EF1 latches the level of the signal input to the input terminal D when the signal XCK rises while the shift pulse signal LP is at the high level. The latched signal level is output from the output terminal Q as a signal EN0. The signal EN0 is D
The signal is input to the input terminal D of the flip-flop FF1. The signal EN0 is supplied to the terminals A and B of the power save circuit JS1.
And the terminals A of the power save circuits JS2 to JS4.

The D flip-flop FF latches the level of the signal EN input to the input terminal D at the rising timing of the signal XCK and outputs it from the output terminal Q. The output of the D flip-flop FF40 is input to the segment driver 34 as a signal EI02.

Signals EN0 are commonly input to terminals A and B of power save circuit JS1, and power save signal PS is input to terminal PS. The signal SO1 output from the terminal O of the power save circuit JS1 is input to the terminal EN of the selector SN1. Table 5 shown below is a truth table of the power save circuit JS.

[0061]

[Table 5]

As shown in Table 5, the power save signal PS
Is "0", the value of the output signal SO is "0" when the value of the signal input to the terminal B is "0", regardless of the value input to the terminal A. When the value input to the terminal B is "1", the value of the signal SO is "1". When the value of the power save signal PS is “1”, regardless of the value of the signal input to the terminal B,
When the value input to the terminal A is “0”, the value of the signal SO is “0”, and when the value of the signal input to the terminal A is “1”, the value of the signal SO is “1”. Become.

The selector SN sets the display data D0 to D3
Drive signals V0, V2, V3, V5 at output terminals S1 to S4 connected to the segment electrodes, respectively, based on AC signal M, signal SO, and signal obtained by inverting signal XCK by inverter NT2. Selectively outputs one voltage. The signal ENs (s is 0 to 9) is input to the terminal B of the power save circuit JSs and the terminals A of the 4s + 1th to 4s + 4th power save circuits JS.

FIG. 8 is a timing chart of each signal in the segment drivers 33 and 34. Fig. 8 (1)
Is always at a high level in the timing chart of FIG. At time t20, a period T11 from when the latch pulse signal LP shown in FIG. 8 (2) rises to a high level until the latch pulse signal LP rises again at time t30 is one horizontal scanning period.

At time t21 in period T12 from time t20 to time t22 when latch pulse signal LP is at the high level, signal XCK shown in FIG. 8 (3) rises, and signal SO1 shown in FIG. 8 (6) rises. It goes up to a high level. When signal XCK rises at time t23, signal SO1 goes low, and signal SO2 shown in FIG. 8 (7) goes high. When the signal XCK rises at time t24, the signal SO2 goes low, and the signal SO3 shown in FIG. 8 (8) goes high. Thereafter, similarly, from time t25 to time t26, the signal SO4 shown in FIG. 8 (9) becomes high level, and from time t26 to time t27, the signal SO5 shown in FIG. 8 (10) becomes high level. In addition, when the signal SO40 shown in FIG. 8 (11) goes high from time t28 to time t29, the liquid crystal drive voltage is applied to the corresponding segment electrode, and the horizontal scanning period ends. For example, the signal SO2 is at a high level during a period T13 from time t23 to time t24, and the display data D0 to D3 shown in FIG.
Is taken into the selector SN.

In the period T11, which is one horizontal scanning period, the driving voltage based on the display data D0 to D3 is applied to the segment electrodes of the liquid crystal display panel 18 by sequentially setting the signals SO1 to SO40 to the high level.

Time t30 at which the subsequent horizontal scanning period starts
In FIG. 8, when the power save signal PS shown in FIG. Time t
When the signal XCK rises at 31, the signals SO1-S
O4 is at the high level until time t32 when the signal XCK rises again. At time t32, the three signals subsequent to the signal SO5 go high at the same time. That is, in the power save mode, the signal SO sequentially rises to the high level in a set of four signals in synchronization with the rising of the signal XCK.

As described above, according to this embodiment of the present invention, when the power save signal PS goes high, the power save mode is set, and the signal ENs is applied to the 4s + 1th to 4s + 4th power save circuits JS. As a result, one type of driving voltage based on the display data D0 to D3 is applied to the four segment electrodes at the same time, and the common driver 31 shown in the first embodiment is applied.
Similarly, the segment driver 33 can be controlled.

In the power saving mode, the ROM 12
Alternatively, predetermined image data may be read out from the CPU to display an image. By displaying an image on the liquid crystal display panel 18 based on the predetermined image data, it is possible to easily determine in which drive mode the liquid crystal display device 2 is being driven. It is possible to prevent the work from being stopped continuously by turning off the power.

[0070]

As described above, according to the present invention, when the common electrode driving means is in the first driving mode, the common electrode driving means applies the selection voltage to the common electrodes one by one according to the arrangement order.
In the second drive mode, since a selection voltage is applied to each common electrode group including a plurality of common electrodes, power required to drive the common electrodes in the liquid crystal display device can be reduced. Further, in either of the first drive mode and the second drive mode, a selection waveform having the same selection width is applied to the common electrode. The scanning period becomes shorter. Thus, the next charge can be performed before the electric charge stored in the liquid crystal is discharged, and a sufficient contrast can be obtained. Further, since the vertical scanning cycle is short, even when displaying a moving image, it can be smoothly displayed. further,
Even when a selection voltage is applied to the common electrode group in the second drive mode, one common electrode is driven by one selection unit, so that the load on each selection unit can be dispersed.

According to the present invention, when the second drive mode is executed by the common electrode drive means,
Since the segment electrode driving means drives the segment electrodes based on predetermined display data provided from the display data generating means, it is possible to easily determine that the liquid crystal display device is driven in the second drive mode, It is possible to prevent the work from being interrupted by, for example, turning off the power while the work is being performed by mistake.

Further, according to the present invention, when the second drive mode is being executed by the common electrode drive means, the segment electrode drive means is configured to divide the segment electrodes into groups along the arrangement direction. Since the same display voltage is applied to each of the electrodes, the common electrode driving means and the segment electrode driving means apply the same voltage to each of the plurality of electrodes for each electrode. The required power can be reduced.

Further, according to the present invention, the common electrode drive means operates in one of the first and second drive modes, and in the second drive mode, the clock output from the i-th flip-flop is output. The signal is input to the (ni-n + 1) th to (ni) th selection means via the switching means, and the same selection voltage is applied to each of the common electrode groups formed by the n common electrodes in the m common electrodes. Is applied, the power required for driving the common electrode can be reduced.

Further, according to the present invention, the common electrode drive means operates in one of the first and second drive modes, and in the second drive mode, the clock output from the i-th flip-flop is output. The signal is input to the (ni-n + 1) th to (ni) th selection means via the switching means, and the same selection voltage is applied to each of the common electrode groups formed by the n common electrodes in the m common electrodes. Is applied, the common electrode driving means and the segment electrode driving means can be operated in the same driving mode, and the control of each electrode driving means can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a common driver 31 according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a part of a common driver 31.

FIG. 3 is a block diagram illustrating a configuration of the electronic device 1.

FIG. 4 is a block diagram showing a configuration of the liquid crystal display device 2.

FIG. 5 is a timing chart of each signal in the common driver 31.

FIG. 6 is a block diagram illustrating a configuration of a segment driver 33 according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a part of a segment driver 33.

8 is a timing chart of each signal in the segment driver 33. FIG.

FIG. 9 is a block diagram showing a configuration of a common driver 51 which is a typical conventional example.

FIG. 10 is a typical conventional example of a segment driver 5;
6 is a block diagram showing a configuration of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Electronic apparatus 2 Liquid crystal display device 10 CPU 11 System bus 12 ROM 13 RAM 14 RTC 15 Tablet control 16 A / D converter 17 Tablet 18 Liquid crystal display panel 21 VRAM 22 Liquid crystal controller 23 Power supply device 31, 32 Common driver 33, 34 Segment Driver NT1, NT2 Inverter DF, FF D flip-flop J, JS Power save circuit SL, SN selector

Claims (5)

(57) [Claims] 1. A driving device for driving a liquid crystal display panel in which a plurality of common electrodes and a plurality of segment electrodes are arranged so as to intersect a liquid crystal between the electrodes and to be orthogonal to each other for display, comprising: A first drive mode in which a selection voltage is applied one by one in accordance with the arrangement order, and a second drive mode in which a selection voltage is applied to each common electrode group formed by grouping the common electrodes along the arrangement direction. And a segment electrode driving unit that applies a display voltage based on display data supplied from the outside to the segment electrodes in synchronization with the application timing of the selection voltage by the common electrode driving unit. The common electrode driving unit includes a plurality of selection units that are individually provided for each common electrode and apply a selection voltage to the common electrode. A driving device for a liquid crystal display panel, wherein a selection waveform having the same selection width is individually applied to a common electrode from each selection means in any one of the first driving mode and the second driving mode. 2. The display device according to claim 1, further comprising: display data generating means for supplying predetermined display data to said segment electrode driving means when said second driving mode is being executed by said common electrode driving means. Liquid crystal display panel driving device. 3. The segment electrode driving means, wherein when the common electrode driving means is executing the second driving mode, each of the segment electrode groups configured by grouping the segment electrodes along the arrangement direction is provided. 2. The liquid crystal display panel driving device according to claim 1, wherein the same display voltage is applied to the electrodes. 4. The common electrode driving means, wherein the liquid crystal display panel has m common electrodes, and the common electrode group includes n (n <m) common electrodes. A pulse generating means comprising a flip-flop for sequentially generating a clock signal defining the application timing of the selection voltage; and a pulse generation means provided corresponding to the common electrode, and applying the selection voltage to each common electrode in synchronization with the clock signal. A pulse generating means, comprising: m selecting means; and m switching means for providing two input terminals and outputting any signal input to the input terminal to the selecting means according to the drive mode. The output of the i-th (i is 1 to m / n) -th flip-flop is connected to the first input terminal of the i-th switching means and the second input terminal of the (ni-n + 1) th to the ni-th switching means. Is the force, the output of the flip-flop from the m / n + 1-th to the m th, the m / n
The first input terminal of the first to m-th switching means, and the switching means outputs a clock signal input to the first input terminal in the first drive mode, 2. The liquid crystal display panel driving device according to claim 1, wherein in the driving mode, a clock signal input to the second input terminal is output. 5. The segment electrode driving means, wherein the liquid crystal display panel has u segment electrodes, and the segment electrode group is composed of v (v <u) segment electrodes; A pulse generating means comprising a flip-flop for sequentially generating a clock signal defining the application timing of the selection voltage; provided in correspondence with the segment electrodes, and based on display data on each segment electrode in synchronization with the clock signal. U selection means for applying a display voltage, and u switching means for providing two input terminals and outputting any signal input to the input terminal to the selection means in accordance with the drive mode, The output of the j-th (j is 1 to u / v) -th flip-flop in the pulse generation means is connected to the first input terminal of the j-th switching means and from the (vj-v + 1) -th Is input to a second input terminal of the switching means of vj to th, the output of the flip-flop from the u / v + 1 th to the u th, u-th / v
+ 1st to u-th switching means are input to first input terminals of the switching means, and in the first drive mode, the switching means outputs a clock signal input to the first input terminal, and 4. The driving device for a liquid crystal display panel according to claim 3, wherein in the driving mode, a clock signal input to the second input terminal is output.