JP3203531B2 - Sidewall manufacturing method and semiconductor device - Google Patents
Sidewall manufacturing method and semiconductor deviceInfo
- Publication number
- JP3203531B2 JP3203531B2 JP13662093A JP13662093A JP3203531B2 JP 3203531 B2 JP3203531 B2 JP 3203531B2 JP 13662093 A JP13662093 A JP 13662093A JP 13662093 A JP13662093 A JP 13662093A JP 3203531 B2 JP3203531 B2 JP 3203531B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- oxide film
- annealing
- ozone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
- H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
- H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
Landscapes
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は絶縁膜の側端部に設ける
サイドウォールの製造方法に係り、特に低温反応により
サイドウォールを製造する方法の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a sidewall provided at a side end of an insulating film, and more particularly to an improvement in a method for manufacturing a sidewall by a low-temperature reaction.
【０００２】[0002]
【従来の技術】従来、この種のシリコン酸化膜の製造方
法としては、例えば反応ガスとしてＳｉＨ4 とＮ2 Ｏを
用いて減圧ＣＶＤによりＨＴＯ膜を形成する方法が知ら
れている。また、他の製造方法としては、特開平３ー４
１７３１号公報，特開平３ー２０１４３５号公報に示さ
れているように、テトラエトキシシラン（以下、ＴＥＯ
Ｓと記す）とオゾンを温度３９０〜４３０℃の常圧下に
おいて反応させて膜を成長させ、更にオゾン雰囲気中等
でアニール処理することによりシリコン酸化膜を得る方
法が知られている。2. Description of the Related Art Heretofore, as a method of manufacturing a silicon oxide film of this type, for example, a method of forming an HTO film by low-pressure CVD using SiH 4 and N 2 O as reaction gases is known. Further, another manufacturing method is disclosed in
No. 1731 and Japanese Patent Laid-Open Publication No. Hei 3-201435, as disclosed in tetraethoxysilane (hereinafter referred to as TEO).
A method is known in which a film is grown by reacting ozone with ozone under normal pressure at a temperature of 390 to 430 ° C. and annealing is performed in an ozone atmosphere or the like to obtain a silicon oxide film.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記ＨＴＯ膜
を製造する方法の場合には、基板面の段差部分における
ＨＴＯ膜のステップカバレッジが悪く、膜がオーバーハ
ング形状になるという欠点があると共に、その成膜速度
が遅いため生産性が悪いという問題がある。一方、ＴＥ
ＯＳとオゾンを常圧で反応させる方法は、生成された膜
のステップカバレッジは良好であり、成膜速度も従来の
ＴＥＯＳを用い基板温度７００〜８００°Ｃで減圧ＣＶ
Ｄにより形成したシリコン酸化膜に比べて２０〜３０倍
速いという利点がある。しかし、この方法によれば、シ
リコン酸化膜のアニール後の膜収縮率がやや大きいた
め、膜の収縮により半導体基板にストレスを与え、結晶
欠陥をもたらすおそれがある。本発明は、上記した問題
点を解決しようとするもので、ステップカバレッジが良
く、成膜速度が速く、かつアニール後の膜収縮率が小さ
いシリコン酸化膜の製造方法を提供することを目的とす
る。However, the method of manufacturing the HTO film has a drawback that the step coverage of the HTO film at the step portion on the substrate surface is poor and the film has an overhang shape. There is a problem that productivity is poor because the film formation speed is low. On the other hand, TE
The method of reacting the OS and ozone at normal pressure has a good step coverage of the formed film, and the film formation rate is the same as that of the conventional TEOS.
There is an advantage that it is 20 to 30 times faster than the silicon oxide film formed by D. However, according to this method, since the film shrinkage rate of the silicon oxide film after annealing is slightly large, stress may be applied to the semiconductor substrate due to shrinkage of the film to cause crystal defects. An object of the present invention is to provide a method for manufacturing a silicon oxide film having good step coverage, a high film forming rate, and a small film shrinkage rate after annealing, in order to solve the above problems. .
【０００４】[0004]
【課題を解決するための手段】上記した目的を達成する
ために、上記請求項１に係る発明の構成上の特徴は、所
定パターンの絶縁膜を設けた基板上にトリエトキシシラ
ンとオゾンとを、トリエトキシシラン１モルに対してオ
ゾン５〜１０モルの割合で供給して２００〜５００℃の
雰囲気中にて熱分解ＣＶＤにより反応させて８５０°Ｃ
でアニールを行った場合の膜収縮率〔（アニール前膜厚
−アニール後膜厚）／（アニール前膜厚）×１００〕を
１０％以下としたシリコン酸化膜を成長させる膜形成工
程と、シリコン酸化膜を異方性エッチング法によりエッ
チングを行うことにより、絶縁膜の側端部にシリコン酸
化膜のサイドウォールを設けるサイドウォール形成工程
とを設けたことにある。In order to achieve the above object, a structural feature of the invention according to claim 1 is that triethoxysilane is provided on a substrate provided with an insulating film having a predetermined pattern. Ozone and ozone are added to one mole of triethoxysilane.
850 ° C. by reacting by pyrolysis CVD in an atmosphere of 200 to 500 ° C. supplied in a ratio of 5 to 10 moles .
Film shrinkage rate when annealing at [(thickness before annealing)
− (Thickness after annealing) / (thickness before annealing) × 100]
A film forming step of growing a silicon oxide film having a thickness of 10% or less, and a silicon oxide film is etched by an anisotropic etching method to form a sidewall of the silicon oxide film at a side end of the insulating film. Process.
【０００５】また、上記請求項２に係る発明の構成上の
特徴は、半導体装置において、前記請求項１に記載の製
造方法により製造されたサイドウォールを設けたことに
ある。Further, a structural feature of the invention according to claim 2 is that a sidewall manufactured by the manufacturing method according to claim 1 is provided in a semiconductor device.
【０００６】上記各請求項に係る発明において、トリエ
トキシシランの反応容器内への供給は、ヘリウム、アル
ゴン、窒素等の不活性ガスによるバブリングによってト
リアルコキシシランを気化させることにより行われる
か、または加熱により気化させて前記不活性ガス等の希
釈ガスと共に供給する方法が一般的である。[0006] In the invention according to the above claim, tri et
Supply to butoxy silane in the reaction vessel, helium, argon, diluent gas such as the inert gas is vaporized by bubbling with an inert gas or is effected by vaporizing the trialkoxysilane, or by heating such as nitrogen It is common to supply them together.
【０００７】もう一方の反応ガスであるオゾンは、酸素
で希釈して反応容器内に供給するのが一般的である。そ
して、オゾン濃度は、１０ｗｔ％を越えない範囲が好ま
しく、３〜７ｗｔ％が特に好ましい。オゾン濃度があま
り高いと、気相での微粒子の発生が激しくなり、基板上
へ付着するおそれがあり、また、オゾン濃度があまり低
いと、反応速度が遅くなり実用的でなくなる。オゾンと
トリアルコキシシランの反応容器への供給割合は、トリ
アルコキシシラン１モルに対してオゾン０．５〜１０モ
ルが好ましく、さらに好ましくは、１〜５モルである。[0007] The other reaction gas, ozone, is generally diluted with oxygen and supplied to the reaction vessel. The ozone concentration is preferably in a range not exceeding 10 wt%, particularly preferably 3 to 7 wt%. If the ozone concentration is too high, the generation of fine particles in the gas phase becomes intense and may adhere to the substrate. On the other hand, if the ozone concentration is too low, the reaction speed becomes slow and impractical. The supply ratio of ozone and trialkoxysilane to the reaction vessel is preferably 0.5 to 10 mol, more preferably 1 to 5 mol of ozone per mol of trialkoxysilane.
【０００８】また、上記基板の温度は、成膜速度及び膜
中水分量に関係するが、好ましくは２００℃から５００
℃、更に好ましくは２８０℃から４５０℃、特に好まし
くは３５０℃から４２０℃である。２００℃未満では、
高温の熱処理による膜収縮が大きくなる場合があり、５
００℃を越えると膜形成速度が低下する恐れが有り、効
率的とは言えなくなる。反応容器内の圧力は、常圧であ
っても減圧であっても良いが、好ましくは８００〜１０
０ｍｍＨｇ、さらに好ましくは８００〜６００ｍｍＨｇ
である。The temperature of the substrate is related to the film formation rate and the amount of water in the film.
° C, more preferably 280 ° C to 450 ° C, particularly preferably 350 ° C to 420 ° C. Below 200 ° C,
The film shrinkage due to high temperature heat treatment may increase,
If the temperature exceeds 00 ° C., there is a possibility that the film formation speed is reduced, and it is not efficient. The pressure in the reaction vessel may be normal pressure or reduced pressure.
0 mmHg, more preferably 800 to 600 mmHg
It is.
【０００９】[0009]
【発明の作用・効果】上記のように構成した請求項１に
係る発明においては、ゲート絶縁膜等の所定パターンの
絶縁膜上にトリアルコキシシランとオゾンを例えば２０
０〜５００°Ｃの低温雰囲気にて熱分解ＣＶＤにより反
応させてシリコン酸化膜を成長させたことにより、基板
上に成長速度が速くかつ絶縁膜の段差部分におけるステ
ップカバレッジの良好なシリコン酸化膜が形成される。
また、このシリコン酸化膜は、膜質が緻密に形成され、
特に、３５０〜４２０°Ｃの範囲において得られた膜
は、膜質が非常に緻密であるため高温の熱処理による膜
収縮も少なく、具体的には、８５０°Ｃでアニールを行
った場合の膜収縮率〔（アニール前膜厚−アニール後膜
厚）／（アニール前膜厚）×１００〕を１０％以下とす
ることができる。このシリコン酸化膜を異方性エッチン
グ法によりエッチングを行うことにより、絶縁膜の側端
部に良好な形状のシリコン酸化膜のサイドウォールが形
成される。このサイドウォールは、膜質が緻密であり、
その後の高温熱処理により膜収縮をほとんど生じないの
で、基板にストレスを与えることがない。従って、基板
に結晶欠陥が発生することもなく、基板及び膜の信頼性
が確保される。According to the first aspect of the present invention, trialkoxysilane and ozone are applied onto an insulating film having a predetermined pattern such as a gate insulating film.
By growing the silicon oxide film by the thermal decomposition CVD in a low temperature atmosphere of 0 to 500 ° C., the growth rate is high on the substrate and the step coverage in the step portion of the insulating film is good. Silicon oxide film is formed.
This silicon oxide film has a dense film quality,
In particular, 350 to 420 films obtained in the range of ° C, the film quality film shrinkage rather low due to very dense and is for high-temperature heat treatment, specifically, line annealed at 850 ° C
Film shrinkage rate [(film thickness before annealing-film after annealing)
(Thickness) / (thickness before annealing) × 100] is set to 10% or less.
Can be By etching this silicon oxide film by an anisotropic etching method, a sidewall of a silicon oxide film having a good shape is formed at a side end of the insulating film. This sidewall has a dense film quality,
Subsequent high-temperature heat treatment hardly causes film shrinkage, so that stress is not applied to the substrate. Therefore, no crystal defects occur in the substrate, and the reliability of the substrate and the film is ensured.
【００１０】また、上記のように構成した請求項２に係
る発明においては、半導体装置例えば絶縁ゲート型半導
体装置のゲート絶縁膜等の側部に前記請求項１に記載の
製造方法により膜質の緻密なサイドウォールを設けたこ
とにより、その後の高温の熱処理によってもシリコン酸
化膜の収縮はほとんどなく、従って下地半導体基板に熱
ストレス等を与えることもない。このため、絶縁ゲート
型半導体装置等はサイドウォールの形成によってその特
性が劣化することもなく、高歩留りで製造されると共に
高い信頼性が得られる。[0010] In the invention according to claim 2 configured as described above, the film quality of the semiconductor device, for example, the gate insulating film of an insulated gate type semiconductor device, is improved by the manufacturing method according to claim 1. The provision of the side walls hardly causes the silicon oxide film to shrink even by the subsequent high-temperature heat treatment, and therefore does not give thermal stress to the underlying semiconductor substrate. Therefore, the characteristics of the insulated gate semiconductor device and the like are not degraded by the formation of the sidewalls, and the device is manufactured at a high yield and high reliability is obtained.
【００１１】[0011]
【実施例】以下、本発明の一実施例について図面により
説明する。まず、図１（ａ）に示すように、絶縁ゲート
型半導体装置のゲート部１１及びフィールド絶縁膜１２
の形成されたシリコン半導体基板（以下、シリコン基板
と記す）１０をＣＶＤ装置の反応容器内に設けたサセプ
タに載置する。なお、ＣＶＤ装置の形式としては、縦
型、横型、パンケーキ型、ベルトコンベア型等のいずれ
を用いてもよい。つぎに、サセプタを加熱することによ
りを、シリコン基板１０を４００℃に保持する。ここ
で、反応容器内に４５℃に加熱したトリエトキシシラン
を流量２．０Ｌ／ｍｉｎのＮ2 ガスによりバブリングし
て導入する。同時に、オゾン濃度４．５％の酸素を流量
７．５Ｌ／ｍｉｎの割合で反応容器内に導入する。反応
容器内にてトリエトキシシランとオゾンとを５分間反応
させることにより、シリコン基板１０上に膜厚０．７５
μｍのシリコン酸化膜１３が形成される。このシリコン
酸化膜１３は、図１（ｂ）に示すように、ゲート部１１
及びフィールド絶縁膜１２の段差部分におけるステップ
カバレッジが良好に形成される。さらに、このシリコン
酸化膜１３を反応イオンエッチング法等の異方性エッチ
ングによりエッチングを行うことにより、図１（ｃ）に
示すように、ゲート部１１の側部に良好な形状のシリコ
ン酸化膜のサイドウォール１４が形成される。An embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1A, a gate portion 11 and a field insulating film 12 of an insulated gate semiconductor device are formed.
The silicon semiconductor substrate (hereinafter, referred to as a silicon substrate) 10 on which is formed is placed on a susceptor provided in a reaction vessel of a CVD apparatus. As a type of the CVD apparatus, any of a vertical type, a horizontal type, a pancake type, a belt conveyor type, and the like may be used. Next, the silicon substrate 10 is kept at 400 ° C. by heating the susceptor. Here, triethoxysilane heated to 45 ° C. is introduced into the reaction vessel by bubbling with N 2 gas at a flow rate of 2.0 L / min. At the same time, oxygen with an ozone concentration of 4.5% is introduced into the reaction vessel at a flow rate of 7.5 L / min. By reacting triethoxysilane and ozone for 5 minutes in a reaction vessel, a 0.75
A μm silicon oxide film 13 is formed. As shown in FIG. 1B, the silicon oxide film 13
In addition, the step coverage in the step portion of the field insulating film 12 is favorably formed. Further, by etching the silicon oxide film 13 by anisotropic etching such as a reactive ion etching method, as shown in FIG. A sidewall 14 is formed.
【００１２】ここで、以上のように形成されたシリコン
酸化膜１３の膜質を調べるために、シリコン酸化膜１３
をＮ2 雰囲気中で３００°Ｃ，４５０°Ｃ，８５０℃で
各々２０分間アニールし、その後、膜収縮率の測定を行
った。膜収縮率の測定結果を図２に示す。ここで、膜収
縮率は、（アニール前膜厚−アニール後膜厚）／（アニ
ール前膜厚）×１００で表されるものとする。この結
果、８５０°Ｃでアニールを行った場合の膜収縮率は、
５％程度と大幅に低減することができた。また、図２に
は、トリエトキシシランとオゾンとを用い、基板温度２
５０°Ｃ，及び３００°Ｃとしたときに得られたシリコ
ン酸化膜について、上記条件によるアニール後の膜収縮
率を調べた結果も示す。Here, in order to examine the film quality of the silicon oxide film 13 formed as described above, the silicon oxide film 13
Was annealed at 300 ° C., 450 ° C., and 850 ° C. for 20 minutes in an N 2 atmosphere, and then the film shrinkage was measured. FIG. 2 shows the measurement results of the film shrinkage. Here, the film shrinkage ratio is represented by (film thickness before annealing−film thickness after annealing) / (film thickness before annealing) × 100. As a result, the film shrinkage when annealing at 850 ° C.
It was able to be greatly reduced to about 5%. FIG. 2 shows a substrate temperature of 2 using triethoxysilane and ozone.
The results of examining the film shrinkage after annealing under the above conditions for the silicon oxide films obtained at 50 ° C. and 300 ° C. are also shown.
【００１３】以上のように、シリコン酸化膜の膜収縮率
の大幅な低減が達成されたことにより、高温の熱処理に
よるシリコン基板に対する熱ストレスの発生が抑えら
れ、シリコン基板における結晶欠陥の発生が防止され
る。その結果、このシリコン酸化膜をゲート部のサイド
ウォールに適用した絶縁ゲート型電界効果トランジスタ
は、特性が劣化することがなく、高歩留りで製造される
と共にその信頼性が高められる。また、本実施例に係る
シリコン酸化膜の製造方法によれば、従来のＴＥＯＳと
オゾンを常圧で反応させる方法よりもさらに膜形成速度
が速いので、半導体装置の製造におけるスループットの
改善を図ることもできる。As described above, since the film shrinkage of the silicon oxide film is significantly reduced, the occurrence of thermal stress on the silicon substrate due to the high-temperature heat treatment is suppressed, and the generation of crystal defects in the silicon substrate is prevented. Is done. As a result, the insulated gate type field effect transistor in which this silicon oxide film is applied to the side wall of the gate portion is not deteriorated in characteristics, is manufactured at a high yield, and has high reliability. Further, according to the method of manufacturing a silicon oxide film according to the present embodiment, the film formation speed is higher than in the conventional method of reacting TEOS with ozone at normal pressure, so that the throughput in manufacturing a semiconductor device is improved. Can also.
【００１４】さらに、上記実施例に係るシリコン酸化膜
の製造方法を、絶縁ゲート型電界効果トランジスタのゲ
ート部へのサイドウォールの形成に限らず、その他の半
導体装置のサイドウォールの形成に用いてもよい。Further, the method of manufacturing a silicon oxide film according to the above embodiment is not limited to the formation of a sidewall at the gate portion of an insulated gate field effect transistor, but may be used to form a sidewall of another semiconductor device. Good.
【図１】本発明を適用した絶縁ゲート型電界効果トラン
ジスタのゲート部のサイドウォール製造工程を示す断面
図である。FIG. 1 is a sectional view showing a step of manufacturing a sidewall of a gate portion of an insulated gate field effect transistor to which the present invention is applied.
【図２】シリコン酸化膜の各種基板温度に対する膜収縮
率とアニール温度との関係を示すグラフである。FIG. 2 is a graph showing a relationship between a film shrinkage ratio and an annealing temperature with respect to various substrate temperatures of a silicon oxide film.
１０；シリコン基板、１１；ゲート部、１２；フィール
ド絶縁膜、１３；シリコン酸化膜、１４；サイドウォー
ル。10; silicon substrate, 11; gate portion, 12; field insulating film, 13; silicon oxide film, 14;
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−153045（ＪＰ，Ａ) 特開 平３−297146（ＪＰ，Ａ) 特開 平４−74424（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 21/316 H01L 21/336 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-153045 (JP, A) JP-A-3-297146 (JP, A) JP-A-4-74424 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 29/78 H01L 21/316 H01L 21/336
Claims (2)
トリエトキシシランとオゾンとを、トリエトキシシラン
１モルに対してオゾン５〜１０モルの割合で供給して２
００〜５００℃の雰囲気中にて熱分解ＣＶＤにより反応
させて、８５０°Ｃでアニールを行った場合の膜収縮率
〔（アニール前膜厚−アニール後膜厚）／（アニール前
膜厚）×１００〕を１０％以下としたシリコン酸化膜を
成長させるシリコン酸化膜形成工程と、 前記シリコン酸化膜を異方性エッチング法によりエッチ
ングを行うことにより、前記絶縁膜の側端部にシリコン
酸化膜のサイドウォールを設けるサイドウォール形成工
程とを設けたことを特徴とするサイドウォールの製造方
法。1. A and triethoxysilane and ozone on a substrate provided with an insulating film having a predetermined pattern, triethoxysilane
Ozone is supplied at a rate of 5 to 10 moles per mole, and 2
The film shrinkage when annealing is performed at 850 ° C. by reacting by pyrolysis CVD in an atmosphere of 00 to 500 ° C.
[(Thickness before annealing-Thickness after annealing) / (Before annealing)
Forming a silicon oxide film having a thickness of less than or equal to 10%, and etching the silicon oxide film by an anisotropic etching method to form a silicon oxide film on a side edge of the insulating film. A sidewall forming step of providing a sidewall of a silicon oxide film.
成されたサイドウォールを設けたことを特徴とする半導
体装置。2. A semiconductor device provided with a sidewall formed by the manufacturing method according to claim 1.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13662093A JP3203531B2 (en) | 1993-05-14 | 1993-05-14 | Sidewall manufacturing method and semiconductor device |
| AU69478/94A AU6947894A (en) | 1993-05-14 | 1994-05-13 | Method of manufacturing side walls and semiconductor device having side walls |
| PCT/US1994/005315 WO1994027316A1 (en) | 1993-05-14 | 1994-05-13 | Method of manufacturing side walls and semiconductor device having side walls |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13662093A JP3203531B2 (en) | 1993-05-14 | 1993-05-14 | Sidewall manufacturing method and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06326125A JPH06326125A (en) | 1994-11-25 |
| JP3203531B2 true JP3203531B2 (en) | 2001-08-27 |
Family
ID=15179566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13662093A Expired - Lifetime JP3203531B2 (en) | 1993-05-14 | 1993-05-14 | Sidewall manufacturing method and semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3203531B2 (en) |
| AU (1) | AU6947894A (en) |
| WO (1) | WO1994027316A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61226965A (en) * | 1985-04-01 | 1986-10-08 | Hitachi Ltd | Mos field-effect transistor |
| US4845054A (en) * | 1985-06-14 | 1989-07-04 | Focus Semiconductor Systems, Inc. | Low temperature chemical vapor deposition of silicon dioxide films |
| JPS63150965A (en) * | 1986-12-15 | 1988-06-23 | Toshiba Corp | Manufacture of semiconductor device |
| US5010029A (en) * | 1989-02-22 | 1991-04-23 | Advanced Micro Devices, Inc. | Method of detecting the width of spacers and lightly doped drain regions |
| JPH04186732A (en) * | 1990-11-21 | 1992-07-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JP3038566B2 (en) * | 1991-12-06 | 2000-05-08 | 株式会社高純度化学研究所 | Method of manufacturing silicon oxide film for semiconductor device |
-
1993
- 1993-05-14 JP JP13662093A patent/JP3203531B2/en not_active Expired - Lifetime
-
1994
- 1994-05-13 WO PCT/US1994/005315 patent/WO1994027316A1/en not_active Ceased
- 1994-05-13 AU AU69478/94A patent/AU6947894A/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| WO1994027316A1 (en) | 1994-11-24 |
| JPH06326125A (en) | 1994-11-25 |
| AU6947894A (en) | 1994-12-12 |
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