JP3209560B2 - Interrupt management method for microprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt management method for a microprocessor system. 2. Description of the Related Art In recent years, many microprocessor systems have been used. In a microprocessor system, an external device or an external device (hereinafter, collectively referred to as an external device) while a microprocessor (hereinafter, referred to as a CPU) is executing a program process. Do)
In many cases, when an interrupt request is issued from the user, the program processing being executed is interrupted to process the interrupt request from the external device.

[0002] Since the content processed by an external request differs for each external device, a user creates an interrupt processing routine (hereinafter, referred to as an interrupt handler) for each external device, and when an interrupt request is made, A method is used in which a CPU identifies an external device that has issued an interrupt request, calls a corresponding interrupt handler, and performs processing.

When the CPU interrupts the program processing being executed due to the occurrence of an external interrupt, the address of the program to be resumed and the contents of the internal register of the CPU used so far are saved before the interrupt processing is performed. Is executed, and when the interrupt processing is completed, these registers are restored to the original state and the program is restarted. However, in the interrupt handler, saving the internal register is described in the interrupt handler. In order to complicate the creation, these processes are usually performed by an interrupt management function of an OS (operating system).

However, in the currently popular microprocessor system, the CPU which receives the interrupt request activates the interrupt handler by hardware, so if the interrupt handler starts the interrupt processing as it is. Then, the OS cannot know the occurrence of the interrupt and cannot save the registers. Therefore, the OS is called from the interrupt handler side (called a system call).
A method is used in which the OS performs a process such as saving a register, and after these processes are completed, the process is returned to the interrupt handler again to perform the interrupt process. At the end of the interrupt processing, a system call is similarly made from the interrupt handler, and the OS
Resumes the interrupted program after restoring the registers and the like. Note that the OS can manage the state of the interrupt processing by this system call.

On the other hand, an interrupt handler created by a user is usually written in a high-level language at present. However, if the interrupt handler is described in a high-level language including the system call, a module ( handler)
The operation of the stack and the rewriting of some registers in the CPU are always performed at the head of the. Therefore, the register of the CPU is used before the contents are saved. A similar problem occurs at the end of the interrupt processing.

In order to avoid such a situation, it is necessary to describe a part before and after a system call using an assembler language instead of a high-level language. However, at present, description in the assembler language is not general, so that it is difficult to accurately describe it. In addition, if there is a branch or the like inside the interrupt handler, an error is likely to occur in the process at the time of termination.

For this reason, there is a need for a microprocessor system interrupt management method in which an interrupt handler can be described only in a high-level language and processing errors are unlikely to occur.

[0008]

2. Description of the Related Art FIG. 6 is a block diagram of a microprocessor system, FIG. 7 is a block diagram of a conventional system, FIG. 8 is a block diagram of a conventional memory, FIG. FIG. 2 is a flowchart of a conventional technique.

FIG. 6 shows an example of the configuration of a microprocessor system to which the present invention is applied. CP in FIG.
U1 is an 8086 series microprocessor (CP
3 shows an example of a microprocessor system configured using U), but the CPU 1
(Random access memory) 4, ROM (read only memory) 5, interrupt controller (hereinafter referred to as PIC) 2
And eight external devices (I / O) 3 _{-1 to} 3 _-8 .

When two or more of the eight external devices 3 _{-1 to} 3 _-8 simultaneously receive interrupt requests via the IR ₀ to IR ₇ lines, the PIC 2 compares priorities and the like. It has a role of arbitrating so that only the interrupt request is made to the CPU 1, and the interrupt request is sent to the CPU 1 through the INTR line. Eight external devices can be connected to one PIC2, but up to two
Up to 56 external devices can be connected.

FIG. 7 shows a system configuration of a portion related to interrupt processing of a microprocessor system in the prior art, and FIG. 8 shows an example of a storage state in a memory (not shown in FIG. 7) of each part in FIG. As shown in FIG.
The prior art will be described below. 7 and FIG.
Only the external devices 3 _{-1 to} 3 _-2 are shown.

A part of the components shown in FIG. 7 is stored in a memory composed of a RAM and a ROM as shown in FIG.
The CPU 1 operates each function while reading these. Many programs can be stored in either RAM or ROM, but here, for convenience of explanation, ROM
The OS 60 stores only an interrupt handler activation processing unit 61, an interrupt handler termination processing unit 62, and an execution management unit 63, and an interrupt handler 81 and an application program (hereinafter referred to as AP) 82 are stored in a RAM. Shall be stored. In the following, when the term “OS” is simply used, the term
60 or a part thereof (mainly the execution management unit 63).

Now, assuming that the CPU 1 is executing an instruction at the address 1200 of the AP 82 in cooperation with the execution management unit 63 of the OS, a program counter (hereinafter referred to as P
1a is the 12th address following the address being executed as shown in FIG.
It points to address 01.

[0014] There is an interrupt request from the external device _3-1 in this state, confirms that the PIC2 are compared and with priority other interrupt requests to prioritize the interrupt request, which CPU
Tell 1 Since the content of the interrupt request differs for each external device, it is necessary to identify the external device from which the interrupt request was issued.However, the external device that issued the interrupt request must be identified by the interrupt number. and then, to the external device 3 _-1 and 3 _-2 interrupt requests, respectively interrupt number 1 and the interrupt number 2.

An interrupt vector area 71 shown in FIG. 8 is a memory area storing a head address (called a vector) of a memory area in which an interrupt handler 81 for defining the interrupt processing content of each interrupt number is stored. And stores 4 bytes of address information (2 bytes for each segment and offset) for each interrupt number.

Since up to 256 external devices can be connected, 256 areas having numbers from 0 to 255 are reserved in the interrupt vector area 71. This number is called a type number, and the interruption to each type number is called a type 0 interrupt to a type 255 interrupt. Actually, the range of type numbers that can be used by the user is limited, but here, for convenience of explanation, the explanation will be made with the interruption number 1 corresponding to the type 0 interruption and the interruption number 2 corresponding to the type 1 interruption. .

For example, addresses 00000 to 003FF (hexadecimal) are used as the physical addresses (byte addresses) of the vector area 71, and the start address of 4 bytes assigned to each type number is used as the address. Therefore, the interrupt number 1 accesses the interrupt vector area 71 using the address 00000 and the interrupt number 2 uses the address 00004.

[0018] interrupt request of the external device _3-1 is transmitted to CPU1 via the PIC2, CPU1 is INTA in Figure 6
The line informs that the interrupt request has been accepted, and the PIC 2 sends the type 0 interrupt address information "00000" as information for identifying the interrupt request source. With this, CPU1
Access address 00000 and read its contents.

Assuming that the start address of the interrupt handler stored in the type 0 interrupt is 3000, the CPU 1 shifts to this address, that is, the processing of the interrupt handler 81. Back up information.

In FIG. 8, the memory area of the save destination is secured in the stack area 83 on the RAM, and the stack pointer (hereinafter referred to as SP) 1b in the CPU 1 points to the address where the save information is stored. The information to be saved is an address to be restored when the interrupt processing is completed. In this case, the address is "1201" of the address pointed to by the PC 1a.

When the CPU 1 stores "1201" in the stack area 83, SP1b moves to the next address and prepares for a higher-order interrupt. After this is completed, the PC 1a jumps to address 3000, which is the start address of the interrupt handler for interrupt number 1, and the processing shifts to the interrupt handler 81. The processing up to this point is O
S60 is performed by the CPU 1 without involvement.

When the interrupt handler 81 starts processing, it first makes the above-mentioned system call, so that the CPU 1 saves registers (not shown) by the interrupt handler activation processing unit 61 constituting a part of the OS 60, that is, the AP 82 Starts saving the contents of the register used by.

At this time, the OS 60 is started from the interrupt handler 81, but since the OS 60 is not informed of which external device the started interrupt handler belongs to, the PIC 2 accesses the PIC 2 and its internal register (not shown). Confirm by reading. This enables the OS to manage which interrupt process is currently being performed, and can cope with a case where multiple interrupts are performed. However, this analysis of the interrupt factor takes a long time when the number of external devices is large and the PICs 2 are connected in cascade.
This causes the overhead of S to increase.

When the saving of the internal registers and the analysis of the interrupt cause are completed, the CPU 1 re-executes the processing by the interrupt handler.
The process proceeds to 81, where substantial interrupt processing is performed by the interrupt handler 81. If a high-order interrupt occurs during execution of the interrupt process by the interrupt handler 81, the CPU 1 and the OS activate the high-order interrupt handler by the same processing as described above, and execute the interrupt process. And return to the previous interrupt handler. The OS always manages the interrupt state in preparation for such multiple interrupts.

When the interrupt processing is completed, the interrupt handler 81 makes a system call again, whereby the interrupt handler termination processing unit 62 of the OS performs the restoration of the registers and the termination processing of the PIC 2, and is stored in the stack area 83. AP82 which was interrupted by transferring the address information "1201" to PC1a
Is restarted.

Although the description has been omitted above, since the memory space that can be used by the current microprocessor system is extremely large, as a means for avoiding an increase in the number of digits of the address, the segment of the address (when distinguishing it from the others) is used. Is called a data segment) and an offset, and a segment is allocated to each task in advance. As a result, each program can be created using only offsets without being aware of segments. However, the application
In the case of shifting from the program processing to the interrupt processing, the segments are changed. Therefore, in the event of an interrupt, a procedure for replacing the segments is determined between the interrupt handler 81 and the OS 60.

FIG. 9 shows a transition state of processing at the time of interrupt processing. As shown in FIG. 9, when an interrupt request is generated during execution of AP processing, processing of the AP is interrupted and an interrupt handler is executed. Is started. When activated, the interrupt handler calls the OS by a system call, and when the OS finishes saving a register or the like, execution is transferred from the OS to execute the original interrupt processing. When the interrupt processing is completed, a system call is performed again, and thereafter, the OS resumes the register and resumes the interrupted AP processing.

FIG. 10 is a flow chart of the processing of the CPU and the OS described above. S11 to S14 and S21 to S23 are symbols indicating the steps of the flow. FIG. 10 (1) shows the flow when the interrupt handler is activated. At the start of the interrupt processing, the interrupt handler is activated by the interrupt vector as shown in FIG.
11) In response to a system call from the interrupt handler, the interrupt handler activation processing unit of the OS stores the CPU internal register (S12) and analyzes the cause of the interrupt (S13), and shifts the processing to the interrupt handler (S14). ) End the processing.

FIG. 10 (2) shows a flow when the interrupt handler is terminated. The interrupt handler termination processing unit notified of the termination of the processing by the system call from the interrupt handler performs termination processing. If the interrupt has been performed, the address of the interrupted interrupt handler stored in the stack area is returned to the management area (S21), and the PIC2 is terminated (S2
2) and the internal register is restored (S23), and the interrupted processing is resumed.

[0030]

As described above, in the prior art, the interrupt processing is performed to the interrupt handler created by the user using the interrupt factor analysis function, the register storage function, and the interrupt state management function of the OS. It has the following problems.

(1) The interrupt handler created by the user performs a system call after startup to cause the OS to save registers and the like. However, if the interrupt handler is described in a high-level language, it is processed first in the system call. It is not possible to create an interrupt handler using only high-level languages, because it may use registers that have not been saved and transfer the necessary values to

(2) If a branch or the like is performed in the interrupt handler, the termination processing is not performed accurately and an error is likely to occur in the system call at the time of termination. Need to create an interrupt handler.

(3) Since it is necessary to change the data segment at the time of an interrupt, a procedure for setting the data segment with the OS is required, and the creation of the interrupt handler becomes complicated.

(4) The OS overhead increases when analyzing the cause of the interrupt. That is, the prior art has the drawback that it is difficult to create an interrupt handler and the OS overhead is large.

The present invention makes it easy to create an interrupt handler,
An object of the present invention is to provide an interrupt management method with a small OS overhead.

[0036]

FIG. 1 is a basic configuration diagram of the present invention. In the figure, 1 is a microprocessor (CPU),
10 is an operating system (OS), 31 is an interrupt handler that defines processing for each interrupt factor in an external interrupt, and 20 is activated by the microprocessor 1 that has received an interrupt request from an external device (not shown). This is a double interrupt designating means for designating a software interrupt and transferring the processing to the operating system 10 before the processing shifts to the interrupt handler 31 when the processing is shifted to the interrupt handler 31.

Reference numeral 11 denotes an analysis of an interrupt factor and a check of internal registers (not shown) of the microprocessor 1 when the processing is shifted through the double interrupt designating means 20 in the operating system 10. After saving,
Interrupt handler activation processing means for activating the interrupt handler 31, 12 in the operating system 10,
When the end of the interrupt processing is notified from the interrupt handler 31, the return of the internal registers and the end processing of the interrupt to the external device are performed, and then the interrupt handler for resuming the interrupted program processing is ended. Processing means.

[0038]

In FIG. 1, when the CPU 1 executing the program processing receives an interrupt request from an external device via the OS 10, the executing program processing is interrupted and the double interrupt specifying means 20 is accessed.

The double interrupt designating means 20 does not directly inform the CPU 1 of the address where the interrupt handler 31 is stored.
Specify execution of soft interrupt. Therefore, the processing is not directly transferred to the interrupt handler 31 by the interrupt request from the external device, and the soft interrupt processing is started.

The software interrupt processing is performed prior to the external interrupt. At this time, instead of the interrupt handler 31 created by the user, the interrupt handler activation processing means 11 having the role of the interrupt processing inside the OS 10 Specify the address where is stored. Thereby, when the interrupt request is made, the CPU 1
The processing is transferred to the OS 10 without directly transferring the processing to the interrupt handler 31 due to the hardware operation.

The interrupt handler activation processing means 11 in the OS 10 to which the processing has been transferred analyzes the cause of the interrupt and saves the internal registers of the CPU 1, and then activates the interrupt handler 31. The external device that has issued the interrupt request is identified by the analysis of the interrupt factor, and the OS can thereafter manage the interrupt status. However, the analysis of the interrupt factor requires access to the external device. It is done in a simple way (details later).

The activated interrupt handler 31 executes the interrupt processing, and when the processing ends, notifies the interrupt handler end processing means 12 in the OS 10 of the end of the interrupt processing. The interrupt handler termination processing means 12 resumes the interrupted program processing after performing the restoration of the internal registers and the interruption termination processing for the external device.

As described above, in the configuration of FIG. 1, when an external interrupt occurs, the CPU 1 does not directly transfer the processing to the interrupt handler 31 but the interrupt handler activation processing means 11 in the OS 10
Then, after saving the internal registers and analyzing the cause of the interrupt, the interrupt handler 31 is started.

Therefore, the interrupt handler 31 does not need to request the saving of registers or the like by a system call, and it is possible to create only the contents of the interrupt processing in a high-level language. In addition, since the analysis of the interrupt factor in the OS is simplified, the overhead of the OS is reduced.

[0045]

FIG. 2 is a system configuration diagram of an embodiment of the present invention, FIG. 3 is a memory configuration diagram of an embodiment of the present invention, FIG. 4 is a diagram for explaining a process transition state of the embodiment of the present invention, and FIG. It is a flow figure of the example of the present invention.

Throughout the drawings, the same symbols indicate the same objects, 1 is a microprocessor (CPU), 1a is a program counter (PC), 1b is a stack pointer (SP),
2 interrupt controller _{(PIC), 3- 1, 3-} 2 is an external device, 10 OS, 11 to 13 in the respective sections constituting the OS 10, 11 interrupt handler activation processing section, 12 end interrupt handler Processing unit, 13 is execution management unit , 14 is interrupt handler address table
Is Le.

Numerals 21 and 22 are parts constituting the double interrupt designating section 20, 21 is an interrupt vector area, and 22 is a double interrupt designating table. 31 is an interrupt handler, 32 is an application program (AP), and 33 is a stack area provided on the RAM.

FIG. 2 is a block diagram of a microprocessor system according to an embodiment of the present invention using an 8086 series microprocessor as the CPU 1. For convenience of explanation, FIGS. 2 and 3 show only two external devices 3 _-1 and 3 _-2 . Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2 and 3, but the description of the same parts as those of the related art will be omitted.

Now, the CPU 1 executes A under the management of the OS 10.
A running 1200 address of P32, PC1a it is assumed that there is an interrupt request from the external device _3-1 in a state in which points to the next address 1201. When PIC2 transmits this to CPU1, C
PU1 saves the address information "1201" pointed to by PC1a in the stack area 33 pointed to by SP1b as the restart address of the AP32 to be interrupted, as in the prior art. At the same time, SP1b proceeds to the next address in the stack area 33,
Prepare for multiple interrupts.

Next, as in the prior art, the CPU 1 accesses the type 0 address of the interrupt vector area 21 and reads out the stored address information "12340". This moves PC1a to address 12342, which is next to address 12340.
The address 12340 is different from the prior art, and is not the head address of the interrupt handler 23 corresponding to the interrupt number, but the address corresponding to the interrupt number 1 of the double interrupt designation table 22.

The double interrupt designation table 22 is prepared by the number of necessary interrupt numbers, but the memory corresponding to each interrupt number stores the same contents, that is, the instruction of the soft interrupt. This soft interrupt has a higher priority than an interrupt from an external device. However, this interrupt also accesses the interrupt vector area 21 in the same manner as the external interrupt, and accesses the interrupt vector area 21 at the beginning of the memory area where the processing routine is stored. You get the address. Here, it is set by a machine language that the type 255 (physical address is 003FC) is used for accessing the interrupt vector area 21 of the soft interrupt.

Since the double interruption has been performed by the software interruption, the address value "12342" to which the PC 1a has been shifted at the first interruption is stored in the stack area 33 pointed to by the SP 1b, and the SP 1b Moves to the next address.

The information obtained from the interrupt vector area 21 by the soft interrupt, for example, "20000" is the start address of the interrupt handler activation processing unit 11 which forms a part of the OS 10 as shown. The interrupt handler activation processing unit 11 is roughly divided into an interrupt factor analysis unit 11a and a register saving processing unit 11b, and the previous address "20000" is the first address of the interrupt factor analysis unit 11a. Here, the analysis of the interrupt factor is performed.

Since the start address of the interrupt handler for each interrupt number is stored in the interrupt factor analysis unit 11a at addresses at 2-byte intervals, if the interrupt number is calculated, "30000 + 2 ×
The address of the interrupt handler corresponding to the interrupt number can be determined by the expression (interrupt number) -2 ".

The interrupt number is obtained by subtracting “12340” of the address value stored at the head of the interrupt vector area 21 from the address value “12342” stored in the stack area 33 and dividing by 2. That is, the analysis of the interrupt factor is performed only by executing a simple operation, and there is no need to access an internal register (not shown) of the PIC 2, so that a large overhead does not occur in the OS.

In this example, "1" is obtained by the above operation, and it is identified that this interrupt is interrupt number 1. Processing from address 20,000 (interrupt factor analysis unit 11a)
In the above, the interrupt number 1 and the interrupt handler address
From the stable state 14, the processing can be shifted to the interrupt handler 31. Prior to this, the register saving processing unit 11b
The internal register of PU1 is saved.

The processing for saving the internal registers is the same as that performed by the system call from the interrupt handler in the prior art, but in the present invention, all the processing can be performed only inside the OS without involving the interrupt handler 31. Therefore, there is no need for the user to create an interrupt handler in consideration of saving registers. At this time, replacement of data segments is also performed (detailed description is omitted).

[0058] register storage processing unit 11b calls the interrupt handler 31 and such as register storage of the end, but this is split
The interrupt factor analysis unit 11a sets the interrupt number 1 and the interrupt handler address
The process is performed using the address value obtained from the table 14. If the address value is, for example, "3000", the process is moved to the address 3000, and the process by the interrupt handler 31 is started.

After the processing is transferred to the interrupt handler 31, if there is a higher-order interrupt request, the processing shifts to the interrupt processing. Therefore, the OS 10 needs to manage the interrupt state during the interrupt processing by the interrupt handler 31, that is, which external device requests the current interrupt processing. Enter the interrupt number identified by the factor analysis unit 11a as O
This is possible by storing it inside S.

As described above, since the interrupt handler 31 is started after all processes performed by the OS are completed, the internal handler of the CPU 1 is saved, or the assembler language is used for segment replacement. It is not necessary to describe a special procedure, and only the contents of the interrupt processing can be described using only a high-level language. As a result, the interrupt handler 31 can be handled in the same manner as a normal subroutine.

The interrupt handler 31 also terminates the interrupt processing.
Does not need to make any special description about the internal registers and segments, and is normally used when returning from a subroutine to the main routine, for example, using a RETURN instruction.
The processing can be returned to S, whereby the OS can know that the interrupt processing has been completed.

In response to an interrupt completion notification from the interrupt handler 31, the interrupt handler completion processing unit 12 of the OS performs a process such as restoring a register and resumes the interrupted process of the AP 32. The description is omitted because it is almost the same as the technology.

FIG. 4 shows the transition state of the processing described above. As shown in the figure, the interrupt handler is called after the CPU completes all the processing such as register saving during the interrupt processing. Therefore, the processing contents of the interrupt handler 23 become very simple.

FIG. 5 is a flowchart showing processing of the CPU and the OS when the interrupt handler is activated as described above.
1 to S5 indicate each step of the flow. If an interrupt occurs, the CPU unconditionally branches to the double interrupt specification table (S1) by hardware processing of the CPU, and then generates a type 255 software interrupt in the double interrupt specification table (S2). The handler activation processing unit analyzes the cause of the interrupt (S3) and saves the CPU internal register (S4).
When these processes are completed, an interrupt handler is activated (S5).

Although the detailed processing at the end of the processing of the interrupt handler is slightly different from that of the prior art as described above, since there is no difference in the flow chart, the description is omitted. As described above, the embodiment of the present invention has been described with reference to FIGS. 2 to 5. However, FIGS. 2 to 5 show only one embodiment of the present invention, and are not limited to those shown in the present invention. Of course not.

For example, while the above description has been made with reference to the 8086 series microprocessor as an example, the present invention is applicable to a microprocessor system using a microprocessor having a similar configuration regardless of the name of the microprocessor. Clearly there is.

Further, R in the memory configuration shown in FIG.
It is clear that the effect of the present invention does not change even if a part of the storage contents of the AM is transferred to the ROM, and it goes without saying that the addresses and the storage contents are not limited to those shown.
Further, the target for the OS to perform the save or change process is not limited to the registers and the data segments, but includes the same kind of components having other names. This does not exclude the modification of the configuration.

[0068]

As described above, according to the present invention, since the OS activates the interrupt handler after all processes such as saving the internal registers have been completed, the interrupt handler saves registers and stores data and data. There is no need to describe the procedure for segment replacement. Therefore, the user can describe all interrupt handlers that define the processing content of the external interrupt in a high-level language, and the possibility of erroneous processing due to simplification of the description decreases. Further, since the analysis of the interrupt factor is performed by a simple calculation without accessing the interrupt controller (PIC), the overhead of the OS is reduced.

That is, the present invention greatly contributes to improving the efficiency of creating an interrupt handler and the efficiency of interrupt processing in a microprocessor system that performs interrupt management.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a system configuration diagram of an embodiment of the present invention.

FIG. 3 is a diagram illustrating a memory configuration according to an embodiment of the present invention;

FIG. 4 is an explanatory diagram of a process transition state according to an embodiment of the present invention.

FIG. 5 is a flowchart of an embodiment of the present invention.

FIG. 6 is a block diagram of a microprocessor system.

FIG. 7 is a system configuration diagram of a conventional technology.

FIG. 8 is a memory configuration diagram of a conventional technology.

FIG. 9 is an explanatory diagram of a process transition state according to the related art.

FIG. 10 is a flowchart of a conventional technology.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Microprocessor (CPU) 1a Program counter (PC) 1b Stack pointer (SP) 2 Interrupt controller (PIC) _3-1 to _3-8 External device (I / O) 10 Operating system (OS) 11 Interrupt handler Start-up processing means 12 Interrupt handler termination processing means 13 Execution management unit 14 Interrupt handler address table 20 Double interrupt specification means 21 Interrupt vector area 22 Double interrupt specification table 31 Interrupt handler 32 Application program (AP) 33 Stack area

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Nobuo Atami 3-9-1-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Inside Fujitsu Communication Systems Co., Ltd. (56) References JP-A-2-158839 (JP, A JP-A-2-133828 (JP, A) JP-A-62-274434 (JP, A) JP-A-59-62937 (JP, A) JP-A-2-299030 (JP, A) JP-A 63-274 296140 (JP, A) JP-A-61-196336 (JP, A) JP-A-51-27745 (JP, A) Interface, Vol. 16, No. 6, CQ Publishing Co., Ltd. (1990), pp. 131-144 (Patent Office CSDB literature number: CSNW199800225001) C MAGAZINE, Vol. 2, No. 2. Nippon SoftBank Corp. (1990), pp. 86-92 (Patent Office CS DB Document No .: CSNW199800150012) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/46 G06F 13/24 CSDB (Japan Patent Office)

Claims (1)

(57) [Claims] When a microprocessor executing a program processing via an operating system receives an interrupt request from an external device, the microprocessor interrupts the program processing being executed and interrupts the processing for each interrupt factor. A microprocessor that causes an interrupt handler (31) that regulates processing to perform interrupt processing
In the system, when activated by the microprocessor (1) having received the interrupt request, a software interrupt is designated and the interrupt handler (3) is designated.
Before the process shift to 1), the operating system (10)
A double interrupt designating means (20) that shifts the processing to, and when the processing is shifted through the double interrupt designating means (20) in the operating system (10),
An interrupt handler activation processing means (11) for activating the interrupt handler (31) after analyzing an interrupt factor and storing the internal registers of the microprocessor (1), and the operating system (10) When the completion of the interrupt processing is notified from the interrupt handler (31), the internal registers are restored and the interrupt processing for the external device is performed, and then the interrupted program processing is resumed. An interrupt management method for a microprocessor system, comprising interrupt handler termination processing means (12) for causing the interrupt handler to terminate.