JPH0217822B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a procedure switching control method, and more particularly to a procedure switching control method in a multiprocessor type information processing device consisting of a plurality of processors that share at least a portion of a main storage device. be.

Prior Art Conventionally, in this type of multiprocessor system, mechanically it has only been possible to specify an execution processor for each job process.
In order to switch execution to a specific processor when switching procedures within one job process, it is necessary to program the switching process using a special dedicated instruction in the procedure immediately before switching. This special dedicated instruction differs from general software instructions in that the instruction code reflects internal system information such as the selection of the execution processor, and as a result, the instruction is dependent on a specific device. .

Therefore, after you have created software using the method described above by assigning different processors to several procedures, if you find it necessary to change the correspondence between the procedure and the processor for performance reasons, etc. The program had to be modified each time. Since the program referred to here is a user program seen from the system, it is in assembly language or machine language, and modification of the above program is usually done in assembly language or machine language in a translation program (compiler) that is a system program. , will be realized by modifying the intermediate language generation part. Although modifications to the compiler are carried out with careful consideration and in a supportive environment with specialized engineers, there is still a risk of damaging the credibility that has already been established.

In this way, the conventional method is quick response, economical,
In order to eliminate the need to modify the program due to safety issues, it is desirable to provide a simple and reliable means in advance and pass the processor selection information to the system through this means. .

OBJECTS OF THE INVENTION The present invention has been made in view of the above requirements, and its purpose is to eliminate information regarding the execution processor of the procedure after switching from the instruction word group in the procedure immediately before the procedure is switched; Another object of the present invention is to provide a procedure switching control system that allows the assignment of procedure processors to be changed without modifying user programs or system programs.

Structure of the Invention The procedure switching control system according to the present invention includes a processor specification information storage means for specifying the processor on which a procedure is to be executed in correspondence with each of these procedures, and a processor specification information storage means for specifying the processor on which a procedure is to be executed, based on the processor specification information when a procedure switching request is generated. The present invention is characterized in that a procedure is provided with means for determining a procedure to be executed, and actual control of the procedure is transferred to the determined processor.

With this configuration, a procedure can be assigned to a processor by simply storing the processor designation information in the processor designation information storage means in advance, regardless of the execution of the job process that includes the procedure. This means that no processor specification information is reflected in the instruction word.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In discussing the embodiments, we intend to maximize the effects of the invention by keeping the following two points in mind. Firstly, in order to minimize the effort required to switch the value of the execution processor information storage means of the procedure, it is possible to change the value by specifying the parameter when executing the combined editing program (if no specification is made, the previous value is inherited). What I did. Second, in order to avoid adding any additional effort to reading the values in the storage means, we have used empty space (redundant parts) in the information that has traditionally been read out when switching procedures as the storage location.

Next, high-speed scientific calculation processing, which is an embodiment of the present invention,
A so-called supercomputer will be explained using drawings. An outline of the system configuration is shown in FIG.
The arithmetic processor 204 (hereinafter referred to as "AP") has different architectures and completely different instruction language systems, and the job process is based on each processor's own base software (hereinafter referred to as "OS"). Runs under control. Both processors have many common processing functions, except that during system startup, overall control is provided solely by CP 202. If the function can be executed on AP204, its execution speed is CP2.
It is assumed to be significantly faster than 02.

The inside of the main storage device 201 mainly consists of the CP20
Storage area CM201 for storing after instruction 2
1 and a main memory area GM2012 mainly for storing instruction words of AP204, but due to constraints such as ``long access time'' and ``limited access methods,''
It is also possible to access CM2011 from GM2012 and AP204. In this sense CP and AP
and share main memory and exchange data with each other.

The system control device 203 is an interface device placed between these two processors 202, 204, the main storage device 201, and the input/output processing device 205, and operates passively according to the requests of these devices. Note that 206 indicates an external storage device.

FIG. 2 is an example of a flowchart depicting the content and operation of the present invention for the apparatus of the embodiment shown in FIG. It is assumed that the job process J1 (the minimum unit of execution in the computer system) indicated by the bold line E in the figure has a higher execution priority (on both processors) than all job processes to be compared. In the figure, a frame consisting of a dashed line is used to distinguish between two modes of the processor: user modes U1 to U6 and system modes S1 to S4. The latter indicates a state in which a privileged program of the job management system is being executed.

01 is a table that summarizes information (PD) such as import point addresses of all procedures used in a certain job process, which is widely adopted in normal single processor systems. Each entry in this table is accessed by . Reference numeral 302 denotes an area called a stack frame for saving execution information such as the return address of the previous procedure when importing a procedure, and for storing messages to a called procedure. stacked on top.

The control structure of job process J1 is CP202,
Each AP204 has a “J1 PCB”
It is called "PSB of J1". These hold information indicating the current state of the process, but also include address information of the recently created stack frame, and when the procedure exits, J1 accesses the stack frame using this address information. Restoring the information of the previous procedure, etc.

In the configuration of the present invention, the lowest 1 bit of each entry in table 301 and the data in stack frame 302 correspond to "processor specification information storage means for specifying the processor on which a procedure is to be executed for each procedure". This is the lowest 1 bit of the return address storage location. The former is referred to when a procedure is entered, and the latter is referred to when a procedure is exited. dotted arrows D1 and D2 indicate the processor that should execute the called procedure. It is transmitted as follows.

The reason why there is no problem in borrowing the least significant bit of the address storage location here is as follows. In most digital computers, the normal unit of information processing (word) is larger than the smallest addressable unit (byte), and the storage area of large units such as procedures is separated by word boundaries, so the starting address The lower several bits of are 0. Therefore, this bit, which is known to always be 0, may be used as a means for storing other information, and when used for the original address, it may be reset to 0 and transferred. In this embodiment, 1 byte = 8 bits and 1 word = 4 bytes, and the lowest 1 bit of the 2 available lower bits is used as the storage means.

In addition, the broken lines C1 to C4 in the figure indicate inter-processor communication, D1 and D2 indicate movement of execution processor specification information, solid lines B1 to B3 indicate address instructions, and double line A indicates procedure evacuation. Each shows the flow of information.

Next, the operation of this embodiment will be explained in chronological order with reference to FIG. The outline of the processing flow is as follows.
Job process J1 running on CP is now AP
After importing it into the above procedure and executing it on the AP, it returns to the original procedure on the CP and executes it on the CP.'' The reason why the job process J1 is executed immediately after the procedure is switched is because this process J1 has the highest priority among the user job processes.

First, a ``stack creation'' command is executed while a certain procedure J1 on the CP is being executed to create a stack frame for this procedure. At this time, along with saving the contents of the register, the return address (the address of the instruction following the next instruction "ENTER", and this address must be placed on a word boundary) is stored, but the lowest bit of this address is stores “0” as the CP name. If the AP name is set to "1" and this address cannot be placed on a word boundary, the processor name specification bit may be stored somewhere else in the stack frame. It doesn't really matter where it is located.

Next, by executing the "ENTER" instruction, the corresponding entry x' in the address table 301 is retrieved based on the value of the operand The procedure is assumed to be "0"), and the value obtained by resetting the lowest 1 bit of x' is expanded to the start address of the procedure to be called. After the "ENTER" command, the CP enters system mode and first rolls out J1.

Since it is known that the transfer is to another processor (AP), the control structure PCB on the CP of J1
1 to the control structure PSB1 on the AP (current state of J1). After completing preparations for procedure import, the CP sends an "import request" communication to the AP and waits for a reply from the AP. The reply receiver CP is enabled to execute other job processes, and repeats roll-in, execution, roll-out, etc. one after another according to the priority.

If we go back and look at the flow of processing on the AP before the J1 procedure switch, the AP is executing job process J2 in user mode U4.
Procedure import request communication from CP during execution C
After receiving 1, execution of J2 is interrupted and system mode S3 is entered. After sending reply C2, save the register contents etc. to PSB of J2, and
J2 rollout, J1
After successively executing the roll-in, the AP enters user mode U5 and starts executing J1. At this time, the start address expanded from x' in 301 is rolled in. When the procedure exit command "RETURN" is executed, the AP changes to system mode S4, rolls out J1, and stores the processor specification information storage location of the exit destination procedure in the stack frame of J1 (stack frame 30).
Read the processor name "0" (=CP) from the lowest 1 bit of the return address of step 2. Locally used registers are stored in the stack frame 302, and areas commonly used between procedures are stored in PSB1.
The content of PCB1 is transferred from each AP to the CP, and a procedure exit request communication C3 is sent from the AP to the CP. The AP receives a reply C4 from the CP, and unless a job process with a higher priority than J2 is ready to run while J1 is being executed, the AP rolls in J2, enters user mode U6, and resumes executing J2.

On the other hand, on the CP, after receiving the procedure exit request communication C3 while the job process _JN is being executed, the CP interrupts the job _{process JN} and enters the system mode S2. After sending reply C4 to AP, register contents etc. are sent to PCB _N of J _N.
After comparing the priorities of J1 and J _N , rolling out J _N and rolling in J1, the process changes to user mode U3 and restarts the procedure on the CP of J1.

The operation of the present invention has been described above with reference to FIG. 2, but as mentioned above, the present invention is applied slightly differently when entering a procedure and when exiting a procedure (see FIG. 2). This means that two types of embodiments have been shown.

As for the method of storing values in the processor selection information storage means, when exiting a procedure, it depends on the command operation to create a stack frame as described above, but when importing a procedure, the value must be determined in advance at least before executing the ENTER command. There are various methods that can be considered. Although it is possible to dynamically store data during the execution of a job process, this is only when a special function is to be realized. It is assumed that processor selection information is input as a parameter during subsequent combined editing, and is stored in the storage means when the combined editing program generates a procedure import point address.

Note that FIG. 3A shows a conventional method in comparison with FIG. 3B, and is a method of changing the compiler that generates instruction words.

Effects of the Invention As explained above, according to the present invention, when selecting a processor for each procedure in a job process in a multiprocessor system,
By providing a new processor selection information storage means for each procedure and switching control to the executing processor, it is possible to change the allocation of procedure processors without modifying the user program or system program. effective.

[Brief explanation of drawings]

Fig. 1 is a schematic system block diagram of an embodiment of the present invention, Fig. 2 is a flowchart explaining the operation of the blocks in Fig. 1, and Fig. 3 clearly shows the method of the present invention in comparison with the conventional method. This is a diagram. Explanation of symbols of main parts: 201...main storage device, 202...control processor, 203...system control device, 204...arithmetic processor.

Claims (1)

[Claims] 1. A procedure switching control method in an information processing device comprising a plurality of processors that share at least a part of a main storage device, the processor specification information specifying a processor on which a procedure is to be executed in correspondence with each of the procedures. A storing means and a means for determining a processor on which a procedure should be executed based on the processor specification information when a procedure switching request is generated are provided, and execution control of the procedure is transferred to the determined processor. Features a procedural switching control system.