JP3222977B2 - Serial data processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a slave device such as a video signal processing device, for example, and serially transmits serial data sent from a master device to a plurality of synchronization pulses sent separately. It relates to a processing circuit.

[0002]

2. Description of the Related Art As is well known, in a video tape recorder (hereinafter, referred to as VTR), on / off control of a rotating erase head, on / off control of a recording current of a rotating video / HiFi head, switching / switching of a double azimuth head. Embedding (Select the larger of the double azimuth head playback output,
Function to eliminate the noise bar during special playback) control, playback screen switching control, etc.

These controls are performed in synchronization with a video head switching signal (video head switching pulse, hereinafter referred to as V-SWP) or a HiFi head switching signal (HiFi head switching pulse, hereinafter referred to as H-SWP). The better the performance. This synchronization control
The following three methods are common.

(1) A signal requiring synchronization is asynchronously output from a master IC such as a microprocessor and latched by V-SWP or H-SWP using a D-latch flip-flop shown in FIG. This includes the case where the SWP is input to the interrupt terminal and output from the master IC in synchronization with the SWP. In this case, however, the signal output response performance is determined by the processing time.) An example is shown in FIG.

(2) A timing pulse generation circuit (hereinafter referred to as TPG) built in by making a servo circuit a microprocessor.
Signal which needs to be synchronized by V-SWP
Or, synchronize with H-SWP. An example is shown in FIG.

In FIG. 7, a comparator 11 compares a count value of a synchronization pulse obtained by a counter (not shown) with a reference value from a reference value FIFO 21 of a memory circuit 12, and outputs a coincidence timing pulse to the memory circuit 12 and a TPG output buffer. Send to 13.

The TPG output buffer 13 is a memory circuit 12
The TPG data from the TPG data FIFO 22 is fetched and synchronously output. The memory circuit 12 updates the values of the output data of the reference value FIFO 21 and the TPG data FIFO 22 each time the timing pulse is input. As a result, the servo timing is synchronized with the synchronization pulse.

(3) The signal is output from an extension IC such as a serial shift type as shown in FIG. in this case,
When the STROBE (latch) signal is V-SWP or HS
Control to synchronize with WP. An example is shown in FIG.

Recently, as a development of the conventional example (3), as shown in FIG. 10, a master IC 100 using a microprocessor or the like by using a bus (I2C bus).
It is desired to configure a system to control a plurality of slave ICs 201 to 20n such as a video, a HiFi, and a P / R (playback / recording) amplifier.

In this case, it is necessary to serially transmit control data including the address and sub-address of each IC through the serial bus 300. However, since the amount of data on the bus increases, for signals requiring synchronization, V-SWP / H-SWP is controlled by software.
It becomes difficult to synchronize.

There is also a problem that it is generally not possible to simultaneously latch with a plurality of ICs. Even if the slave has a latch function other than the end of reception, it is necessary to send the same serial data to a plurality of ICs within a certain time. Especially I ² When trying to realize using C bus,
According to the standard, data can be sent only within 100 [kbit / sec], which causes a problem in temporal response.

The timing which is most problematic in terms of time is, for example, when six heads are arranged at equal intervals on a rotating cylinder, the shortest section 5.5 [ms] (edge) of both SWP edges. During NTSC signaling VTRs), serial data must be sent to multiple ICs.

Particularly, when this is realized by a microprocessor having a servo function, even if the bus (I ² C bus)
Even if a part of the input / output control is replaced with hardware (for example, the hardware of the serial input / output circuit and the FIFO of the serial input / output buffer), since the servo processing of the microprocessor has too much real-time processing, an interrupt This may not be possible depending on the timing of the factors.

[0014]

As described above, in a conventional serial data processing circuit used in a VTR or the like, when synchronizing serial data transferred from a master device with a plurality of synchronization pulses, a serial bus on a serial bus is used. Due to the increase in data amount, it becomes difficult to synchronize a signal requiring synchronization with each synchronization pulse by software control.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. Even when serial data increases, a signal requiring synchronization can be synchronized with a plurality of synchronization pulses on the slave device side, and the master device can be synchronized. It is an object of the present invention to provide a serial data processing circuit capable of reducing the burden of software control on the side.

[0016]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a master device which has different phases from each other.
With at least first and second sync pulse train is transmitted, it is provided in the slave device serial data is transferred including the first and second data to be synchronized respectively with the first and second synchronization pulse train Serial In the data processing circuit, the first synchronization from the master device
Latch the first and second data by a pulse train
A first latching means, and
By the second synchronizing pulse train, the first latch means
A second latch for latching the latched second data;
And a switch means .

[0017]

In the serial data processing circuit having the above configuration,
Different phases from master device to slave device
Each synchronization with at least the first and second synchronization pulse trains
First and second data to be synchronized with each pulse train
When sending signals including serial
First, the edge of each synchronization pulse is used as the latch timing.
And second latch means, and the first latch means
Latch first and second data by one synchronization pulse train
Then, the second latch means generates the first synchronizing pulse train to
Latching the second data latched by the latch means
Like that. This allows the master device to manage data transfer only with the first synchronization pulse, thereby reducing the responsiveness of software processing time.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS.

FIG. 1 shows an embodiment of a serial data processing circuit according to the present invention, and shows a configuration in which the serial data processing circuit is mounted on a slave IC. This slave IC has I ² The serial data SDA and its synchronization clock SCL are supplied from a master device (not shown) through a two-wire serial data bus such as a C bus (4 is a clock transmission line, 5 is a data transmission line), and other transmissions are performed. A first synchronization pulse P1 and a second synchronization pulse P2 are supplied via lines 10,20. The serial data processing circuit includes a data decode circuit 1, a first latch circuit 2, and a second latch circuit 3.

First, the data decoding circuit 1 receives the serial data SDA from the serial data buses 4 and 5,
After the detection of the end of reception, the received data is decoded into a signal S11 that requires synchronization with the first synchronization pulse P1, a signal S21 that requires synchronization with the second synchronization pulse 20, and a signal S6 that does not require synchronization. I do. Since the decoded signal S6 obtained here is not required for synchronization, it is derived as it is to the subsequent circuit, and both the decoded signals S11 and S21 are sent to the first latch circuit section 2.

The first latch circuit 2 latches the input decode signals S11 and S21 at the timing of the first synchronization pulse P1. These latch signals S13,
S22 is a synchronization signal of the first synchronization pulse P1 that requires synchronization of the first synchronization pulse P1, and a synchronization signal of the first synchronization pulse P1 that requires synchronization of the second synchronization pulse P2. Since the latch signal S13 is already synchronized with the first synchronization pulse, it is derived as it is, and the latch signal S22 is sent to the second latch circuit unit 3.

The second latch circuit 3 latches the latch signal S22 from the first latch circuit 2 at the timing of the second synchronization pulse P2. The signal S2 latched here
Reference numeral 3 denotes a synchronization signal of the second synchronization pulse P2 which requires synchronization of the second synchronization pulse P2. In the above configuration,
The operation will be described with reference to FIGS.

When the clock SCL and the serial data SDA from the master IC are input to the slave IC and received by the data decoding circuit 1, the data decoding circuit 1 converts the received data into the first synchronization pulse 1
A signal S11 requiring synchronization with 0, a signal S21 requiring synchronization with the second synchronization pulse 20, and a signal S6 not requiring synchronization.
Is decoded.

The decode signal S6 is used as it is inside or outside the slave. Decode signals S11, S2
1 is sent to the first latch circuit 2 and is latched at the timing of the synchronization pulse P1. The latch signal S13 of the decode signal S11 is a synchronization signal that requires synchronization of the first synchronization pulse, and is used as it is inside or outside the slave. The latch signal S22 of the decode signal S12 is sent to the second latch circuit 2, and is latched at the timing of the synchronization pulse S20. This latch signal S23 is a synchronization signal that requires synchronization of the second synchronization pulse P2, and is used as is inside or outside the slave.

The configuration of the slave IC is the same as that of video signal processing such as VTR video, HiFi, and reproduction / recording amplifier.
In the case of one of C, the first and second synchronization pulses include V-SWP and H-SWP, and the signals requiring synchronization are the on / off signal of the rotating erase head and the rotating video / H.
Recording current on / off signal for iFi head (hereinafter referred to as video / HiFi recording mute signal), switching signal for double azimuth head / embedding (function to select the larger double azimuth head playback output and eliminate noise bars during special playback) Signal, a playback screen switching signal, and the like. Here, to simplify the explanation, the slave IC is a reproduction / recording amplifier and the serial bus is I ² The case of the C bus will be described.

FIGS. 2 and 3 are timing charts in the case where a video / HiFi recording mute signal of the reproducing / recording amplifier is generated from the serial bus data SDA in the slave IC, respectively, at the start of recording.

In FIGS. 2 and 3, a is video recording mute on / HiFi recording mute on, b is video recording mute on / HiFi recording mute off, c is video recording mute off / HiFi recording mute off, and d is H
iFi recording mute on, e is control data for instructing HiFi recording mute off.

FIG. 2 shows a pattern in which there is a margin in the timing of video recording mute and HiFi recording mute from the phase relationship between H-SWP and V-SWP, and FIG.
A pattern in a case where there is a margin in the timing of video recording mute and HiFi recording mute from the phase relationship between -SWP and V-SWP is shown.

In the initial state, both the video / HiFi recording mute is on, and it is necessary to turn off the HiFi mute and the video recording mute at the start of recording. To realize this timing, the master IC serially transmits the control data a, b, and c to the reproducing / recording amplifier sequentially between both edges of the first synchronization pulse V-SWP.

That is, the master IC is initially connected to the V-SW
The control data a is sent to the reproducing / recording amplifier between both edges of P. The data decoding circuit unit 1 of the reproducing / recording amplifier includes:
After the reception of the control data a, for V (video) synchronization,
Separate for H (HiFi) synchronization. The first latch circuit unit 2 latches both data separated at the edge timing of V-SWP. Furthermore, the second latch circuit unit 3
The control data d for H synchronization latched by the latch circuit unit 2 is latched at the next H-SWP edge timing.
As a result, both the video / HiFi recording mute are turned on.

The master IC sends the control data b to the reproducing / recording amplifier in the next cycle. After the reception of the control data b, the data decode circuit unit 1 of the reproduction / recording amplifier
Separate for synchronization and H synchronization. The first latch circuit unit 2 latches both data separated at the edge timing of V-SWP. Further, the second latch circuit unit 3 latches the control data e for H synchronization latched by the first latch circuit unit 2 at the next H-SWP edge timing. As a result, only the HiFi recording mute is turned on.

The master IC sends control data c to the reproducing / recording amplifier in the next cycle. After the reception of the control data c, the data decoding circuit unit 1 of the reproduction / recording amplifier separates the data for V synchronization and H synchronization. The first latch circuit unit 2 latches both data separated at the next V-SWP edge timing. As a result, the video storage mute is turned on with a delay of HiFi. At this time, the second
Latch circuit 3 latches the control data e for H synchronization latched by the first latch circuit 2 at the next H-SWP edge timing. Thus, the HiFi recording mute is continuously turned on.

In the case of a VTR designed so that six heads are arranged at equal intervals on a rotary cylinder,
It is necessary to send data to a plurality of ICs during the shortest section 5.5 ms (VTR of NTSC signaling) at the edge of P.

On the other hand, I ² C bus is 100kbi in standard
Data can be sent only within t / sec. Therefore, it is necessary to send the address and sub-address data of each slave IC with 10 bits per word. The average data amount at this time is 6 words per IC (about 60b).
it).

For this reason, conventionally, video, HiF
i, the data sent to the three ICs of the reproduction / recording amplifier alone is 1.8 mS at the earliest and 3.6 mS only by halving the clock speed. A servo microprocessor of a VTR system computer that performs other real-time processing simply sends control data to three slave ICs so as to synchronize with each head switching pulse. In this case, it is necessary to send data even if there is another interrupt input during 5.5 mS, but a problem of processing response may occur.

On the other hand, if the serial data processing circuit having the above configuration is mounted on the slave IC, the data is sent between both edges of V-SWP, that is, within 16.6 mS (VTR of the NTSC system). You can take the timing. Therefore, the problem of the processing response does not occur.

Therefore, in the serial data processing circuit having the above configuration, when the master IC is a one-chip microprocessor and sends a large amount of data to a plurality of slave ICs, and the control data input by each slave IC is One sync pulse (eg, video head switching signal)
Alternatively, even when synchronizing with a second synchronization pulse (for example, a HiFi head switching signal), only data is sent from the master IC to the slave IC during the first synchronization pulse.
After the necessary signal is latched on the slave side by the first synchronization pulse, only the signal synchronized with the second synchronization pulse is changed to the second synchronization pulse.
Can be latched by the synchronizing pulse.

As a result, the master IC can manage data transfer only by the first synchronization pulse, and can reduce the responsiveness of software processing time even in a system with many real-time processes.

In the above embodiment, I ² Although described using the C bus, other serial data transfer may be used. Further, when a plurality of latches as in the present invention are required even in a serial circuit in which latch is performed by STROBE, the burden on the master can be reduced by making the circuit configuration of the slave IC the same as that of the present invention.

In the above description, serial data is always sent to a plurality of slave ICs during the first synchronization pulse P1. However, when timing is not required, for example, in the case of refresh, serial data is sent to a plurality of slave ICs. Need not necessarily be sent during the first synchronization pulse P1.

Further, in the description of the above embodiment, for the sake of convenience, the data decoding circuit section 1 separates data for V synchronization and H synchronization after the end of reception of control data, but this is not always necessary. The data for V synchronization among the data latched by the latch circuit unit 2 may be derived as a signal S13, and the data for H synchronization may be latched by the second latch circuit unit 3 and derived as a signal S23.

Further, a plurality of second latch circuits 3 may be arranged in parallel so that the signal S22 is commonly latched at the same timing by the second synchronization pulse. Further, the signal S latched by the second latch circuit unit 3
A latch circuit unit is connected in series, such that a part or all of 22 is latched by a latch circuit unit (not shown) driven by another synchronization pulse (not shown),
It is also possible to adopt a configuration in which data is latched with synchronization pulses having different phases, and data to be synchronized with another synchronization pulse among the latched data is sent to the subsequent stage.

FIG. 4 shows another embodiment according to the present invention. The first and second synchronization pulses V-SWP, H- in FIG.
The structure when multiplexing and sending SWP is shown. 7 is a multiplexed pulse transmission line, and 8 is a synchronous pulse separation circuit. The basic operation is the same as that of FIG. 1, the first and second synchronization pulses P1 and P2 multiplexed and transmitted are separated by the separation circuit unit 8 and input to the corresponding latch circuit units 2 and 3, respectively. It is like that. In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0044]

As described above, according to the present invention, even when serial data increases, a signal requiring synchronization can be synchronized with a plurality of synchronization pulses on the slave device side, and software control on the master device side can be performed. It is possible to provide a serial data processing circuit that can reduce the burden on the serial data processing circuit.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a serial data processing circuit according to the present invention.

FIG. 2 is a timing chart showing a pattern when there is a margin in the timing of video recording mute and HiFi recording mute from the phase relationship between H-SWP and V-SWP in the embodiment.

FIG. 3 is a timing chart showing a pattern when there is a margin in the timing of video recording mute and HiFi recording mute from the phase relationship between H-SWP and V-SWP in the embodiment.

FIG. 4 is a block circuit diagram showing another embodiment according to the present invention.

FIG. 5 is a block circuit diagram showing a configuration when a D-latch flip-flop is used for various synchronization controls in a conventional VTR.

FIG. 6 is a timing chart showing an example of the synchronization control timing of FIG. 5;

FIG. 7 is a block circuit diagram showing a configuration in a case where a timing pulse generation circuit built in a microprocessor of a servo circuit is used for various synchronization controls in a conventional VTR.

FIG. 8 is a block circuit diagram showing a configuration in a case where an extension IC such as a serial shift type is used for various synchronization controls in a conventional VTR.

FIG. 9 is a timing chart showing an example of the synchronization control timing of FIG. 5;

FIG. 10 is a block circuit diagram showing a configuration of a serial bus control system that has recently been desired.

[Explanation of symbols]

11 Comparator 12 Memory circuit 21 Reference value FIFO 22 TPG data FIFO 13 TPG
Output buffer, 100: Master IC, 201 to 20n
... Slave IC, 300 ... Serial bus, 1 ... Data decode circuit section, 2 ... First latch circuit section, 3 ... Second latch circuit section, 4 ... Clock transmission line, 5 ... Data transmission line,
7: multiplexed pulse transmission line, 8: synchronous pulse separation circuit,
SDA: Serial data, SCL: Synchronization clock, P
1: first sync pulse, P2: second sync pulse, V-
SWP: video head switching signal, H-SWP: HiHi
Head switching signal.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 G11B 15/14 H04N 5/782-7/783

Claims (7)

(57) [Claims] 1. A phase difference from a master device.
At least the first and second synchronization pulse trains are transmitted and synchronized with the first and second synchronization pulse trains, respectively.
In the serial data processing circuit provided in the slave device to which the serial data including the first and second data to be transferred is transferred, the serial data processing circuit receives the first synchronization pulse train from the master device.
A first latch for latching the first and second data.
And the second synchronization pulse train from the master device.
The second data latched by the first latch means.
Serial data processing circuit for a second latch means for latching over data, characterized by comprising a. 2. The video signal processing device according to claim 1, wherein the slave device is a video signal processing device, and the synchronization pulse train is a video signal processed by the video signal processing device.
2. The serial data processing circuit according to claim 1, wherein the serial data processing circuit has a predetermined phase relationship with the vertical synchronizing signal of the signal e . 3. The slave device is a video signal processing device used in a magnetic recording / reproducing device using a rotary head equipped with a pair of video heads and a pair of audio heads, wherein the first and second synchronization pulse trains are 2. A serial data processing circuit according to claim 1, wherein the signal is a video head switching signal and an audio head switching signal. 4. The slave device inputs the serial data and a clock synchronized with the data through a bus in which data and a clock synchronized with the data are transmitted through different lines, and based on the clock, the first and the second data are inputted.
2. The serial data processing circuit according to claim 1, wherein each serial data is input to said second latch means. Wherein said first and second sync pulse train is intended to be multiplex transmission, the slave device has been multiplexed
2. The serial data processing circuit according to claim 1, further comprising a synchronization pulse separation unit for separating a synchronization pulse train . 6. The slave device according to claim 1, further comprising an asynchronous data separating means for separating, from the input serial data, data that does not need to be synchronized with the first and second synchronization pulse trains , in the serial data input stage. 2. The serial data processing circuit according to claim 1, wherein 7. The method according to claim 6, wherein the serial data includes at least the first and second pulses between both edges of the first synchronization pulse train .
2. The serial data processing circuit according to claim 1, wherein the serial data processing circuit is configured to transmit the second data .