JP3227786B2 - Element isolation region forming method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming an element isolation region, a method for manufacturing a semiconductor device, and a semiconductor device.

[0002]

2. Description of the Related Art In recent years, as the capacity of semiconductor devices has increased, the area of semiconductor elements has been reduced. Along with this, multilayering of wiring layers and the like has progressed, and as a result, undulations (irregularities) of the semiconductor element have been increased. For this reason, it is necessary to flatten the base on which the wiring layer is to be formed in order to prevent disconnection of the wiring layer due to the step of the base. Conventionally, the LOCOS method has been used to form an element isolation region. However, since the element isolation region formed of an oxide film is raised from the surface of the semiconductor substrate, the surface of the semiconductor substrate cannot be flattened by the LOCOS method. .

[0003] In recent years, attention has been paid to the trench isolation method (for example, in the literature, “Submicron Mech”).
anically Planarized Shallow Trench Isolation With
Field Shiels '', WS Lindenberger, et al., 1991 Sy
mposium of VLSI TechnologyDigest of Technical Pape
rs, pp89-90). The trench isolation method is a technique for forming an element isolation region by embedding an insulating material in a trench (trench) formed in a semiconductor substrate. In this trench isolation method, after the trench is filled with an insulating material, it is necessary to remove the insulating material deposited outside the trench and to planarize the trench. The outline of the conventional trench isolation method will be described below with reference to FIG.

[Step-10] Thin S on a semiconductor substrate 50
After forming the iO ₂ film 52 and the SiN film 54, patterning is performed by a photolithography method, and a groove (trench) 56 is formed by etching (see FIG. 8A).

[Step-20] Next, an oxide film is formed in the groove 56 by thermal oxidation. After that, the CV is
An insulating film 58 made of SiO ₂ is deposited by D or the like. At this time, the insulating film 58 is also formed in a portion other than the groove 56 (see FIG. 8B).

[Step-30] Next, the insulating film 58 made of SiO ₂ formed in a portion other than the groove portion 56 is removed by a polishing method to flatten the semiconductor substrate (FIG. 8C).
reference).

In such a conventional trench isolation method, when an insulating film made of SiO _{2 is} used as a filling material, a semiconductor substrate is formed by using SiN having a lower polishing rate than SiO ₂ as a stopper layer in the polishing method. Can be flattened. This technique is
In addition to the trench isolation method, it is applied to, for example, a planarization process of an interlayer insulating layer.

[0008]

When this trench isolation method is used in various semiconductor device manufacturing processes, the insulating film made of SiO ₂ to be removed by the polishing method is
Harder than a semiconductor substrate, so hard to cut. Therefore, an SiN film 54 is formed on the semiconductor substrate as a stopper layer. After the role of the stopper layer is over,
It is necessary to remove the N film 54. SiN is about 150 °
It can be removed by dipping in hot phosphoric acid heated to C. However, in this way, SiN having a thickness of 10
When etched by hot phosphoric acid to about 0 nm, SiO ₂
The insulating film 58 of about 20 nm is also etched, and as a result, there is a problem that the insulating film 58 becomes thin (see FIG. 9).

Also, since SiN has a stress of about 10 ⁹ Pa, the SiN formed on the semiconductor substrate 50
There is also a problem that crystal defects 60 are generated on the semiconductor substrate 50 due to the influence of the stress from the N film 54 (see FIG. 10A). For example, when a MOS transistor is formed on a semiconductor substrate having such crystal defects 60,
There is a problem that the junction leakage and the like increase and the characteristics of the semiconductor element deteriorate (see FIG. 10B).

In various semiconductor devices, for example, memory devices, when the area of a stopper layer included in a peripheral circuit other than the memory portion is smaller than the area of the entire memory element, the stopper layer included in the peripheral circuit is The polishing pressure at the time of polishing is concentrated. Therefore, the polishing rate is increased, and the stopper layer included in the peripheral circuit alone does not sufficiently function as a stopper at the time of polishing, and the insulating film 58A in the groove portion in the isolated circuit pattern portion is scraped off, and is used as the original stopper layer. There is also a problem that the role of (1) is not sufficiently exhibited (see FIG. 11). Therefore, even in a circuit pattern in which the area ratio of the stopper layer must be reduced with respect to the entire area, a flattening technique by a good polishing method is desired.

Accordingly, an object of the present invention is to solve the problems described in the conventional trench isolation method, and it is possible to further smooth the surface of the semiconductor substrate after forming the trench (trench). A method for forming an element isolation region in a semiconductor substrate, a method for manufacturing a semiconductor device, and a method for forming a semiconductor device without causing defects in the semiconductor substrate and having little dependence on a circuit pattern formed on the semiconductor substrate. It is an object of the present invention to provide an improved semiconductor device.

[0012]

An object of the present invention is to provide an element isolation region forming method for forming an element isolation region by forming an insulating film in a groove formed in a semiconductor substrate, and has the following features. This can be achieved by the method of the present invention. That is, (a) a step of forming a metal film harder than the insulating film on the semiconductor substrate and then patterning the metal film. (B) Etching the semiconductor substrate using the patterned metal film as a mask, and forming a groove in the semiconductor substrate. Forming step (c) forming an insulating film in the trench and on the metal film (d) removing the insulating film formed on the metal film by a rotary polishing method using the metal film as a stopper layer

The metal film can be made of Mo, W, TiN, WC, or various metal silicides such as ZrSi ₂ , WSi ₂ , TaSi ₂ and NiSi ₂ . When the value of the micro Vickers hardness (mHv) of the metal film is larger than the value of the micro Vickers hardness (mHv) of the insulating film, the metal film is said to be harder than the insulating film. FIG. 7 shows the values of the micro Vickers hardness of these various materials.
The value of the micro-Vickers hardness in FIG.
ress, Inc., SP Muraka, "Silicide for VLSI Applic
ation ", pp. 67. Vickers hardness is measured by pressing a diamond indenter with a square pyramid (136 ° facing angle) into the sample.
When I, a hardness which is defined from the ratio of the surface area of the indentation and the load.

The patterning of the metal film can be performed by a usual photolithography method and etching method. The insulating film is made of, for example, SiO ₂ .

Further, the object of the present invention is to form an element isolation region by forming an insulating film in a trench formed in a semiconductor substrate, and then form at least a gate electrode region and a source / drain region, A method for manufacturing a semiconductor device, comprising forming a metal layer on an electrode region and forming an interlayer insulating layer in a region other than the gate electrode region, which can be achieved by the method of the present invention having the following characteristics. . That is, (a) a step of forming a metal film harder than the insulating film on the semiconductor substrate and then patterning the metal film. (B) Etching the semiconductor substrate using the patterned metal film as a mask, and forming a groove in the semiconductor substrate. Step of forming (c) Step of forming an insulating film in the groove and on the metal film (d) Using the metal film as a stopper layer, the insulating film formed on the metal film is removed by a rotary polishing method. Step of forming an isolation region (E) Step of forming a gate electrode region and a source / drain region, and then forming a metal layer at least on the gate electrode region and then forming an interlayer insulating layer on the entire surface (F) Metal Using the layer as a stopper layer, removing the interlayer insulating layer formed on the metal layer by a rotary polishing method, and flattening the interlayer insulating layer

The metal layer is made of TiC, TiN, TiO _x
N, Mo, W, WC, or ZrSi ₂ , WSi ₂ ,
It can be made of various metal silicides such as TaSi ₂ and NiSi. Interlayer insulating layer may be formed of SiO _2.

A semiconductor device according to the present invention is manufactured by the above-described method for manufacturing a semiconductor device, and uses a metal layer for a contact portion of a wiring or an electrode.

According to a preferred embodiment of the semiconductor device of the present invention, a metal layer is used for the self-aligned contact portion.

[0019]

In the method for forming an element isolation region according to the present invention,
As the stopper layer in the rotary polishing method, a metal film harder than the insulating film formed in the groove is used. Therefore, even when the area of the stopper layer is smaller than the area to be polished, a good flat shape can be formed. Further, since the metal film is used as the stopper layer, the metal film serving as the stopper layer can be removed without affecting the insulating film after the rotation polishing.

In the method of manufacturing a semiconductor device according to the present invention, the element isolation region can be formed in the same manner as the method for forming the element isolation region. Moreover, the metal layer formed on the gate electrode region is used as a stopper layer, and the interlayer insulating layer formed on the metal layer is removed by a rotary polishing method to planarize the interlayer insulating layer. Planarization can be controlled accurately.

Further, in the semiconductor device of the present invention, since such a metal layer is used for a wiring or a contact portion of an electrode, the manufacturing process of the semiconductor device can be simplified.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. (Embodiment 1) Embodiment 1 relating to a method for forming an element isolation region of the present invention will be described with reference to FIG. 1 which is a schematic partial sectional view of a semiconductor element. In Example 1, TiN was used as the metal film, and SiO ₂ was used as the insulating film. [Step-100] First, a semiconductor substrate 1 made of silicon
0, a metal film 12 of TiN having a thickness of 30 nm
Deposit. The deposition conditions can be set as follows: gas TiCl ₄ / NH ₃ = 9/900 sccm temperature 600 ° C. pressure 0.3 Pa. The stress of the metal film 12 thus deposited is about 10 ⁸ Pa. [Step-110] Next, after forming a P-type or N-type region on the semiconductor substrate 10, resist patterning is performed, and then dry etching of the metal film 12 made of TiN is performed. Dry etching conditions can be set as follows: gas SiCl ₄ / N ₂ = 10/10 sccm pressure 2 Pa microwave power 850 W (2 MHz) RF power 200 W In this way, a semiconductor element structure whose schematic partial cross-sectional view is shown in FIG. [Step-120] Subsequently, dry etching of the semiconductor substrate 10 is performed under the same dry etching conditions to form a trench (trench) 14 shown in FIG. [Step-130] Next, an insulating film 16 made of SiO ₂ is deposited on the metal film 12 and in the groove 14 (see FIG. 1C). The conditions for depositing SiO ₂ can be as follows. TEOS / O ₃ = 1000/2000 sccm Temperature 390 ° C. Pressure 1.2 × 10 ⁴ Pa Film thickness 400 nm

[Step-140] Next, the insulating film 16 is polished by a rotary polishing method, the insulating film 16 on the metal film 12 is removed, and the insulating film 16 is left only in the groove 14. Thereby, the surface of the semiconductor substrate 10 is planarized (see FIG. 1D).

FIG. 5 shows an outline of a polishing apparatus 100 used for the rotary polishing method. The polishing apparatus 100 includes a polishing plate 102, a substrate support 110, and a slurry supply system 116. The polishing plate 102 is supported on a rotating polishing plate rotation shaft 106, and the polishing pad 10
4 are provided. The substrate support 110 is disposed above the polishing plate 102 and is supported by a substrate support rotation shaft 112. The substrate 108 to be polished is the substrate support 1
10. The substrate support rotating shaft 112 is a polishing pressure adjusting mechanism 114 for pushing the substrate support in the direction of the polishing pad.
Attached to. Slurry 120 containing abrasive
Is supplied from the slurry supply system 116 to the polishing pad 104 through the slurry supply port 118.

The rotary polishing method uses such a polishing apparatus 100. Then, the polishing plate 102 is rotated while the slurry 120 containing the abrasive is supplied to the polishing pad 104. The substrate 1 placed on the substrate support 110 at the same time
While rotating 08, the polishing pressure of the substrate 108 against the polishing pad 104 is adjusted by the polishing pressure adjusting mechanism 114. Thus, the surface of the substrate 108 can be polished.

Alternatively, as described in Japanese Utility Model Application Laid-Open No. 63-754, slurry is applied to a polishing plate rotating shaft 1.
06 and the inside of the polishing plate 102, and can be supplied from a slurry supply port 118 provided in the polishing pad 104 (see FIG. 6).

The conditions in the rotary polishing method were, for example, as follows. Polishing plate rotation speed 37 rpm Substrate support base rotation speed 17 rpm Polishing pressure 5.5 × 10 ³ Pa Slurry flow rate 225 ml / min Polishing pad temperature 40 ° C. Slurry composition Silica (0.025 μm) + K
OH + H ₂ O

[Step-150] Next, the metal film 12 made of TiN is removed. That is, a mixed aqueous solution of aqueous ammonia and aqueous hydrogen peroxide (aqueous ammonia: NH ₄ OH: H ₂₎
By immersion in O ₂ : H ₂ O = 1: 2: 2) for 10 minutes, only the metal film 12 made of TiN is selectively etched. Through the above steps, the semiconductor substrate 10
An element isolation region composed of the trench 14 in which the insulating film 16 is embedded is formed (see FIG. 1E).

(Embodiment 2) Embodiment 2 is an example in which the method shown in Embodiment 1 is improved so as to prevent polishing of an isolated circuit pattern portion. Example 2 will be described with reference to FIG. 2 which is a schematic partial cross-sectional view of a semiconductor device.

[Step-200] First, a metal film 12 made of TiN is deposited on the entire surface of the semiconductor substrate 10. Next, after forming a P-type or N-type region on the semiconductor substrate 10, resist patterning is performed, and then, dry etching of the metal film 12 made of TiN is performed.
Dry etching of the semiconductor substrate 10 is performed under the same dry etching conditions. Next, the insulating film 1 made of SiO ₂
6 is deposited on the metal film 12 and in the groove 14. The above steps are performed from [Step-100] to [Step-13] in Example 1.
0], and a detailed description thereof will be omitted. In this way, a semiconductor element structure whose schematic partial cross-sectional view is shown in FIG.

[Step-210] Next, a second metal film 20 made of TiN is deposited on the entire surface of the insulating film 16.
The deposition conditions can be the same as the conditions described in [Step-100] of the first embodiment. Next, resist patterning is performed on the second metal film 20, and after patterning the second metal film 20 by dry etching, the resist is removed. The dry etching conditions can be, for example, SiCl ₄ / N ₂ = 10/10 sccm, pressure 2 Pa, microwave power 850 W (2 MHz), and RF power 200 W. As a result, the second metal film 20 is formed on the insulating film 16 deposited on the isolated circuit pattern portion 22 (see FIG. 2B).

[Step-220] Then, using the polishing apparatus shown in FIG. 5 or FIG.
The insulating film 16 deposited thereon is removed by a rotary polishing method, and the surface of the semiconductor substrate 10 is planarized (see FIG. 2C).
The conditions for the rotary polishing can be the conditions described in [Step-140] of the first embodiment. In this case, the insulating film 16 in the isolated pattern portion 22 is made of the second
Is covered with the metal film 20, the insulating film 16 in the isolated pattern portion 22 is not scraped, and the flatness of the semiconductor substrate surface can be maintained.

[Step-230] Then, in order to remove the first metal film 12 and the second metal film 20 made of TiN, similarly to [Step-150] of the first embodiment, 10% ammonia water was added. By immersion for minutes, only the metal film 12 and the second metal film 20 are selectively etched. Through the above steps, an element isolation region composed of a trench in which the insulating film 16 is embedded is formed in the semiconductor substrate 10.

(Embodiment 3) Next, Embodiment 3 of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 1 and 3 which are schematic partial sectional views of a semiconductor element. still,
In Example 3, the TiN metal film, a SiO ₂ as the insulating film was used ZrSi ₂ as the metal layer. In the method according to the third embodiment, the salicide structure and the self-aligned contact portion can be formed at once in the semiconductor device.

[Step-300] First, a metal film 12 made of TiN is deposited on the entire surface of the semiconductor substrate 10. Next, after forming a P-type or N-type region on the semiconductor substrate 10, resist patterning is performed, and then, dry etching of the metal film 12 made of TiN is performed.
Dry etching of the semiconductor substrate 10 is performed under the same dry etching conditions. Next, the insulating film 1 made of SiO ₂
6 is deposited on the metal film 12 and in the groove 14. Next, the insulating film 16 is polished by a rotary polishing method, the insulating film 16 on the metal film 12 is removed, and the insulating film 16 is left only in the groove 14. Thereby, the surface of the semiconductor substrate 10 is flattened. Thereafter, in order to remove the metal film 12 made of TiN, only the metal film 12 made of TiN is selectively etched by immersion in an ammonia peroxide solution for 10 minutes. Through the above steps, the semiconductor substrate 10 is provided with the element isolation region 18 formed of the trench in which the insulating film 16 is embedded.
Is formed. These steps are the same as those described in Example 1 [Step-1].
00] to [Step-150], and a detailed description will be omitted. In this way, a semiconductor element structure whose schematic partial cross-sectional view is shown in FIG.

[Step-310] Next, a gate oxide film is formed on the flattened surface of the semiconductor substrate 10, and then polysilicon is deposited thereon, followed by resist patterning and dry etching to form a gate electrode. A region 30 is formed. After that, LDD (Lightly Doped Dr.
ain) In order to form a structure, ion implantation is performed to form a shallow impurity diffusion region 32. The conditions of this ion implantation can be, for example, As 40 Kev 1 × 10 ¹⁴ / cm ² when forming an NMOS, and, for example, BF ₂ 30 KeV 5 × 10 when forming a PMOS. ¹³ / cm ² . Next, an approximately 400 nm thick SiO
_Two layers are formed on the entire surface. The conditions for forming the SiO ₂ layer are as follows, for example, using gas SiH ₄ / O ₂ / N ₂ = 250/250/1.
The temperature can be as low as 00 sccm and 420 ° C. Thereafter, the SiO ₂ layer is etched by anisotropic dry etching to form sidewalls 34 of SiO ₂ on the sidewalls of the gate electrode region 30. The etching conditions for SiO ₂ can be, for example, a gas used, C ₄ F ₈ = 50 sccm, an RF power of 1200 W, and a pressure of 2 Pa. Through the above steps, a semiconductor element having a structure as shown in a schematic partial cross-sectional view in FIG. 3B can be formed.

[Step-320] Next, a Zr layer is deposited to a thickness of 20 nm on the entire surface. The deposition conditions can be, for example, RF bias −50 W DC sputtering power 1 kW Ar flow rate 40 sccm pressure 0.4 Pa temperature 200 ° C. deposition rate 60 nm / min.

[Step-330] Then, RTA (Rapid
Thermal Annealing) in an inert gas at 600 °
C, performing a first round of annealing for 30 sec, silicided metal layer made of Zr, forming a ZrSi _X. Next, the unreacted Zr is selectively etched by immersion in ammonia peroxide for 10 minutes. Next, at 800 ° C. in an inert gas (eg, N ₂ ) atmosphere.
C, a second annealing treatment is performed for 30 seconds, and ZrS
_Let i _{X be} stable ZrSi ₂ with low resistance. As a result, the metal layer 3 made of uniform ZrSi ₂ is formed on the source / drain region formation planned region and the gate electrode region 30.
8 are selectively formed.

[Step-340] Thereafter, ion implantation is performed on the entire surface to form the source / drain regions 40 (see FIG. 3C). The conditions for ion implantation are NMOS
When forming, for example, be a ^{As 50KeV 3 × 10 15 / cm} 2, when forming a PMOS, for example, be a ^{_{BF 2 20KeV 3 × 10 15 /}} cm 2.

[Step-350] Then, the entire surface is made of SiO
CVD interlayer insulating layer 42 having a thickness of about 400nm made of ₂
(See FIG. 4A). The deposition conditions for SiO ₂ can be, for example, a gas flow rate TEOS / O ₃ = 1000/2000 sccm, a temperature of 390 ° C., and a pressure of 1.2 × 10 ⁴ Pa. Next, 1100 ° in N ₂ atmosphere
C, a short annealing process of 10 seconds is performed. This activates Si and ZrSi ₂ and simultaneously diffuses impurities in the source / drain region 40 to form a junction region. As a result, selectively uniform ZrSi ₂ is formed on the source / drain region 40 and the gate electrode region 30.
, And a reduction in sheet resistance (for example, 10 Ω / sq.) Can be realized.

[Step-360] Next, using the polishing apparatus shown in FIG. 5 or FIG. 6, the interlayer insulating layer 42 is flattened by a rotary polishing method. That is, the surface of the interlayer insulating layer 42,
The interlayer insulating layer 42 is polished so that the surface of the metal layer 38 formed on the gate electrode region 30 is substantially flush with the surface (see FIG. 4B). The conditions in the rotary polishing method,
For example, it was as follows. Polishing plate rotation speed 37 rpm Substrate support base rotation speed 17 rpm Polishing pressure 5.5 × 10 ³ Pa Slurry flow rate 225 ml / min Polishing pad temperature 40 ° C. Slurry composition Silica (0.025 μm) + K
OH + H ₂ O

At this time, the metal layer 38 formed on the gate electrode region 30 not only reduces the sheet resistance and the contact resistance of the gate electrode but also functions as a stopper layer at the time of rotary polishing. Further, ZrSi ₂ is exposed on the surface by polishing the surface of the metal layer 38,
This metal layer 38 becomes a contact portion of the gate electrode. Therefore, the self-aligned contact portion can be formed by performing the rotational polishing.

[Step-370] Next, a barrier metal layer 44 for a metal wiring layer is formed. The barrier metal layer 44 has a two-layer structure of, for example, Ti / TiON, and can be sequentially formed by a sputtering method under the following conditions. Ti: Ar flow rate 100 sccm DC sputtering power 4 kW Pressure 0.4 Pa Film thickness 30 nm TiON: Ar / N ₂ -6% O ₂ = 40/70 sccm DC sputtering power 5 kW Pressure 0.4 Pa Film thickness 70 nm

[Step-380] Next, a metal wiring layer 46 made of Al-1% Si is formed (see FIG. 4C). First, Al-1% Si is sputtered, for example, under the following conditions. Ar flow rate 40 sccm Pressure 0.4 Pa DC sputtering power 6 kW Sputtering rate 800 nm / min Thickness 400 nm After that, resist patterning is performed, and then dry etching is performed.
The patterning of the 1-1% Si and the barrier metal layer is performed, and the resist is removed to complete the aluminum-based metal wiring layer 46. Dry etching is, for example, RF
It can be performed under the following conditions using an application type ECR etcher. BCl ₃ / Cl ₂ = 60/90 sccm Microwave power 1000 W DC sputter power 1 kW Ar flow rate 40 sccm RF power 50 W Pressure 13.3 Pa By the above process, Al-1% Si / TiON / T
The contact resistance between the metal wiring layer made of i and the metal layer made of ZrSi ₂ formed on the gate electrode region 30 can be reduced to about 30Ω. Further, since the metal layer made of ZrSi ₂ is also formed on the source / drain region 40, the sheet resistance in the source / drain region can be reduced.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The conditions in each step are merely examples, and can be changed as appropriate depending on the manufacturing conditions and the equipment used. Also, for example, instead of using TiN as the metal film, alumina, diamond, or the like can be used.

[0046]

According to the method of the present invention, since a material which can be selectively etched with respect to the insulating film is used as the stopper layer at the time of rotary polishing, it is possible to prevent the insulating film formed in the groove from being etched. As a result, the surface of the semiconductor substrate can be further flattened. The metal film serving as the stopper layer has low stress and does not cause crystal defects in the semiconductor substrate. Further, even when the area ratio of the stopper layer per unit area is small, the stopper layer functions well and the surface of the semiconductor substrate can be flattened.

In the semiconductor device of the present invention, since a metal layer is used as a stopper layer for flattening the interlayer insulating layer, after the interlayer insulating layer is flattened, the metal layer is selectively formed on the contact portion. And the sheet resistance is reduced. Further, even when a contact is made with the upper wiring layer, a reduction in resistance can be realized. After the planarization of the interlayer insulating layer, the metal layer which is a stopper layer selectively becomes a contact portion,
A process for newly forming a contact hole is not required than the photolithography process and the dry etching process, and a self-aligned contact hole can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of one embodiment of a method for processing a semiconductor substrate of the present invention.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor device for explaining a part of a process of another embodiment of the method for processing a semiconductor substrate of the present invention.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic partial cross-sectional view of the semiconductor element for explaining each step, following FIG. 3;

FIG. 5 is a diagram showing an example of a polishing apparatus suitable for carrying out the method of the present invention.

FIG. 6 is a diagram showing another example of the polishing apparatus.

FIG. 7 is a graph showing values of micro-Vickers hardness of a metal film material suitable for use in the method of the present invention.

FIG. 8 is a diagram showing an outline of a conventional trench isolation method.

FIG. 9 is a diagram showing a problem in the related art.

FIG. 10 is a diagram showing another problem in the related art.

FIG. 11 is a diagram showing still another problem in the related art.

[Explanation of symbols]

Reference Signs List 10 semiconductor substrate 12 metal film 14 groove 16 insulating film 20 second metal film 30 gate electrode region 38 metal layer 40 source / drain region 42 interlayer insulating layer 44 barrier metal layer 46 metal wiring layer 50 semiconductor substrate 52 SiO ₂ film 54 SiN film 56 Groove (trench) 58 Insulating film 100 Polishing device 102 Polishing plate 104 Polishing pad 108 Substrate 110 Substrate support 114 Polishing pressure adjusting mechanism 120 Slurry

Continuation of the front page (56) References JP-A-63-29932 (JP, A) JP-A-61-159737 (JP, A) JP-A-3-148155 (JP, A) JP-A-2-122525 (JP) JP-A-3-205827 (JP, A) JP-A-52-113687 (JP, A) JP-A-50-64767 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 21/76 H01L 21/304 622

Claims (2)

(57) [Claims] 1. A device isolation region forming method for forming an element isolation region by forming an insulating film in the trench formed in the semiconductor substrate, (b) in the semiconductor substrate, metal harder than the insulating film After forming the film, patterning the metal film; (b) etching the semiconductor substrate using the patterned metal film as a mask to form a groove in the semiconductor substrate; And (d) forming a second metal film, which is harder than the insulating film, over the entire surface, and then patterning the second metal film to form an insulating film on the semiconductor substrate.
In the groove, the top surface has substantially the same level as the metal film left in
A step of leaving a second metal film on the formed portion of the insulating film, (e) the metal film and the second metal film as a stopper layer, a rotating polishing an insulating film formed on the metal film A method for forming an element isolation region, the method comprising: 2. After the step (e), a metal film and a second gold
A process for removing a metal film.
The method for forming an element isolation region according to claim 1.