JP3470705B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [0001] 1. Field of the Invention [0002] The present invention relates to a method for forming an element isolation region.
Method and method for manufacturing semiconductor device and semiconductor device
You. [0002] 2. Description of the Related Art In recent years, as the capacity of semiconductor devices has increased,
As a result, the area of the semiconductor element is being reduced. Accompanying it
As the number of wiring layers and other layers increases, as a result,
Undulation (irregularity) is large. For this reason,
Wiring layers to prevent disconnection of wiring layers due to differences
It is necessary to planarize the underlayer on which is to be formed. Conventionally,
LOCOS method is used to form the child isolation region
However, the element isolation region consisting of an oxide film is
The LOCOS method uses
The surface of the body substrate cannot be flattened. In recent years, trench isolation has been developed.
Law is attracting attention (for example, in the literature, “Submicron Mech
anically Planarized Shallow Trench Isolation With
Field Shiels '', W.S.Lindenberger, et al., 1991 Sy
mposium of VLSI TechnologyDigest of Technical Pape
rs, pp89-90). Trench isolation and
Is an insulating material in the trench (trench) formed in the semiconductor substrate.
To form an element isolation region. this
In the trench isolation method, the trench
After embedding the part, remove the insulating material deposited on the part other than the groove part
Need to be planarized. Conventional trench isolation
The outline of the session method will be described below with reference to FIG. [Step-10] Thin S on a semiconductor substrate 50
iO_TwoAfter forming the film 52 and the SiN film 54, the photoresist
Patterning by lithography and etching
To form a trench 56 (see FIG. 8A).
See). [Step-20] Next, the groove is formed by thermal oxidation.
An oxide film is formed in 56. After that, the CV is
SiO by D etc._TwoAn insulating film 58 made of
You. At this time, the insulating film 58 is also formed in portions other than the groove portions 56.
(See FIG. 8B). [Step-30] Next, portions other than the groove portion 56
SiO formed in minutes_TwoOf insulating film 58 made of
And the semiconductor substrate is planarized (FIG. 8C).
reference). [0007] Such a conventional trench isolation
In the deposition method, SiO_TwoAbsence consisting of
When an edge film is used, it is used as a stopper layer in the polishing method.
And SiO_TwoUsing SiN with a slower polishing rate
Thus, the semiconductor substrate can be flattened. This technique is
In addition to the trench isolation method, for example,
It is applied to the edge layer planarization process. [0008] SUMMARY OF THE INVENTION
Method is used in the manufacturing process of various semiconductor devices.
In the case, SiO to be removed by the polishing method_TwoThe insulating film consisting of
Harder than a semiconductor substrate, so hard to cut. So, the stopper
A SiN film 54 is formed on the semiconductor substrate as a layer. So
Then, after the role as the stopper layer is over,
It is necessary to remove the N film 54. SiN is about 150 °
It can be removed by immersion in hot phosphoric acid heated to C.
You. However, in this way, a SiN having a thickness of 10
When etched by hot phosphoric acid to about 0 nm, SiO_Two
The insulating film 58 is also etched by about 20 nm.
That is, as a result, there is a problem that the insulating film 58 becomes thin.
(See FIG. 9). Further, SiN is 10⁹Stress of about Pa
, The Si formed on the semiconductor substrate 50
Due to the influence of the stress from the N film 54, on the semiconductor substrate 50
There is also a problem of generating crystal defects 60 (see FIG. 10).
(A)). Semiconductor having such crystal defects 60
For example, when a MOS transistor is formed on a substrate,
Junction leakage etc. increase, deteriorating the characteristics of semiconductor elements
There is a problem (see FIG. 10B). Further, various semiconductor devices such as a memory device
In the peripheral circuits other than the memory
The area of the topper layer is
Smaller, the stopper layer included in the peripheral circuit
Polishing pressure during polishing is concentrated. Therefore, the polishing speed is high.
And polishing only with the stopper layer included in the peripheral circuit
Stop functioning as a time stopper
The insulating film 58A in the groove in the standing circuit pattern portion is cut.
Removed to fully fulfill the role of the original stopper layer
There is also the problem of not doing so (see FIG. 11). Therefore, the whole
The area ratio of the stopper layer to the area of
Even with circuit patterns that cannot be obtained,
There is a need for a tanning technique. Accordingly, an object of the present invention is to provide a conventional trench.
Solving the problems described in the isolation method
The surface of the semiconductor substrate after forming the trench (trench)
Can be further smoothed and the semiconductor substrate has defects.
Circuit formed on a semiconductor substrate without causing
Devices on semiconductor substrates with little dependence on patterns
Method of forming isolation region, method of manufacturing semiconductor device, and
To provide a semiconductor device formed by such a method.
And there. [0012] SUMMARY OF THE INVENTION The above object is achieved by a semiconductor substrate.
By forming an insulating film in the groove formed in the board
An element isolation region forming method for forming an element isolation region.
Achieved by the method of the present invention having the following features
be able to. That is, (A) A metal film that is harder than an insulating film is formed on a semiconductor substrate.
After the step of patterning the metal film (B) Semiconductor using patterned metal film as a mask
Process to form a groove in a semiconductor substrate by etching the body substrate
About (C) forming an insulating film in the groove and on the metal film; (D) Formed on a metal film using the metal film as a stopper layer
Of removing the removed insulating film by rotary polishing The metal film includes Mo, W, TiN, and WC.
Well, ZrSi_Two, WSi_Two, TaSi_Two, NiSi_TwoEtc.
It can be composed of various metal silicides. Metal film
Of the micro Vickers hardness (mHv) of the insulating film
If it is larger than the value of micro Vickers hardness (mHv)
The metal film is said to be harder than the insulating film. These various materials
The value of the micro Vickers hardness of the material is illustrated in FIG.
The value of the micro-Vickers hardness in FIG.
ress, Inc., S.P.Muraka, "Silicide for VLSI Applic
ation ", pp 67. Vickers hardness is square
A cone (a diamond indenter with a facing angle of 136 ° is pressed into the sample
The hard surface defined by the ratio of the load to the surface area of the cavity.
That's it. [0014] Patterning of the metal film is performed by a usual photolithography.
Can be formed by lithography and etching
You. The insulating film is made of, for example, SiO_TwoConsists of Further, the above object is achieved by forming a semiconductor substrate.
Device isolation area by forming an insulating film in the groove.
Region, and then the gate electrode region and the source / drain
After forming the gate region, at least above the gate electrode region
A metal layer is formed on the region other than the gate electrode region.
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating layer.
Achieved by the method of the present invention having the following features
be able to. That is, (A) A metal film that is harder than an insulating film is formed on a semiconductor substrate.
After the step of patterning the metal film (B) Semiconductor using patterned metal film as a mask
Process to form a groove in a semiconductor substrate by etching the body substrate
About (C) forming an insulating film in the groove and on the metal film; (D) Formed on a metal film using the metal film as a stopper layer
The removed insulating film is removed by a rotary polishing method.
Step of forming isolation region (E) Form gate electrode region and source / drain region
And then apply a metal layer at least over the gate electrode area.
After forming, a step of forming an interlayer insulating layer on the entire surface (F) The metal layer is formed on the metal layer as a stopper layer.
The removed interlayer insulating layer is removed by a rotary polishing method, and the interlayer insulating layer is removed.
Flattening process The metal layer is made of TiC, TiN, TiO._X
N, Mo, W, WC or ZrSi_Two, WSi_Two,
TaSi_TwoComposed of various metal silicides such as NiSi and NiSi
can do. The interlayer insulating layer is made of SiO_TwoForm from
Can be The semiconductor device according to the present invention is the semiconductor device described above.
And the metal layer is formed by wiring or
It is characterized in that it is used for a contact portion of an electrode. According to a preferred embodiment of the semiconductor device of the present invention,
According to this, a metal layer is used for the self-aligned contact portion. [0019] In the method for forming an element isolation region according to the present invention,
Formed in the groove as a stopper layer in the rotary polishing method
Use a metal film that is harder than the insulating film. Therefore, polishing
When the area of the stopper layer is smaller than the area to be
However, a good flat shape can be formed. In addition, metal film
Since it is used as a topper layer, it can be
Removal of metal film as stopper layer without affecting
can do. In the method of manufacturing a semiconductor device according to the present invention,
In the same way, the element isolation region
Can be achieved. Moreover, the gold formed on the gate electrode region
Using the metal layer as a stopper layer, the interlayer formed on the metal layer
The insulating layer is removed by a rotary polishing method, and the interlayer insulating layer is planarized.
Therefore, it is possible to accurately control the planarization of the interlayer insulating layer.
Wear. Further, in the semiconductor device of the present invention,
Use of such metal layer for wiring or contact part of electrode
As a result, the manufacturing process of the semiconductor device can be simplified.
You. [0022] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
I will explain. (Example 1) Formation of an element isolation region of the present invention
Example 1 relating to the method is described in the form of a schematic partial section of a semiconductor device.
This will be described with reference to FIG. In Example 1,
In other words, TiN is used as a metal film and S
iO_TwoIt was used. [Step-100] First, silicon is used
A metal film 12 made of TiN is formed on the entire surface of the semiconductor
Deposit 30 nm. Deposition conditions Gas TiCl_Four/ NH_Three= 9 / 900sccm Temperature 600 ° C Pressure 0.3Pa It can be. The metal film 12 thus deposited
Stress is 10⁸It is about Pa. [Step-110] Next, on the semiconductor substrate 10
After forming a P-type or N-type region in the resist pattern
And then doping of the metal film 12 made of TiN.
Light etching is performed. Dry etching conditions Gas SiCl_Four/ N_Two= 10/10 sccm Pressure 2Pa Microwave power 850W (2MHz) RF power 200W It can be. Thus, FIG.
A semiconductor element structure showing a partial cross-sectional view is formed. [Step-120] Subsequently, the semiconductor substrate 10
Dry etching under the same dry etching conditions
To form a groove (trench) 14 shown in FIG.
I do. [Step-130] Next, SiO_TwoConsisting of
An insulating film 16 is deposited on the metal film 12 and in the groove 14.
(See FIG. 1C). SiO_TwoThe deposition conditions for
Can be TEOS / O_Three = 1000 / 2000sccm Temperature 390 ° C Pressure 1.2 × 10^Four  Pa 400nm thickness [Step-140] Then, by a rotary polishing method
Polishing the insulating film 16 and removing the insulating film 16 on the metal film 12
Then, the insulating film 16 is left only in the groove 14. By this
As a result, the surface of the semiconductor substrate 10 is planarized (see FIG. 1).
(D)). The polishing apparatus 100 used in the rotary polishing method
An outline is shown in FIG. The polishing apparatus 100 is a polishing play machine.
102, the substrate support 110, and the slurry supply system 116
Consisting of The polishing plate 102 is a rotating polishing plate.
The polishing pad 10 is supported on a rotating shaft 106 and has a polishing pad 10 on its surface.
4 are provided. The substrate support 110 is a polishing play
Is mounted above the substrate 102 and is
It is supported. The substrate 108 to be polished is the substrate support 1
10. The substrate support rotating shaft 112 is connected to the substrate support.
Polishing pressure adjusting mechanism 114 for pushing the support in the direction of the polishing pad
Attached to. Slurry 120 containing abrasive
Connects the slurry supply port 118 from the slurry supply system 116.
And supplied to the polishing pad 104. The rotary polishing method uses such a polishing apparatus 100.
Used. Then, the slurry 120 containing the abrasive is polished.
While supplying to the pad 104, the polishing plate 102 is rotated
Invert. The substrate 1 placed on the substrate support 110 at the same time
08 by rotating the polishing pressure adjusting mechanism 114.
The polishing pressure of the substrate 108 against the polishing pad 104
adjust. Thus, polishing the surface of the substrate 108
Can be. Alternatively, see Japanese Utility Model Laid-Open No. 63-754.
As described, the slurry was applied to the polishing plate
06 and the inside of the polishing plate 102,
Supplied from a slurry supply port 118 provided in the pad 104
(See FIG. 6). The conditions in the rotary polishing method are as follows, for example.
It was as follows.         Polishing plate rotation speed 37rpm         Substrate support table rotation speed 17 rpm         Polishing pressure 5.5 × 10^ThreePa         Slurry flow rate 225ml / min         Polishing pad temperature 40 ° C         Slurry composition Silica (0.025 μm) + KOH + H_TwoO [Step-150] Next, TiN
The metal film 12 is removed. That is, ammonia water and peroxidation
Mixed aqueous solution of hydrogen water (ammonia peroxide: NH_FourOH: H_Two
O_Two: H_TwoO = 1: 2: 2) for 10 minutes
Therefore, only the metal film 12 made of TiN is selectively etched.
To run. Through the above steps, the semiconductor substrate 10
An element isolation region including a trench 14 in which an insulating film 16 is embedded.
An area is formed (see FIG. 1E). (Embodiment 2) Embodiment 2 is similar to Embodiment 1.
Method to prevent the polishing of isolated circuit patterns
This is an improved example. Example 2 is a schematic diagram of a semiconductor device.
This will be described with reference to FIG. 2 which is a partial sectional view. [Step-200] First, on the semiconductor substrate 10
A metal film 12 made of TiN is deposited on the entire surface. Next
Then, a P-type or N-type region is formed on the semiconductor substrate 10.
After that, resist patterning is performed, and then TiN
Dry etching of the metal film 12 made of
Dry etching of the semiconductor substrate 10 is performed by the same dry etching.
Perform under the ching condition. Next, the SiO_TwoInsulating film 1 made of
6 is deposited on the metal film 12 and in the groove 14. More than
The steps are performed from [Step-100] to [Step-13] in Example 1.
0], and a detailed description thereof will be omitted. Like this
FIG. 2A is a schematic diagram showing a semiconductor device having a partial cross-sectional view.
A child structure is formed. [Step-210] Next, on the insulating film 16
A second metal film 20 made of TiN is deposited on the entire surface.
The deposition conditions were described in [Step-100] in Example 1.
It can be the same as the condition. Then such a second
Perform resist patterning on the metal film 20 and dry
Patterning of the second metal film 20 by etching.
After that, the resist is removed. Dry etching conditions
For example, SiCl_Four/ N_Two  = 10/10 sccm Pressure 2Pa Microwave power 850W (2MHz) RF power 200W It can be. This allows isolated circuit patterns
The second metal is formed on the insulating film 16 deposited on the
The film 20 is formed (see FIG. 2B). [Step-220] Then, FIG. 5 or FIG.
Using the illustrated polishing apparatus, a metal film 12 made of TiN is formed.
The insulating film 16 deposited on the upper surface is removed by a rotary polishing method.
The surface of the body substrate 10 is flattened (see FIG. 2C).
The conditions of the rotary polishing are described in [Step-140] of Example 1.
Conditions can be set. In this case, an isolated pattern
The insulating film 16 in the region 22 is formed of a second
Is isolated by the metal film 20
The insulating film 16 in the portion 22 is not shaved,
The flatness of the body substrate surface can be maintained. [Step-230] Next, TiN
To remove the first metal film 12 and the second metal film 20
In the same manner as in [Step-150] of Example 1, ammonia
The metal film 12 and the metal film 12
Only the second metal film 20 is selectively etched. that's all
The insulating film 16 is embedded in the semiconductor substrate 10 from the step
An element isolation region consisting of the groove is formed. (Embodiment 3) Next, a semiconductor device according to the present invention will be described.
Example 3 relating to the manufacturing method is described in a schematic diagram of a semiconductor device.
A description will be given with reference to FIGS. still,
In the third embodiment, TiN is used as a metal film and an insulating film is used.
And SiO_TwoWith ZrSi as the metal layer_TwoIt was used. Real
In the method of the third embodiment, a salicide structure
In addition, the self-aligned contact portion can be formed at once. [Step-300] First, on the semiconductor substrate 10
A metal film 12 made of TiN is deposited on the entire surface. Next
Then, a P-type or N-type region is formed on the semiconductor substrate 10.
After that, resist patterning is performed, and then TiN
Dry etching of the metal film 12 made of
Dry etching of the semiconductor substrate 10 is performed by the same dry etching.
Perform under the ching condition. Next, the SiO_TwoInsulating film 1 made of
6 is deposited on the metal film 12 and in the groove 14. Next
Then, the insulating film 16 is polished by the rotary polishing method,
Of the insulating film 16 is removed, and the insulating film 16 is
leave. As a result, the surface of the semiconductor substrate 10 is flattened.
It is. After that, the metal film 12 made of TiN was removed.
Immersion in ammonia peroxide for 10 minutes
To selectively etch only the metal film 12 made of TiN.
To Through the above steps, the semiconductor substrate 10 is completely isolated.
An element isolation region 18 composed of a groove portion in which an edge film 16 is embedded.
Is formed. These steps are the same as those described in Example 1 [Step-10].
0] to [Step-150], and the detailed description is omitted.
Abbreviate. Thus, FIG. 3A is a schematic partial cross-sectional view.
Is formed. [Step-310] Next, the planarized semiconductor
A gate oxide film is formed on the surface of the
Deposit polysilicon on top and resist patterning
Gate electrode area by dry etching
An area 30 is formed. After that, LDD (LightlyDoped Dra
in) Perform ion implantation to form a shallow
A pure substance diffusion region 32 is formed. Conditions for this ion implantation
When forming an NMOS, for example, As 40Kev 1 × 10¹⁴/ Cm^Two And when a PMOS is formed,
Is, for example, BF_Two       30 KeV 5 × 10¹³/ Cm^Two It can be. Next, an approximately 400 nm thick SiO
_TwoA layer is formed on the entire surface. SiO_TwoLayer formation conditions
If       Gas used SiH_Four/ O_Two/ N_Two= 250/250 / 100sccm       Temperature 420 ° C It can be. After that, anisotropic dry etching
By SiO_TwoEtch layer and remove SiO_TwoRhino consisting of
A wall 34 is formed on the side wall of the gate electrode region 30.
You. SiO_TwoThe etching conditions of, for example, Gas used C_FourF₈= 50sccm RF power 1200W Pressure 2Pa It can be. By the above steps, FIG.
(B) A semiconductor having a structure as shown in a schematic partial sectional view.
An element can be formed. [Step-320] Next, a Zr layer is formed over the entire surface.
Deposit 20 nm. Deposition conditions are, for example, RF bias -50W DC sputter power 1kW Ar flow rate 40sccm Pressure 0.4Pa Temperature 200 ° C Deposition rate 60 nm / min It can be. [Step-330] Then, RTA (Rapid
Thermal Annealing) in an inert gas at 600 °
C, first annealing for 30 seconds,
Of the metal layer made of ZrSi_XForm
You. Next, by immersing in ammonia peroxide for 10 minutes
Thus, unreacted Zr is selectively etched. Next
And an inert gas (eg, N_Two800) in atmosphere
C, a second annealing treatment is performed for 30 seconds, and ZrS
i_XWith low resistance and stable ZrSi_TwoAnd By this
On the source / drain region formation region and the gate electrode.
On the pole region 30, a uniform ZrSi_TwoMetal layer 3 consisting of
8 are selectively formed. [Step-340] Then, the source / drain
Implantation is performed on the entire surface to form the ion region 40.
(See FIG. 3C). The conditions for ion implantation are NMOS
When forming, for example, As 50 KeV 3 × 10^Fifteen/ Cm^Two When a PMOS is formed, for example, BF_Two       20 KeV 3 × 10^Fifteen/ Cm^Two It can be. [Step-350] Then, the entire surface is made of SiO
_TwoOf an interlayer insulating layer 42 of about 400 nm
(See FIG. 4A). SiO_TwoPile of
Conditions, for example, Gas flow rate TEOS / O_Three= 1000 / 2000sccm Temperature 390 ° C Pressure 1.2 × 10^FourPa It can be. Next, N_Two1100 ° in atmosphere
C, a short annealing process of 10 seconds is performed. By this
And Si, ZrSi_TwoActivate the source at the same time
Diffusion in the drain / drain region 40 to form a junction region
Form an area. As a result, the source / drain regions 40 and
And ZrSi on the gate electrode region 30_Two
Sheet metal can be formed to reduce sheet resistance
(For example, 10 Ω / sq.). [Step-360] Next, as shown in FIG.
Polishing method for the interlayer insulating layer 42 using the polishing apparatus
To flatten. That is, the surface of the interlayer insulating layer 42,
The surface of the metal layer 38 formed on the gate electrode region 30
The interlayer insulating layer 42 is polished so that
(See FIG. 4B). The conditions in the rotary polishing method,
For example, it was as follows.         Polishing plate rotation speed 37rpm         Substrate support table rotation speed 17 rpm         Polishing pressure 5.5 × 10^ThreePa         Slurry flow rate 225ml / min         Polishing pad temperature 40 ° C         Slurry composition Silica (0.025 μm) + KOH + H_TwoO At this time, the region formed on the gate electrode region 30
The metal layer 38 is formed by the sheet resistance and contour of the gate electrode.
Not only reduces the contact resistance, but also
It acts as a par layer. Furthermore, the surface of the metal layer 38
Is polished so that ZrSi_TwoIs exposed on the surface,
This metal layer 38 becomes a contact portion of the gate electrode. Obedience
The self-aligned contact part is
Can be formed. [Step-370] Next, for the metal wiring layer
Is formed. This barrier metal layer
44 has a two-layer structure of, for example, Ti / TiON,
It can be formed sequentially by the putter method under the following conditions. Ti: Ar flow rate 100sccm DC sputter power 4kW Pressure 0.4Pa Thickness 30nm TiON: Ar / N_Two-6% O_Two  = 40 / 70sccm DC sputtering power 5kW Pressure 0.4Pa Thickness 70nm [Step-380] Next, whether Al-1% Si
A metal wiring layer 46 is formed (see FIG. 4C).
See). First, Al-1% Si is doped under the following conditions, for example.
To putter. Ar flow rate 40sccm Pressure 0.4Pa DC sputter power 6kW Sputter rate 800nm / min Thickness 400nm After that, resist patterning is performed, and then dry etching is performed.
By performing the etching, the sputtered A
Patterning of 1-1% Si and barrier metal layer
Remove the resist and remove the aluminum-based metal wiring layer
46 is completed. Dry etching is, for example, RF
Using an application type ECR etcher under the following conditions
be able to. BCl_Three/ Cl_Two      = 60 / 90sccm Microwave power 1000W DC sputter power 1kW Ar flow rate 40sccm RF power 50W Pressure 13.3Pa By the above process, Al-1% Si / TiON / T
formed on the metal wiring layer made of i and the gate electrode region 30
ZrSi_TwoContact with a metal layer 38 of
The resistance value can be reduced to about 30Ω. Also source / dray
ZrSi also on the_TwoForming a metal layer consisting of
The sheet resistance in the source / drain regions
Can be reduced. The present invention has been described based on the preferred embodiments.
As described, the present invention is limited to these examples.
There is no. Conditions in each step are examples, and manufacturing conditions and
It can be changed as appropriate depending on the device used. Ma
For example, instead of using TiN as a metal film,
Lumina, diamond, and the like can be used. [0052] According to the method of the present invention, a method for rotating and polishing
Selective etching for insulating film as stopper layer
Since a material that can be used is used, the insulating film formed in the groove
Etching can be prevented and the surface of the semiconductor substrate
The layer can be planarized. Also, in the stopper layer
Some metal films have low stress and crystal defects on the semiconductor substrate
Does not occur. Furthermore, stopper layer per unit area
Good stopper layer even when the area ratio of
And the surface of the semiconductor substrate can be flattened. In the semiconductor device of the present invention, interlayer insulation
Use a metal layer as a stopper layer to flatten the layer
After the planarization process of the interlayer insulating layer,
The layer becomes a contact portion, and the sheet resistance is reduced. Change
Low resistance when contacting the upper wiring layer
Can be realized. Also, after the interlayer insulating layer is flattened,
The metal layer which is the stopper layer becomes the contact part,
New from photolithography and dry etch processes
No need for a process to form contact holes
Thus, a self-aligned contact hole can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of an embodiment of a method for processing a semiconductor substrate of the present invention. FIG. 2 is a schematic partial cross-sectional view of a semiconductor device for explaining a part of a process of another embodiment of the method for processing a semiconductor substrate of the present invention. FIG. 3 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of an embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 4 is a schematic partial cross-sectional view of the semiconductor element for explaining each step, following FIG. 3; FIG. 5 is a diagram showing an example of a polishing apparatus suitable for carrying out the method of the present invention. FIG. 6 is a diagram showing another example of the polishing apparatus. FIG. 7 is a graph showing values of micro-Vickers hardness of a metal film material suitable for use in the method of the present invention. FIG. 8 is a diagram showing an outline of a conventional trench isolation method. FIG. 9 is a diagram showing a problem in the related art. FIG. 10 is a diagram showing another problem in the related art. FIG. 11 is a diagram showing still another problem in the related art. [Description of Signs] 10 ... semiconductor substrate, 12 ... metal film, 14 ...
Groove, 16: insulating film, 20: second metal film, 3
0 ... gate electrode area, 38 ... metal layer, 40 ...
.Source / drain region, 42... Interlayer insulating layer, 44
... Barrier metal layer, 46 ... Metal wiring layer, 50
... semiconductor substrate, 52 ··· SiO ₂ film, 54 ··· S
iN film, 56 groove (trench), 58 insulating film, 100 polishing machine, 102 polishing plate, 104 polishing pad, 108 substrate, 11
0 ... substrate support, 114 ... polishing pressure adjustment mechanism,
120 ・ ・ ・ Slurry

Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/8234 H01L 29/78 301N 27/088 21/88 K 29/78 27/08 102D (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/304 H01L 21/3205 H01L 21/336 H01L 21/76 H01L 21/8234 H01L 27/088 H01L 29/78

Claims (1)

(57) Claims 1. An element isolation region is formed by forming an insulating film in a trench formed in a silicon semiconductor substrate,
Next, after forming a gate electrode region and a source / drain region , a metal layer is formed on the gate electrode region and the source / drain region , and a region other than the gate electrode region is formed.
A method for manufacturing a semiconductor device, wherein an interlayer insulating layer is formed thereon, comprising: (a) forming a metal film harder than the insulating film on a semiconductor substrate, and then patterning the metal film; Using the patterned metal film as a mask, etching a semiconductor substrate to form a groove in the semiconductor substrate; (c) forming an insulating film in the groove and on the metal film; (E) removing the insulating film formed on the metal film by a rotary polishing method using the film as a stopper layer, thereby forming an element isolation region; (e) removing the metal film; forming a gate electrode area of polysilicon,
Next, a step of forming a metal layer on the entire surface and (g) heat treatment to form a gate electrode region
Composed of polysilicon and metal layer, and silicon semiconductor substrate
The metal layer is reacted with the silicon
After id of, removing the unreacted metal layer, (h) forming source / drain regions, forming an interlayer insulating layer (Li) entirely, (j) a gate electrode region on Formed into silicide
And the metal layer as a stopper layer, a method of manufacturing a semiconductor device characterized by comprising a layer insulating layer is removed on a rotary polishing method, the step of planarizing the interlayer insulating layer from.