JP3227980B2 - Polycrystalline silicon thin film forming method and MOS transistor channel forming method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a polycrystalline silicon thin film and a method for forming a channel of a MOS transistor using the method.

[0002]

2. Description of the Related Art A transistor for driving a pixel of a liquid crystal display device, a transistor of a peripheral element thereof, a static RAM of a load element type (hereinafter referred to as an SRAM), etc. have an amorphous structure.
Thin film transistors using a thin film of (amorphous) silicon or polycrystalline silicon (polysilicon) [T
FT (Thin Film Transistor)] is used.

However, in polycrystalline silicon, dangling bonds of silicon atoms are present at a higher density than in single crystal silicon, and these dangling bonds cause leakage current when switching off. As a result, the operation speed at the time of switch-on is reduced. Therefore, in order to improve the characteristics of the TFT, it is required to form a polycrystalline silicon thin film having few crystal defects and excellent uniformity. As a method for forming such a polycrystalline silicon thin film, a chemical vapor deposition method, a solid phase growth method, and the like have been proposed. As a means for reducing dangling bonds causing a leak current or the like, a hydrogenation technique of doping hydrogen into a dangling bond by doping hydrogen into a polycrystalline silicon thin film has been used.

[0004] However, when a polycrystalline silicon thin film is formed by growing a crystal having a large grain size by a chemical vapor deposition method, the film thickness becomes non-uniform. Further, it is difficult to obtain a polycrystalline silicon thin film having a uniform film thickness by the chemical vapor deposition method. For this reason, it is difficult to form a transistor having uniform element characteristics using a polycrystalline silicon thin film.

[0005] In the solid phase growth method, crystals grow in a dendritic manner, and the crystal grain size can be formed to a size of 1 μm or more. In the dendritic crystal grains, dislocations, twins and the like are formed. Includes minute defects, which act as traps, hindering and improving characteristics.

[0006]

In order to reduce the density of grain boundary traps due to dangling bonds, a method of performing an annealing process using excimer laser light has been proposed. Excimer laser light has an advantage that it has a large absorption coefficient of silicon due to UV light and can heat only near the silicon surface. Therefore, the base (glass substrate, lower LSI
It does not affect the joints. Excimer laser annealing is performed by first annealing the amorphous silicon film directly, and annealing the polycrystalline silicon film after solid-phase growth with excimer laser light at an energy density that does not melt the entire film. There is.

The former method of directly annealing amorphous silicon has a simpler process than the latter method, and is advantageous for mass production of LSIs in the future. Further, if the large area can be annealed by one excimer laser irradiation, it is more advantageous for mass production. However, when a conventional excimer layer device is used for direct annealing to an amorphous silicon film, a single shot has a large area and surface area sufficient to obtain a polycrystalline silicon thin film having a low grain boundary trap density and good crystallinity. It was difficult to obtain a uniform excimer laser beam. In order to compensate for this, in recent years, excimer lasers having a large output energy capable of annealing a large area with a single shot have been developed. In addition, in order to enhance the effect of excimer laser annealing, a method of heating the substrate to several hundred degrees and performing direct annealing on amorphous silicon has been devised, but a polycrystalline silicon thin film with low grain boundary trap density and good crystallinity has been devised. The process conditions for obtaining are not specified.

In addition, in the conventional method of directly annealing amorphous silicon, the crystal grain size of polycrystalline silicon was 50 nm or less on average. An object of the present invention is to provide a method for forming a polycrystalline silicon thin film having improved crystallinity more than before, and a method for forming a channel of a transistor having excellent electrical characteristics by using the polycrystalline silicon thin film. I do.

[0009]

SUMMARY OF THE INVENTION The present invention provides a method of forming a polycrystalline silicon thin film and a method of forming a channel of a transistor using the method of forming a polycrystalline silicon thin film.

That is, in the method for forming a polycrystalline silicon thin film according to the present invention, in the first step, preferably 3
An amorphous silicon layer having a thickness of 0 nm to 50 nm is formed. Next, in the second step, preferably 350 to 500
℃, more preferably 350 to 450 ℃ substrate heating
Then, the amorphous silicon layer is heated.

Then, in a third step, at least an excimer laser energy density of 100 is applied to the amorphous silicon layer.
^{mJ / cm 2 ~500mJ / cm 2} , preferably 280
^{mJ / cm 2 ~330mJ / cm 2} , pulse width 80ns
The amorphous silicon layer is irradiated with excimer laser light of 200 to 200 ns, preferably 140 ns to 200 ns, and is directly annealed to form a polycrystalline silicon thin film. The total energy of the laser irradiation device used for excimer laser light irradiation is 5 J or more, preferably 10 J or more. At this time, an area of at least 10 cm ² or more is irradiated at a time in one shot.

Further, after the first step and the third step.
Before the step, it is preferable to form an antireflection film on the amorphous silicon layer. By forming the anti-reflection film, the absorption efficiency of laser light to the amorphous silicon layer is improved,
Excimer laser energy density, for example, 180 m
It can be reduced to about J / cm ^{2 to} 230 mJ / cm ² .

According to a method of forming a channel of a MOS transistor according to the present invention, a channel region of a MOS transistor is formed in a polycrystalline silicon thin film formed by using the above method of forming a polycrystalline silicon thin film.

[0014]

In order to obtain a transistor having excellent electric characteristics and uniform element characteristics, the crystal grain size of the polycrystalline silicon thin film is large enough not to exceed the channel dimension of the transistor. The condition is that there are no crystal defects in the grains.

In order to obtain a polycrystalline silicon thin film which satisfies such requirements, the energy of the excimer laser is efficiently transmitted to the amorphous silicon thin film, and the amorphous does not cause defects in the crystal grains. It is necessary to obtain an energy profile with time as a parameter for crystallization. Parameters for this include an excimer laser pulse width, an excimer laser energy density, an amorphous silicon film thickness, and a substrate heating temperature. When trying to obtain a polycrystalline silicon thin film having ideal crystallinity, the influence of these parameters on crystallinity is correlated with each other. For example, if the substrate is heated, the required excimer laser energy density will be low, but if the film thickness is large, the required excimer laser energy density will be high due to the difference in thermal diffusion state. Therefore, in order to obtain a polycrystalline silicon thin film having desired crystallinity, it is necessary to narrow down the conditions of these parameters.

The features of the present invention are as follows. The amorphous silicon is directly annealed by using an excimer laser, and has a single shot, a large area, in-plane uniformity, and is most suitable for forming a transistor. The above parameters have been determined in order to obtain an ideal polycrystalline silicon thin film having low grain boundary trap density and good crystallinity.

According to the present invention, the average crystal grain size is 150 nm (with a variation of about ± 100 cm) over a wide area of at least 10 cm ² or more, preferably 6 cm × 6 cm or more.
nm), it becomes possible to form a polycrystalline silicon thin film having a low electron trap density in the crystal grain boundaries and in the crystal grains.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the present invention will be described based on specific embodiments. First Embodiment A first embodiment of the polycrystalline silicon thin film forming method of the present invention will be described with reference to a polycrystalline silicon thin film forming process shown in FIG.

As shown in FIG. 1A, an insulating layer 12 is formed on a substrate 11. The substrate 11 is not particularly limited. For example, a semiconductor substrate such as a silicon substrate or a glass substrate can be used. The insulating layer 12 is not particularly limited, but for example, silicon oxide can be used. Next, as a first step, an amorphous silicon layer 13 is deposited on the insulating layer 12 by, for example, a chemical vapor deposition method. This amorphous silicon layer 13 is deposited to a thickness of, for example, 40 nm.

The amorphous silicon layer 13 is formed by a low pressure (LP) CVD method using, for example, monosilane (SiH ₄ ).
It is desirable to set the temperature to 00 ° C. or lower. By setting the deposition temperature to 500 ° C. or less, a polycrystalline silicon thin film with few crystal defects in crystal grains can be formed in the next step when excimer laser annealing of the amorphous silicon layer 13 is performed. Can be. When the deposition temperature is set to a temperature exceeding 550 ° C., the crystal grows partially and a polycrystalline silicon thin film having a high defect density is formed.

Next, at least the amorphous silicon layer 13 is heated together with the substrate (substrate heating). The substrate is heated using, for example, a resistance wire, and the substrate heating temperature is set to, for example, 400 ° C. Next, as shown in FIG. 1B, the amorphous silicon layer 13 is irradiated with excimer laser light 15 to directly anneal the amorphous silicon layer 13 to recrystallize the melted region. A polycrystalline silicon thin film 13a is formed.

As the excimer laser beam 15, for example, a xenon chloride (XeCl) excimer laser beam having a wavelength of 308 nm is used. In that case, the excimer laser light 1
An excimer laser energy density is set to, for example, 300 mJ / cm ² , and a pulse width is set to, for example, 150 ns, using a device having a total energy of 5 or more, for example, 10 J or more.

The excimer laser beam may be any laser beam having a wavelength easily absorbed by the amorphous silicon layer 13, for example, a laser beam having a wavelength of 24.
9 nm krypton fluoride (KrF) excimer laser light or 193 nm wavelength argon fluoride (Ar
F) Excimer laser light or the like may be used. In that case, the value of the irradiation energy density is appropriately selected.

In the method for forming a polycrystalline silicon thin film according to the present embodiment, the thickness of the amorphous silicon layer, the substrate heating temperature, the pulse width of the excimer laser light, By setting the energy density of the excimer laser light to a specific value, at least over a wide area of 6 cm × 6 cm
The polycrystalline silicon thin film 13a having an average particle diameter of 150 nm and having a low electron trap density in the crystal grain boundaries and in the crystal grains can be formed. Therefore, if the obtained polycrystalline silicon thin film is used for a medium- and small-sized direct-view type liquid crystal display device or the like, mass production of a high-performance liquid crystal display device or the like can be performed.

Second Embodiment Next, as a second embodiment of the method of forming a polycrystalline silicon thin film, a method of depositing an antireflection film 14 on an amorphous silicon layer 13 and irradiating an excimer laser beam 15 is used. Figure 2
The process will be described with reference to FIGS.

In the step shown in FIG. 2, the surface of the substrate 11 is
After the amorphous silicon layer 13 is formed in the same manner as in the first embodiment, an antireflection film 14 is deposited on the amorphous silicon layer 13 by, for example, 50 nm. The conditions for forming the amorphous silicon layer 13 are the same as those in the first embodiment.

[0027] As the anti-reflection film 14, for example, silicon oxide _{(Si x O y), Si} x N y, Si x O y N
_z can be used. The thickness of the antireflection film is determined so that the antireflection effect is maximized. In the case of this embodiment, the excimer laser beam 15 is irradiated with an energy density of, for example, 200 mJ / cm ² and a pulse width of, for example, 150 ns, using a device having a total energy of, for example, 10 J or more. After that, the antireflection film 14 is removed by using an etching technique. In the method for forming a polycrystalline silicon thin film according to the second embodiment,
By using the antireflection film 14, a polycrystalline silicon thin film 13b equivalent to the polycrystalline silicon thin film 13a obtained in the first embodiment can be obtained with a lower excimer laser energy density than that in the first embodiment. it can.

According to the method of forming a polycrystalline silicon thin film according to this embodiment, at least 6 c
The average grain size is 15 over a large area of mx 6 cm.
At 0 nm, a polycrystalline silicon thin film 13b having a low electron trap density in the crystal grain boundaries and in the crystal grains is obtained. Therefore, if the obtained polycrystalline silicon thin film is used for a medium- and small-sized direct-view type liquid crystal display device or the like, mass production of a high-performance liquid crystal display device or the like can be performed.

Third Embodiment Next, a bottom gate type MOS in which a channel region is formed in a polycrystalline silicon thin film formed by using the polycrystalline silicon thin film forming method according to the first and second embodiments. A method for manufacturing a transistor (TFT: thin film transistor) will be described with reference to a manufacturing process diagram in FIG. The same components as those described in the first embodiment and the second embodiment are denoted by the same reference numerals, and the description thereof will be partially omitted.

First, as shown in FIG. 3A, an insulating layer 12 is formed on a substrate 11 by, for example, a chemical vapor deposition method. Next, a gate electrode formation film 20 is deposited on the insulating layer 12. The gate electrode formation film 20 is formed by, for example, a CVD method, is made of polycrystalline or amorphous silicon doped with phosphorus, and has a thickness of, for example, 100 nm.
Having a film thickness of

Subsequently, the portion of the gate electrode forming film 20 indicated by the two-dot chain line is removed by photolithography and etching, and the gate electrode 21 is formed with the remaining gate electrode forming film 20. Next, the gate insulating film 22 is formed by, for example, a chemical vapor deposition method (or a thermal oxidation method) so as to cover at least the surface of the gate electrode 21. Gate insulating film 22 is made of, for example, silicon oxide, and has a thickness of, for example, 30 nm.

Next, as shown in FIG.
By the same method as described in the embodiment or the second embodiment, the surface of the gate insulating film 22 is formed on the surface of the gate insulating film 22 by a chemical vapor deposition method capable of forming a film having excellent step coverage.
An amorphous silicon layer 23 is deposited. This amorphous silicon layer 23 is formed to a thickness of, for example, 40 nm.

Next, as shown in FIG. 3C, the amorphous silicon layer 23 is irradiated with excimer laser light 25 under the same conditions as those in the first embodiment or the second embodiment. The silicon layer 23 is directly annealed, and the melted region is recrystallized to form a polycrystalline silicon thin film 23a.

As the excimer laser 25, for example, xenon chloride (XeCl) excimer laser light having a wavelength of 308 nm is used. In that case, the excimer laser light 25
The total energy of the excimer laser energy density is set to, for example, 3 using an apparatus of 10 J or more.
Irradiation is performed by setting the pulse width to 00 mJ / cm ² and the pulse width to 150 ns, for example.

Subsequently, as shown in FIG. 4D, the interlayer portion 26 indicated by a two-dot chain line in the polycrystalline silicon thin film 23a is removed by, for example, lithography and etching, and the gate electrode 21 and both sides thereof are removed. Then, a conductive layer forming region 27 having a predetermined pattern is formed with the polycrystalline silicon thin film 23a.

Next, as shown in FIG. 4E, an ion implantation mask composed of, for example, a resist film in a pattern of the gate electrode 21 is formed on the conductive layer forming region 27 by a coating technique and a lithography technique. 28 are formed. Then, the gate electrode 21 is formed by ion implantation.
An impurity (not shown) is introduced into the conductive layer forming region 27 on both sides of the substrate to form source / drain regions 29 and 30. The conductive layer forming region 27 below the ion implantation mask 31 becomes the channel region 31 of the TFT type MOS transistor.

[0037] As the ion implantation conditions at this time, to set, for example, the implantation energy 10 KeV, a dose of 3 × 10 ¹⁵ cm ^- is set to 2, boron ions (B ⁺⁾
Is introduced. Alternatively, the driving energy is 35 Ke
Set V, and dose of 3 × 10 ¹⁵ cm ^- is set to 2,
Boron difluoride ion (BF ₂ ⁺ ) is introduced.

Thereafter, the ion implantation mask 28 is removed by asher treatment or wet etching. Then, activation annealing is performed on the source / drain regions 29 and 30. As annealing conditions, for example, the annealing temperature is set to 900 ° C., and the annealing time is set to 20 minutes. Thereafter, as shown in FIG. 4F, an interlayer insulating film 32 is formed so as to cover the conductive layer formation region 27. The interlayer insulating film 32 is not particularly limited, but is composed of, for example, a silicon oxide film, a silicon nitride film, a PSG (phosphorus-doped glass) film, and a BPSG (boron and phosphorus-doped glass) film formed by a CVD method.

Next, contact holes 34 and 35 are formed in the interlayer insulating film 32 by ordinary lithography and etching techniques. Contact hole 3
Through electrodes 4 and 35, electrodes 36 and 37 connected to source / drain regions 29 and 30 are formed. Although not shown, an electrode connected to the gate electrode 21 is also formed.
These electrodes are made of polysilicon or a metal such as aluminum. Thereafter, a sintering process of the electrode is performed. The conditions for the sintering process are not particularly limited, but are, for example, 400 ° C. and 1 hour.

As described above, the bottom gate type MOS
A transistor 40 is formed. In the method of manufacturing the bottom gate type MOS transistor 40, the polysilicon thin film 23a is formed in substantially the same manner as the polysilicon thin film forming method described in the first embodiment or the second embodiment.
Is formed, and the polycrystalline silicon thin film 23a is used as a conductive layer forming region 27. Then, by forming the channel region 31 there, it becomes possible to obtain the channel region 49 having a low electron trap density in the crystal grain boundaries and in the crystal grains. As a result, TFT type MO with excellent electrical characteristics
An S transistor is obtained.

The TF having the bottom gate structure according to this embodiment
When the T-type MOS transistor 40 is used, for example, as a load element of an SRAM, the power consumption of the SRAM is reduced. In addition, since the soft error resistance of the SRAM is improved, the reliability can be improved. Further, the TFT-type MOS transistor according to this embodiment can be suitably used as a driving transistor of a liquid crystal display element.

Fourth Embodiment Next, a top gate type MOS in which a channel region is formed in a polycrystalline silicon thin film formed by using the polycrystalline silicon thin film forming method according to the first and second embodiments.
A method of manufacturing a transistor (TFT) will be described with reference to FIGS. The same components as those described in the first embodiment and the second embodiment are denoted by the same reference numerals, and the description thereof will be partially omitted.

First, as shown in FIG. 5A, an insulating layer 12 is formed on a substrate 11 by, for example, a chemical vapor deposition method. Next, an amorphous layer is formed on the insulating layer 12 by a chemical vapor deposition method capable of forming a film having excellent step coverage by the same method as described in the first embodiment or the second embodiment. A quality silicon layer 41 is deposited. This amorphous silicon layer 41 has a thickness of, for example, 40
nm.

Next, the amorphous silicon layer 41 is irradiated with an excimer laser beam under the same conditions as in the first embodiment or the second embodiment, and the amorphous silicon layer is directly annealed to form a molten region. Is recrystallized to form a polycrystalline silicon thin film 41a. As the excimer laser, for example, xenon chloride (XeCl) excimer laser light having a wavelength of 308 nm is used. In that case, the total energy of the excimer laser beam is set to, for example, 10 J or more, and the excimer laser energy density is set to, for example, 300 mJ / cm ² and the pulse width is set to, for example, 150 ns.
And irradiate.

Subsequently, as shown in FIG. 5B, the polycrystalline silicon thin film 41a is etched by, for example, a lithography technique and an etching technique to form a conductive layer forming region 42 having a predetermined pattern. Subsequently, the gate insulating film 4 is formed on the surface of the conductive layer forming region 42 by, for example, a chemical vapor deposition (CVD) method or a thermal oxidation method.
Form 3 This gate insulating film 43 is made of, for example, silicon oxide, and has a thickness of, for example, 30 nm.

Further, as shown in FIG. 5C, the surface of the gate insulating film 43 is
A gate electrode forming film 44 is deposited. The gate electrode forming film 44 is made of, for example, amorphous silicon or polycrystalline silicon doped with phosphorus as an impurity, and has a thickness of, for example, about 100 nm.

Next, the portion of the gate electrode forming film 44 indicated by the two-dot chain line is removed by photolithography and etching using the resist film 45, and the gate electrode forming film located on the conductive layer forming region 42 is removed. At 44, a gate electrode 46 is formed. Subsequently, as shown in FIG. 6D, ion implantation is performed using the resist film 45 used for etching for forming the gate electrode 46 as an ion implantation mask. Note that a mask different from the resist film 45 at the time of etching may be used as the ion implantation mask. By this ion implantation, an impurity (not shown) is introduced into the conductive layer forming region 42 located on both sides of the gate electrode 46, and the source / drain region 4
7, 48 are formed in a self-aligned manner. Therefore, channel region 49 is formed in self-alignment in conductive layer forming region 42 made of polycrystalline silicon.

[0048] As the ion implantation conditions at this time, to set, for example, the implantation energy 10 KeV, a dose of 3 × 10 ¹⁵ cm ^- is set to 2, boron ions (B ⁺⁾
Is introduced. Alternatively, the driving energy is 35 Ke
Set V, and dose of 3 × 10 ¹⁵ cm ^- is set to 2,
Boron difluoride ion (BF ₂ ⁺ ) is introduced.

After that, the resist film 45 is removed by asher treatment or wet etching. Then, activation annealing of the source / drain regions 47 and 48 is performed. As annealing conditions, for example, the annealing temperature is set to 900 ° C., and the annealing time is set to 2 hours.
Set to 0 minutes.

Next, as shown in FIG. 6E, an interlayer insulating film 50 is formed on the gate electrode 46 and the gate insulating film 43 by, for example, 150 nm to 200 nm by CVD.
m. This interlayer insulating film 50 is formed of a silicon oxide based film such as a PSG film or a BPSG film or a silicon nitride film.

Thereafter, the contact holes 51, 52, 52 are formed by ordinary photolithography and etching.
53 is formed. Further, electrodes 55, 54, 56 connected to the gate electrode 46 and the source / drain regions 47, 48 through the contact holes 51, 52, 53 are formed by a normal wiring forming technique. These electrodes are made of polysilicon or a metal such as aluminum.

Thereafter, a sintering process is performed. The conditions for the sintering process are not particularly limited, but are, for example, 400 ° C. and 1 hour. Thus, the top gate type MOS transistor 60 is formed. Top-gate type MOS transistor 6 according to the present embodiment
In the manufacturing method No. 0, the polycrystalline silicon thin film 41a is formed using the polycrystalline silicon thin film forming method according to the first embodiment or the second embodiment, and the polycrystalline silicon thin film 4a is formed.
By forming the channel region 49 in 1a, it is possible to obtain the channel region 49 having a low electron trap density in the crystal grain boundaries and in the crystal grains. As a result, a TFT type MOS transistor having excellent electric characteristics can be obtained.

The TF having the top gate structure according to this embodiment
When the T-type MOS transistor 60 is used, for example, as a load element of an SRAM, the power consumption of the SRAM is reduced. In addition, since the soft error resistance of the SRAM is improved, the reliability can be improved. Further, the TFT-type MOS transistor according to this embodiment can be suitably used as a driving transistor of a liquid crystal display element.

Hereinafter, the present invention will be described based on more specific examples. Note that the present invention is not limited to these examples. Example 1 First, an amorphous silicon film having a thickness of 80 nm was formed on a quartz substrate by a low pressure (LP) CVD method using monosilane (SiH ₄ ). The deposition temperature was 500 ° C. Next, the amorphous silicon film was irradiated with an excimer laser to crystallize the amorphous silicon to obtain a polycrystalline silicon film. At that time, the substrate was heated to 400 ° C. The apparatus used for laser irradiation was VEL manufactured by Sopra with a total energy of 10J.
The energy density of the laser was 280 mJ / cm ² . The number of shots was one shot, and the range was 6 cm × 6 cm.

Next, in order to observe with a transmission electron microscope (TEM), using a mixed solution of HF: H ₂ O = 1: 1,
The quartz substrate (SiO ₂ ) was etched to obtain only a polycrystalline silicon thin film (sample). FIG. 7 shows a TEM observation result (bright field image) of the substantially central portion of the sample. As TEM, JEOL 2000FX with an accelerating voltage of 200 kV
-II was used.

Table 1 shows the results of obtaining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG.

[0057]

[Table 1] Example 2 A sample was prepared in the same manner as in Example 1 except that the laser energy density was changed to 350 mJ / cm ² , and a TEM observation was performed at a substantially central portion of the sample. FIG. 8 shows the result of TEM observation (bright field image).

Table 1 shows the results of obtaining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG. Comparative Example 1 A sample was prepared in the same manner as in Example 1 except that the laser energy density was changed to 220 mJ / cm ² , and a TEM observation was performed at a substantially central portion of the sample. FIG. 9 shows the result of TEM observation (electron diffraction pattern).

The diffraction pattern in the photograph shown in FIG. 9 showed that the sample was still amorphous. Comparing Evaluation Examples 1 and 2 and Comparative Example 1, as shown in Table 1, in order to obtain a polycrystalline silicon thin film having a large crystal grain size at a film thickness of 80 nm, the energy density was 350 mJ / cm ² . Certain Example 2 has been found to be preferred.

Example 3 A sample was prepared in the same manner as in Example 1 except that the thickness of the amorphous silicon film at the time of deposition was 40 nm and the laser energy density was 300 mJ / cm ² . TEM observation was performed at a substantially central portion. FIG. 10 shows the result of TEM observation (bright field image).

Table 2 shows the results of obtaining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG.

[0062]

[Table 2] Example 4 A sample was prepared in the same manner as in Example 1 except that the thickness of the amorphous silicon film at the time of deposition was 40 nm and the laser energy density was 350 mJ / cm ^2. Was observed by TEM. FIG. 11 shows the result of TEM observation (bright field image).

Table 2 shows the results of determining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG. Comparative Example 2 A sample was prepared in the same manner as in Example 1 except that the thickness of the amorphous silicon film during deposition was set to 40 nm and the laser energy density was set to 150 mJ / cm ^2. Was observed by TEM. FIG. 12 shows the result of TEM observation (electron diffraction pattern).

The diffraction pattern in the photograph shown in FIG. 12 showed that the sample was still amorphous. Comparing Evaluation Examples 3 and 4 and Comparative Example 2, as shown in Table 2, in order to obtain a polycrystalline silicon thin film having a large crystal grain size at a film thickness of 40 nm, the energy density was 300 mJ / cm ² . It turned out to be sufficient, and even higher energy densities were not so different.

Example 5 The procedure of Example 5 was repeated except that the thickness of the amorphous silicon film during deposition was 80 nm, the laser energy density was 350 mJ / cm ^2, and laser annealing was performed without heating the substrate (at room temperature). A sample was prepared in the same manner as in Example 1, and a TEM observation was performed at a substantially central portion of the sample. FIG. 13 shows the result of TEM observation (bright field image).

Table 3 shows the results of obtaining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG.

[0067]

[Table 3] Example 6 A sample was prepared in the same manner as in Example 5, except that the number of shots of laser irradiation for the same sample was changed to 10.
TEM observation was performed at the approximate center of this sample. TE
FIG. 14 shows the M observation result (bright field image).

Table 3 shows the results of obtaining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG. Example 7 A sample was prepared in the same manner as in Example 5, except that the number of shots for the same sample was changed to 100, and a TEM observation was performed at a substantially central portion of the sample. FIG. 15 shows the result of TEM observation (bright field image).

Table 3 shows the results of obtaining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG. Comparing Evaluation Examples 5 to 7, it was found that the crystallinity and crystal grain size of the polycrystalline silicon thin film did not depend on the number of shots as shown in FIGS. Therefore, from the viewpoint of shortening the process, one shot is sufficient for the number of laser shots.

Example 8 A sample was prepared in the same manner as in Example 1 except that the thickness of the amorphous silicon film at the time of deposition was 40 nm and the laser energy density was 350 mJ / cm ² . TEM observation was performed at a substantially central portion. FIG. 16 shows the result of TEM observation (bright field image).

Table 4 shows the results of determining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG.

[0072]

[Table 4] Example 9 A sample was prepared in the same manner as in Example 8 except that the film thickness of the amorphous silicon film at the time of deposition was set to 80 nm, and a TEM observation was performed at a substantially central portion of the sample. FIG. 17 shows the result of TEM observation (bright field image).

Table 4 shows the results of determining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG. Comparing Evaluation Examples 8 and 9, as shown in FIGS. 16 and 17 and Table 4, under the same conditions except for the film thickness, in order to obtain a polycrystalline silicon thin film having a large grain size, the film thickness was as thin as 40 nm. Proved to be more advantageous.

Example 10 The procedure of Example 10 was repeated except that the thickness of the amorphous silicon film during deposition was 40 nm, the laser energy density was 300 mJ / cm ² , and the substrate was not heated (room temperature) and laser annealing was performed. A sample was prepared in the same manner as in Example 1, and a TEM observation was performed at a substantially central portion of the sample. FIG. 18 shows the result of TEM observation (bright field image).

Table 5 shows the results of obtaining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG.

[0076]

[Table 5] Example 11 A sample was prepared in the same manner as in Example 10 except that the substrate heating temperature was set to 400 ° C., and TEM observation was performed at a substantially central portion of the sample. FIG. 19 shows the result of TEM observation (bright field image).

Table 5 shows the results of determining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG. Example 12 A sample was prepared in the same manner as in Example 1 except that the laser energy density was set to 350 mJ / cm ² and laser annealing was performed without heating the substrate (at room temperature). Observations were made. FIG. 20 shows the result of TEM observation (bright field image).

Table 6 shows the results of determining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG.

[0079]

[Table 6] Example 13 A sample was prepared in the same manner as in Example 12 except that the substrate heating temperature was set to 400 ° C., and a TEM observation was performed at a substantially central portion of the sample. FIG. 21 shows the result of TEM observation (bright field image).

Table 6 shows the results of obtaining the crystal grain size range and the average crystal grain size in the polycrystalline silicon film (sample) from the photograph shown in FIG. Evaluation As shown in FIGS. 18 to 21 and Tables 5 and 6,
It was found that under the condition that only the substrate heating was performed or not, it was possible to obtain a polysilicon film having a large crystal grain size by performing the substrate heating.

Further, as to the sample of Example 11, as a result of examining the in-plane uniformity of the crystal grain size range and the average crystal grain size, the crystal grain size was large at the center and slightly larger at the periphery than at the center. It was also found that the crystal grain size tended to be small, but it was found that the crystal grain size was within a range in which there was no problem in device fabrication.

[0082]

As described above, according to the polycrystalline silicon thin film forming method of the present invention, a single annealing process
Over a wide area of at least 3 cm × 3 cm, it is possible to obtain a polycrystalline silicon thin film having a considerably large average crystal grain size and having a low electron trap density in crystal grain boundaries and crystal grains. Therefore, the obtained polycrystalline silicon thin film is
If it is used for a medium- and small-sized direct-view type liquid crystal display device, mass production of a high-performance liquid crystal display device or the like can be performed.

Further, according to the transistor channel forming method of the present invention, the transistor channel is formed in the polycrystalline silicon thin film formed by the polycrystalline silicon thin film forming method. The effect is reduced. Therefore, leakage current is reduced, variation in threshold voltage is significantly reduced, and transistor reliability can be significantly improved.

Further, there is an effect that variation in characteristics of each transistor can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are process diagrams of a method for forming a polycrystalline silicon thin film according to an embodiment of the present invention.

FIG. 2 is a process diagram of a polycrystalline silicon thin film forming method according to another embodiment of the present invention.

FIGS. 3A to 3C are process diagrams showing a method for forming a channel of a MOS transistor according to an embodiment of the present invention.

4 (D) to 4 (F) are process diagrams subsequent to FIG. 3;

5 (A) to 5 (C) are process diagrams showing a method for forming a channel of a MOS transistor according to another embodiment of the present invention.

6 (D) and 6 (E) are process diagrams subsequent to FIG. 5;

FIG. 7 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 1 of the present invention.

FIG. 8 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 2 of the present invention.

FIG. 9 is a TEM observation result (electron diffraction pattern) of the sample according to Comparative Example 1 of the present invention, which is an electron micrograph.

FIG. 10 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 3 of the present invention.

FIG. 11 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 4 of the present invention.

FIG. 12 is a diagram showing TE of a sample according to Comparative Example 2 of the present invention.
It is an electron micrograph of the M observation result (electron diffraction pattern).

FIG. 13 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 5 of the present invention.

FIG. 14 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 6 of the present invention.

FIG. 15 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 7 of the present invention.

FIG. 16 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 8 of the present invention.

FIG. 17 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 9 of the present invention.

FIG. 18 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 10 of the present invention.

FIG. 19 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 11 of the present invention.

FIG. 20 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 12 of the present invention.

FIG. 21 is an electron micrograph showing a TEM observation result (bright field image) of the polycrystalline silicon film according to Example 13 of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Substrate 12 ... Insulating layer 13, 23, 41 ... Amorphous silicon layer 13a, 23a, 41a ... Polycrystalline silicon layer 14 ... Antireflection film 21, 46 ... Gate electrode 22, 43 ... Gate insulating film 29, 30, 47, 48 source / drain regions 31, 49 channel regions 40, 60 MOS transistors

Claims (6)

(57) [Claims] In a first step, an amorphous silicon layer having a predetermined thickness is formed on a substrate, and in a second step, the amorphous silicon layer is heated to a predetermined temperature. in the process, the total energy by a laser light generating apparatus having the above 5 J, at least on the amorphous silicon layer, a laser beam having a laser energy density ^{100mJ / cm 2 ~500mJ / cm 2} , in the one-shot 10 cm ² or more A polycrystalline silicon thin film forming method for irradiating an area to form a polycrystalline silicon thin film. 2. The amorphous silicon layer has a thickness of 30 nm.
The method for forming a polycrystalline silicon thin film according to claim 1, wherein the thickness is from 50 to 50 nm. 3. The method according to claim 1, wherein the heating temperature of the substrate in the second step is 350 ° C. to 500 ° C. 4. An anti-reflection film is formed on the surface of the amorphous silicon layer at least before the third step.
The laser energy density in the process is 100 mJ / cm ²
Polycrystalline silicon thin film forming method according to any one of claims 1 to 3, characterized in that to set the ~230mJ / cm ^2. 5. The pulse width of the laser beam irradiation in the third step is 80 ns to 200 ns.
The method for forming a polycrystalline silicon thin film according to any one of the above. 6. The method according to claim 1, wherein a channel region of a MOS transistor is formed in the polycrystalline silicon thin film formed in the third step. A method for forming a channel of the MOS transistor used.