JP3684909B2 - Thin film transistor manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor thin film transistor used in an electronic circuit or the like, a manufacturing method of a thin film transistor having a MOS type structure used as a configuration of a display pixel and a liquid crystal driving circuit of a liquid crystal display device, and a thin film transistor manufactured by the manufacturing method.
[0002]
[Prior art]
Conventionally, a thin film transistor having a MOS type structure is widely used for a pixel electrode of a liquid crystal display device, a liquid crystal driving circuit, and the like. Thin film transistors having the MOS type structure are classified into amorphous thin film transistors and polycrystalline thin film transistors based on the difference in the atomic arrangement structure of the semiconductor active layer. The former uses a so-called amorphous semiconductor, which does not have long-range order of atomic arrangement, as an active layer. In the current market, amorphous semiconductor materials using amorphous Si: H composed of silicon and hydrogen are the mainstream. However, since an amorphous semiconductor is used, the electrical characteristics of the semiconductor active layer, such as mobility, are low, and it is not suitable for applications that require a high switching speed and a relatively large current. It is used for driving. The latter uses a polycrystalline semiconductor film composed of a plurality of crystal regions as a semiconductor active layer. Currently, silicon is the mainstream. Since the crystallinity is high except for the grain boundaries, the electrical characteristics of the semiconductor active layer, such as mobility, are relatively high, and it can be used for high-speed switching and large current applications as well as liquid crystal pixel driving. it can. Those using a polycrystalline semiconductor film are further divided depending on whether a relatively high process temperature or a relatively low process temperature is used in the process of polycrystallization and interface formation. Usually, the former is called a high-temperature process thin film transistor, and the latter is called a low-temperature process thin film transistor. In the high temperature process, solid phase growth of a semiconductor film in a high temperature furnace is used for the polycrystallization process, and in the interface formation process, a thermal oxidation process used in an interface formation process such as LSI is basically used. In the low-temperature process thin film transistor, the polycrystallization process is a melting and solidification process by laser irradiation, and the interface is formed by directly forming a gate insulating film on the crystallized semiconductor film.
[0003]
As shown in FIG. 3, many thin film transistors using amorphous silicon have a structure called a bottom gate method. A structural feature of this method is that a gate electrode for controlling a current flowing between the source and the drain is on the substrate, and there is a gate insulating film and an amorphous semiconductor layer serving as an active layer thereon. On the other hand, the structure of a thin film transistor using polycrystalline silicon is mainly a top gate structure as shown in FIG. The structural feature of this system is that a base layer made of an insulator is formed on a substrate, a semiconductor layer serving as an active layer is formed thereon, and a gate insulating film and a gate are formed in this order.
[0004]
In general, in these thin film transistors having the MOS type structure, the MOS interface is very important, and a clean interface is desired in order to exhibit the performance of the thin film transistor. However, in an amorphous thin film transistor and a low-temperature process thin film transistor, the interface is not always kept clean during the process because the gate insulating film is deposited on the active layer or the active layer is formed on the gate insulating film. . That is, since the device is different in the active layer forming process and the gate insulating film forming process, the cleanliness of the interface is greatly impaired in the transition process. In addition, since a high-temperature process thin film transistor uses a thermal oxidation process used in LSI or the like, a clean interface is formed. However, since a very high temperature (900 ° C. or higher) is used, the substrate material is required to have heat resistance. At present, a quartz glass substrate is widely used, but it is difficult to produce a substrate having a large area compared to glass or the like, and the cost is very high when a large substrate is used. Therefore, amorphous semiconductor thin film transistors and low-temperature process thin film transistors are suitable for forming a large number of thin film transistors in a large area at a low cost, and are widely used, and research and development are also being conducted vigorously.
[0005]
[Problems to be solved by the invention]
However, the amorphous thin film transistor and the low temperature process thin film transistor have a problem in the cleanliness of the interface as described above, and it is difficult to improve the characteristics of the thin film transistor. There have been several attempts. As an attempt, a clean interface is formed by oxidizing the surface of a semiconductor layer serving as an active layer very thinly with oxygen plasma or ozone activated by ECR or RF plasma. In this state, since the thickness of the gate oxide film is still very thin, the gate oxide film is additionally deposited to a desired thickness by another method. As an oxide film deposition method, for example, RF plasma is used in another apparatus by TEOS or the like.
[0006]
By doing so, the interface can be formed not inside the surface of the semiconductor active layer, but inside the semiconductor active layer. Therefore, the process is the same as the interface formation by the thermal oxide film, and a clean interface can be realized. However, the structure of an amorphous thin film transistor is not a conventional bottom gate type but a top gate type structure. Further, another device is used to obtain a desired film thickness even if the surface of the semiconductor layer that becomes the folding active layer as described above is oxidized extremely thinly by oxygen plasma or ozone activated by ECR to form a clean interface. It is necessary to move to. At that time, by touching an atmosphere containing impurities or moisture outside the device, an extremely inconvenient state that affects the device operation is created on the surface of the gate insulating film formed very thin. In addition, if some ions are introduced at this time, the ions become movable ions when the element is operating, thereby destabilizing the element operation.
[0007]
As another problem, the use of a plurality of apparatuses causes problems of apparatus cost, process time, and process complexity.
[0008]
In view of the above-described problems, the present invention performs contamination of the interface between the first-layer gate insulating film and the second-layer gate insulating film by performing the interface forming step and the gate insulating film forming step in one apparatus. An object of the present invention is to provide a thin film transistor having a clean interface and excellent characteristics. Furthermore, the present invention provides a method for manufacturing a thin film transistor having excellent characteristics, which eliminates process time and process complexity.
[0009]
[Means for Solving the Problems]
  In order to solve the above-described problems, the thin film transistor manufacturing method of the present invention is a method for forming a MOS thin film transistor having a MOS type structure by continuously performing a MOS interface forming process and a gate oxide film forming process on the semiconductor thin film in the same apparatus. InIn the MOS interface forming step, an oxidation method using plasma energy is used in an oxygen atmosphere diluted with an inert gas.It is characterized by that. Here, MOS structure means metal-oxide-semiconductor (Metal-Oxide-Semiconductor) is a structure with the structure. The MOS interface forming step is a step of creating a semiconductor-oxide interface of a MOS device. The gate oxide film forming step refers to a step of forming a gate oxide film with a desired thickness on a thin oxide film on the MOS interface formed in the MOS interface forming step. Here, the semiconductor thin film is a film formed of a semiconductor such as Ge or Si. The gate oxide film is a combination of the semiconductor material and other elements, such as silicon dioxide and silicon nitride.
[0010]
  To solve the above problems,the aboveIn the thin film transistor manufacturing method, the MOS interface forming step uses an oxidation method utilizing plasma energy. Here, examples of the oxidation method using plasma energy include an RF plasma CVD apparatus and an ECR plasma CVD apparatus.
[0011]
  To solve the above problems,the aboveIn the thin film transistor manufacturing method, the MOS interface forming step is an RF plasma oxidation method.
[0012]
  To solve the above problems,the aboveIn the thin film transistor manufacturing method, the gate insulating film forming step is an oxide film forming step using plasma energy.
[0013]
  To solve the above problems,the aboveIn the thin film transistor manufacturing method, the gate insulating film forming step is an oxide film forming step by a chemical vapor deposition method using RF plasma..To solve the above problems,the aboveIn the thin film transistor manufacturing method, the MOS interface forming step on the semiconductor is an RF plasma oxidation method, and the gate insulating film forming step is an oxide film forming step using plasma energy.
[0014]
  To solve the above problemsIn the above thin film transistor manufacturing method,The MOS interface formation step on the semiconductor is an oxidation method using plasma energy, and the gate insulating film formation step is an oxide film formation step by a chemical vapor deposition method using RF plasma.
[0015]
Further, in order to solve the above-mentioned problems, claim 8 is characterized in that the preparation method according to claims 1 to 7 is included in a part of the process.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.
[0017]
First, a conventional process will be described with reference to FIG.
[0018]
First, a base protective film and an amorphous semiconductor film are formed on a substrate. As materials for semiconductor films for crystallization, there are materials such as silicon (Si), germanium (Ge), tellurium (Te), selenium (Se). Si, which is being promoted, was used. This series of forming methods will be described.
[0019]
(Underlying protective film layer formation)
In FIG. 5, a silicon oxide film is deposited as a base protective layer 20 on a substrate 30 heated to 400 ° C. by a chemical vapor deposition method (hereinafter referred to as PECVD method) using plasma assist using TEOS as a raw material.
[0020]
(Amorphous semiconductor film formation process)
Subsequently, an amorphous semiconductor film 510 is formed. Disilane (Si) by LPCVD₂H₆) As a source gas.
[0021]
For crystallization, a KrF excimer laser beam (wavelength 248 nm) is used, such as a line beam having a trapezoidal cross section.
[0022]
The crystallization is performed by shifting the trapezoidal beam while shifting the beam so that the irradiation partially overlaps in the direction perpendicular to the longitudinal direction of the beam to crystallize the entire active layer on the substrate. As described above, an active layer is formed (FIG. 5B).
[0023]
Next, the polycrystalline silicon film is patterned using a photolithography technique, and a semiconductor layer to be an active layer of the TFT later is formed in an island shape 511 (FIG. 5C). After this, surface cleaning is performed, but the contamination remains without being sufficiently removed. Subsequent to this, a gate insulating film is formed.
[0024]
Subsequently, a thin film to be the gate electrode 70 is formed by PVD or CVD (FIG. 5D). After patterning the gate electrode, impurity ions are implanted into the polycrystalline semiconductor film 511 to form a source region 511 and a drain region 512. (FIG. 5D).
[0025]
Next, an interlayer insulating film 580 is formed by the CVD method (5 (E)). Finally, a contact hole 61 for wiring is formed on the source / drain, the source / drain is taken out, and the electrode 5 and the wiring are connected by PVD or CVD. The thin film transistors are completed by the same formation (FIG. 5E).
[0026]
(First embodiment)
In this embodiment, a low-temperature polycrystalline silicon thin film transistor will be described as an example. However, the present invention can also be applied to amorphous silicon thin film transistors.
[0027]
The present invention relates to a part of all processes related to the fabrication of a thin film transistor having a MOS type structure, an interface forming process and a gate insulating film forming process. Therefore, the steps before the step of applying the present invention will be described first.
[0028]
(Primary protective film layer formation process)
In FIG. 1, a silicon oxide film is deposited as a base protective layer 20 on a substrate 30 heated to 400 ° C. by a chemical vapor deposition method (hereinafter referred to as a PECVD method) by plasma assist using TEOS as a raw material. Deposition is not particularly problematic in the ECR-CVD method, the atmospheric pressure chemical deposition method (hereinafter referred to as APCVD method) using monosilane (SiH4) and oxygen gas as source gases, or the sputtering method.
[0029]
The underlying protective layer is not limited to a silicon oxide film, and may be silicon nitride or other films. In the present invention, various substrates can be used depending on applications. For example, a liquid crystal display device needs to be able to transmit light in the visible light region, and a transparent substrate is desired. In addition, heat resistance is also required because it is placed at a relatively high temperature of 400 ° C. to 500 ° C. during the process. Examples of such materials include heat-resistant glass such as quartz glass, Corning 7059, and Nippon Electric Glass OA-2. In applications such as electronic circuits, a single crystal Si substrate or the like can be used because it is not necessary to be transparent.
[0030]
(Active layer semiconductor film formation process and patterning process)
Subsequently, an amorphous semiconductor film 10 is formed. This layer is later polycrystallized to become the active layer. In the present embodiment, deposition is performed using disilane (Si 2 H 6) as a source gas by low pressure chemical vapor deposition (hereinafter referred to as LPCVD method). First, the substrate deposited up to the base layer is set in the substrate holder of the deposition furnace, the temperature of the reaction chamber is kept constant at 250 ° C., and it is waited until it reaches an equilibrium state. Thereafter, the inside of the furnace is evacuated by a turbo molecular pump, and then the substrate is slowly heated to a film forming temperature of 425 ° C. uniformly. Nitrogen gas with a purity of 99.9999% is allowed to flow at a flow rate of 300 SCCM 10 minutes after the start of temperature increase. When the substrate reaches the deposition temperature, the introduction of nitrogen gas is stopped, the source gas disilane (Si2H6) 200 SCCM and the dilution helium gas (purity 99.9999 or more) 1000 SCCM are introduced to form the amorphous semiconductor layer. Do it. When the desired film thickness is reached, the film formation is stopped. In this example, the film thickness was 50 nm. Subsequently, nitrogen gas is introduced at 200 SCCM as before, the substrate is cooled to 300 ° C., and the remaining disilane gas is sufficiently replaced. Then, the internal pressure is brought to atmospheric pressure, and then the substrate is taken out. Note that the amorphous semiconductor film may be deposited by APCVD, PECVD, or sputtering. In the PECVD method, deposition can be performed at a substrate temperature of about 100 ° C. to 500 ° C. using monosilane or the like as a raw material. Further, in the sputtering method, deposition can be performed at a substrate temperature of about room temperature to 400 ° C. Further, a film which is not an amorphous semiconductor but is polycrystallized or microcrystallized from the beginning by the above method may be used.
[0031]
Next, crystallization of the amorphous layer will be described. The following steps can be omitted when a polycrystalline film having sufficient characteristics is formed in the previous step.
[0032]
For the crystallization, a KrF excimer laser beam (wavelength: 248 nm) was used as a line beam having a trapezoidal cross section (hereinafter referred to as a trapezoidal beam). The flat part had a width of 300 μm, and the part where the power dropped gently on both sides was 50 μm. The length direction of the line was 40 cm, which is about the width of the substrate. The cross-sectional shape is not limited to a trapezoid, but may be Gaussian or the like, and may be any beam that is convenient for crystallization, such as a rectangular spot-shaped beam instead of a line beam. Regarding the laser, XeCl excimer laser, Nd-YAG laser, Ar laser, Co2 laser, He-Ne laser, GaAs-based or GaN-based semiconductor laser, etc. may be used. Lasers that can generate very short pulse oscillations such as lasers, Nd-YAG lasers, and semiconductor lasers are desirable.
[0033]
Crystallization is performed while shifting the trapezoidal beam so that irradiation partially overlaps in a direction perpendicular to the longitudinal direction of the beam. In the embodiment of the present invention, using the trapezoidal beam, the front surface of the substrate was crystallized by performing pulse oscillation once every moving distance of 15 μm (hereinafter referred to as moving pitch). Regarding the power, in the embodiment of the present invention, what was performed with a power intensity of 400 mJ / cm 2 had the best characteristics. Therefore, an active layer crystallized with this power as the optimum crystallization power was used. The optimum power and moving pitch vary depending on the deposition conditions, but the present invention can be applied to any case. As described above, an active layer is formed (FIG. 1B).
[0034]
Next, the polycrystalline silicon film is patterned by using a photolithography technique, and a semiconductor layer to be an active layer of the TFT later is formed in an island shape 10 (FIG. 1C).
[0035]
(MOS interface formation process)
The MOS interface forming process according to the present invention will be described in detail below.
[0036]
In this embodiment, the interface is formed by direct oxidation of the active layer by RF plasma.
[0037]
First, an RF plasma apparatus will be described with reference to FIG.
[0038]
In the figure, 201 is a chamber of an RF plasma apparatus, and is connected to an exhaust system through an exhaust hole 202. There is a sample stage 203 on the bottom of the chamber for placing a substrate 204 that also serves as an anode. The sample stage has a heating mechanism for heating the substrate. A shower head 205 also serving as a cathode is provided at the upper part of the chamber so as to face the sample stage. The shower head is provided with a plurality of holes 206 so that a gas can be supplied from the gas supply hole 207 from the outside on the opposite side and a source gas can be introduced into the chamber. An RF power source 209 is connected to the introduction tube, so that an RF band electric field can be applied in the chamber.
[0039]
After the pre-process is completed, the substrate is immersed in a solution in which H2SO4 and H2O2 are mixed at a ratio of 10: 1 and heated to 95 ° C. for 15 minutes to perform cleaning. Next, it is immersed in a solution in which HF and H2O are mixed at 1:30 for 30 seconds, and the oxide film on the surface of the active layer is removed. Further, a solution prepared by mixing HCl, H 2 O 2 and H 2 O at 1: 1: 5 is immersed in heated at 75 ° C. for 10 minutes to wash the active layer.
[0040]
The substrate after cleaning is fixed to the sample stage of the RF plasma apparatus. A gas in which oxygen is mixed with an inert gas (hereinafter referred to as diluted oxygen gas) is introduced into the RF plasma apparatus through the gas supply hole 7, and the active layer is oxidized to form a MOS interface. In the embodiment of the present invention, Ar or He is used as the inert gas.
[0041]
First, the substrate is heated to 400 ° C. by the substrate heating mechanism, and diluted oxygen gas is introduced into the chamber at a flow rate of He and oxygen of 5000 SCCM and 100 SSM (oxygen gas introduction amount 2%) from the gas supply hole, and at the exhaust hole side. The exhaust flow rate was adjusted, and the pressure in the chamber was 1 Torr. Therefore, an RF electric field (input power 1 W / cm 2) was applied for 10 minutes to generate radical oxygen, oxidize the surface of the active layer, and form a MOS interface. The flow rate and pressure are the same when Ar is used as the inert gas. As a result, a 61 angstrom silicon oxide film 13 and a MOS interface 12 were formed on the surface of the active layer (FIG. 1D). It should be noted that the present invention has the same effect even in the following ranges as conditions for this step.
[0042]
Dilution gas: He, Ne, Ar, Kr, Xe, N2
Oxygen introduction amount: 1% to 15%
RF power: 0.1 to 1.5W / cm2
Substrate temperature: 20 ° C to 600 ° C
Pressure: 100 to 4000 mTorr
(Gate insulation film formation process)
Next, a gate insulating film is formed (FIG. 1E).
[0043]
After the formation of the MOS interface in the previous step, the introduction of the dilution gas is stopped, the inside of the chamber is evacuated, the pressure is reduced to 0.6 Torr, and the pressure is maintained for about 10 minutes. Meanwhile, the substrate temperature of the sample stage is kept at 400 ° C.
[0044]
Subsequently, the source gas of the silicon oxide film, TEOS (Si- (O-CH₂-CH₃)₄) And oxygen were introduced into the chamber at 4200 SCCM and 140 SSM, respectively, the exhaust flow rate was adjusted on the exhaust hole side, and the pressure in the chamber was 0.6 Torr. In this state, the gate insulating film 14 is completed by depositing the gate oxide film until the total thickness of the gate insulating film becomes 1200 angstroms.
[0045]
(Subsequent processes)
Subsequently, a thin film that becomes the gate electrode 70 is formed by a PVD method or a CVD method. Usually, since the gate electrode and the gate wiring are made of the same material and in the same process, it is necessary to be stable at a temperature of about 350 ° C. In this example, a tantalum thin film having a thickness of 600 nm is formed by sputtering. The substrate temperature when forming the tantalum thin film is 180 ° C., and the sputtering gas is an argon gas containing 6 to 7% nitrogen gas. After the gate electrode patterning, impurity ions are implanted into the active layer semiconductor film to form the source region 15 and the drain region 17. At this time, the gate electrode 70 serves as a mask to form a self-aligned structure. The present invention can also be applied to a so-called Lightly Doped Drain structure in which a region having an ion implantation concentration lower than that of a source region or a drain region is provided between a channel portion and a drain portion. As the ion doping gas, hydrogen-implanted hydrides of implanted impurity elements such as phosphine (PH3) and diborane (B2H6) having a concentration of about 0.1% to 10% are used. In this embodiment, an ion doping apparatus is used, and phosphine (PH3) diluted in hydrogen is implanted at an acceleration voltage of 100 keV. Injection volume is 1 × 10¹⁶cm^-2It is.
[0046]
Next, an interlayer insulating film 18 is formed by CVD or PVD (FIG. 1H). In this example, TEOS (Si- (O-CH₂-CH₃)₄) And oxygen and H₂A film of 500 nm is formed at a substrate temperature of 300 ° C. using O as a source gas and argon as a diluent gas. Thereafter, in order to activate the implanted impurity ions and to densify the interlayer insulating film, the temperature is raised to 300 ° C. or higher, and heat treatment is performed for several tens of minutes to several hours. The purpose of impurity activation is as follows. The implanted impurities cannot generate carriers unless they are replaced with silicon atoms at the lattice positions. Many of the impurities that have just been implanted enter the silicon lattice. Therefore, this process is performed in order to place impurity atoms implanted in the lattice position of silicon properly and to generate conductive carriers effectively. Also, the gate insulating film and the interlayer insulating film usually have different film quality, and the etching rate differs when the so-called contact hole is formed to make electrical connection between the source and drain and the outside. The hole shape becomes a reverse taper shape that is wider toward the bottom, or a flaw is formed, resulting in a defect in which electrical connection is insufficient. In order to prevent this, it is necessary to increase the density of the interlayer insulating film. In this example, heat treatment was performed at 300 ° C. for 1 hour under an atmosphere of oxygen containing 1% steam with a dew point of 80 ° C. The pressure is about 0.5 to 1.5 atmospheres in an oxygen-containing gas (preferably an oxygen concentration of 25 to 100%) containing about 35 to 100 degrees C. of dew point. The temperature is about 100 to 400 degrees C. When the temperature is about 30 minutes to 6 hours, the quality of the gate insulating film and the interlayer insulating film is improved, the etching rate is reduced, and the above problem is eliminated or alleviated.
[0047]
Finally, a contact hole 61 for wiring is opened on the source / drain, the source / drain is taken out, and electrodes and wiring are formed by the PVD method, the CVD method, or the like to complete the TFT.
[0048]
In order to see the basic characteristics and reliability of the fabricated TFT, a BT test was attempted. A change in Ids-Vgs characteristics was measured when a DC of Vds = 5 V and Vgs = 18 V was continuously applied at a temperature of 150 ° C. Measurement time is 60 minutes. FIG. 5 shows a measurement example of the thin film transistor according to the present invention, and FIG. Obviously, there is little deterioration compared with the conventional example. Also, the initial characteristics of the thin film transistor according to the present invention are superior. In order to compare these points, we tried to measure the interface state by the usual CV evaluation method. According to this, in the present invention, 2 × 10¹¹[cm^-2・ EV^-1In the conventional example, 1 × 10^{1 2}[cm^-2・ EV^-1] Clearly shows that the former has lower interface states and better characteristics.
[0049]
As can be seen from these results, according to the present invention, a TFT having excellent initial characteristics and reliability can be obtained.
[0050]
(Embodiment 2)
In this embodiment, a low-temperature polycrystalline silicon thin film transistor will be described as an example. However, the present invention can also be applied to amorphous silicon thin film transistors.
[0051]
The present invention relates to a part of all processes related to the fabrication of a thin film transistor having a MOS type structure, an interface forming process and a gate insulating film forming process. Therefore, the steps before the step of applying the present invention will be described first.
[0052]
(Primary protective film layer formation process)
In FIG. 3, a silicon oxide film is deposited as a base protective layer 320 on a substrate 310 heated to 400.degree. C. by a chemical vapor deposition method (hereinafter referred to as PECVD method) using plasma assist using TEOS as a raw material. Deposition is not particularly problematic in the ECR-CVD method, the atmospheric pressure chemical deposition method (hereinafter referred to as APCVD method) using monosilane (SiH4) and oxygen gas as source gases, or the sputtering method.
[0053]
The underlying protective layer is not limited to a silicon oxide film, and may be silicon nitride or other films. In the present invention, various substrates can be used depending on applications. For example, a liquid crystal display device needs to be able to transmit light in the visible light region, and a transparent substrate is desired. In addition, heat resistance is also required because it is placed at a relatively high temperature of 400 ° C. to 500 ° C. during the process. Examples of such materials include heat-resistant glass such as quartz glass, Corning 7059, and Nippon Electric Glass OA-2. In applications such as electronic circuits, a single crystal Si substrate or the like can be used because it is not necessary to be transparent.
[0054]
(Active layer semiconductor film formation process and patterning process)
Subsequently, an amorphous semiconductor film 330 is formed. This layer is later polycrystallized to become the active layer. In the present embodiment, deposition is performed using disilane (Si 2 H 6) as a source gas by low pressure chemical vapor deposition (hereinafter referred to as LPCVD method). First, the substrate 310 is set on the substrate holder of the deposition furnace, the temperature of the reaction chamber is kept constant at 250 ° C., and the process waits until an equilibrium state is reached. Thereafter, the inside of the furnace is evacuated by a turbo molecular pump, and then the substrate is slowly heated to a film forming temperature of 425 ° C. uniformly. Nitrogen gas with a purity of 99.9999% is allowed to flow at a flow rate of 300 SCCM 10 minutes after the start of temperature increase. When the substrate reaches the film forming temperature, the introduction of nitrogen gas is stopped, and disilane (Si2H6) 200 SCCM as a source gas and helium gas for dilution (purity 99.9999 or more) 1000 SCCM are introduced to form a semiconductor layer. When the desired film thickness is reached, the film formation is stopped. In this example, the film thickness was 50 nm. Subsequently, nitrogen gas is introduced at 200 SCCM as before, the substrate is cooled to 300 ° C., and the remaining disilane gas is sufficiently replaced. Then, the internal pressure is brought to atmospheric pressure, and then the substrate is taken out. Note that the amorphous semiconductor film may be deposited by APCVD, PECVD, or sputtering. In the PECVD method, deposition can be performed at a substrate temperature of about 100 ° C. to 500 ° C. using monosilane or the like as a raw material. Further, in the sputtering method, deposition can be performed at a substrate temperature of about room temperature to 400 ° C. Further, a film which is not an amorphous semiconductor but is polycrystallized or microcrystallized from the beginning by the above method may be used.
[0055]
Next, crystallization of the amorphous layer will be described. The following steps can be omitted when a polycrystalline film having sufficient characteristics is formed in the previous step.
[0056]
For the crystallization, a KrF excimer laser beam (wavelength: 248 nm) was used as a line beam having a trapezoidal cross section (hereinafter referred to as a trapezoidal beam). The flat part had a width of 300 μm, and the part where the power dropped gently on both sides was 50 μm. The length direction of the line was 40 cm, which is about the width of the substrate. The cross-sectional shape is not limited to a trapezoid, but may be Gaussian or the like, and may be any beam that is convenient for crystallization, such as a rectangular spot-shaped beam instead of a line beam. Regarding the laser, XeCl excimer laser, Nd-YAG laser, Ar laser, Co2 laser, He-Ne laser, GaAs-based or GaN-based semiconductor laser, etc. may be used. Lasers that can generate very short pulse oscillations such as lasers, Nd-YAG lasers, and semiconductor lasers are desirable.
[0057]
Crystallization is performed while shifting the trapezoidal beam so that irradiation partially overlaps in a direction perpendicular to the longitudinal direction of the beam. In the embodiment of the present invention, using the trapezoidal beam, the front surface of the substrate was crystallized by performing pulse oscillation once every moving distance of 15 μm (hereinafter referred to as moving pitch). Regarding the power, in the embodiment of the present invention, what was performed with a power intensity of 400 mJ / cm 2 had the best characteristics. Therefore, an active layer crystallized with this power as the optimum crystallization power was used. The optimum power and moving pitch vary depending on the deposition conditions, but the present invention can be applied to any case. The active layer is formed as described above.
[0058]
Next, the polycrystalline silicon film is patterned using a photolithography technique, and a semiconductor layer to be an active layer of the TFT later is formed in an island shape (FIG. 3C).
[0059]
(MOS interface formation process)
The MOS interface forming process according to the present invention will be described in detail below.
[0060]
In this embodiment, the interface is formed by direct oxidation of the active layer by ECR plasma.
[0061]
First, the ECR plasma apparatus will be described. The basic structure and operation will be described with reference to FIG.
[0062]
The ECR plasma apparatus is large and includes a plasma generation chamber 401 and a reaction chamber 402. There is a sample stage 403 in the lower part of the reaction chamber, and a substrate 404 is placed thereon. The sample stage is equipped with a substrate heating mechanism so that the substrate can be heated. A gas introduction hole 405 is provided at the upper part of the peripheral wall of the reaction chamber. The bottom is connected to the exhaust system. Furthermore, the upper part is connected to a plasma generation chamber from which plasma is introduced. The plasma generation chamber is surrounded by a large magnetic field application coil 406, and the upper portion is connected to the waveguide 408, and a microwave for plasma excitation is introduced. Further, a gas introduction hole 407 is also provided.
[0063]
After the pre-process is completed, the substrate is immersed in a solution in which H2SO4 and H2O2 are mixed at a ratio of 10: 1 and heated to 95 ° C. for 15 minutes to perform cleaning. Next, it is immersed in a solution in which HF and H2O are mixed at 1:30 for 30 seconds, and the oxide film on the surface of the active layer is removed. Further, a solution prepared by mixing HCl, H 2 O 2 and H 2 O at 1: 1: 5 is immersed in heated at 75 ° C. for 10 minutes to wash the active layer.
[0064]
The substrate after the cleaning is fixed to the sample stage of the ECR plasma apparatus. A gas in which oxygen is mixed with an inert gas (hereinafter referred to as diluted oxygen gas) is introduced into the ECR plasma apparatus through a gas supply hole 407, and the active layer is oxidized to form a MOS interface. In the embodiment of the present invention, Ar or He is used as the inert gas.
[0065]
First, the substrate is heated to 400 ° C. by the substrate heating mechanism, and diluted oxygen gas is introduced into the chamber through the gas supply holes with the flow rates of He and oxygen being 500 SCCM and 2.5 SSM (oxygen gas introduction amount 2%), respectively, and the exhaust hole side The exhaust flow rate was adjusted with the pressure in the chamber to 1 Torr. Therefore, a microwave was introduced at 100 W to generate radical oxygen, and the surface of the active layer was oxidized to form a MOS interface. The flow rate and pressure are the same when Ar is used as the inert gas. As a result, a silicon oxide film 313 and a MOS interface 312 were formed on the surface of the active layer (FIG. 3D). It should be noted that the present invention is also effective as conditions for this step other than the above conditions.
[0066]
(Gate insulation film formation process)
Next, a gate insulating film is formed.
[0067]
After the formation of the MOS interface is completed in the previous step, the introduction of the dilution gas is stopped, the inside of the chamber is sufficiently evacuated, and then kept for about 10 minutes. Meanwhile, the substrate temperature of the sample stage is kept at 400 ° C.
[0068]
Subsequently, the source gas of the silicon oxide film, SiH4 and oxygen are introduced into the chamber from the gas supply hole 407 while applying a microwave of 500 W, the exhaust flow rate is adjusted on the exhaust hole side, and the pressure in the chamber is set to 1 Torr. . In this state, the gate insulating film is completed by depositing the gate oxide film until the total thickness of the gate insulating film reaches 1200 angstroms.
[0069]
(Subsequent processes)
Subsequently, a thin film that becomes a gate electrode is formed by a PVD method or a CVD method. Usually, since the gate electrode and the gate wiring are made of the same material and in the same process, it is necessary to be stable at a temperature of about 350 ° C. In this example, a tantalum thin film having a thickness of 600 nm is formed by sputtering. The substrate temperature when forming the tantalum thin film is 180 ° C., and the sputtering gas is an argon gas containing 6 to 7% nitrogen gas. After the gate electrode patterning, impurity ions are implanted into the active layer semiconductor film to form a source region and a drain region. At this time, the gate electrode serves as a mask to form a self-aligned structure. The present invention can also be applied to a so-called Lightly Doped Drain structure in which a region having an ion implantation concentration lower than that of a source region or a drain region is provided between a channel portion and a drain portion. As the ion doping gas, hydrogen-implanted hydrides of implanted impurity elements such as phosphine (PH3) and diborane (B2H6) having a concentration of about 0.1% to 10% are used. In this embodiment, an ion doping apparatus is used, and phosphine (PH3) diluted in hydrogen is implanted at an acceleration voltage of 100 keV. Injection volume is 1 × 10¹⁶cm^-2It is.
[0070]
Next, an interlayer insulating film is formed by a CVD method or a PVD method (FIG. 3H). In this example, TEOS (Si- (O-CH₂-CH₃)₄) And oxygen and H₂A film of 500 nm is formed at a substrate temperature of 300 ° C. using O as a source gas and argon as a diluent gas. Thereafter, in order to activate the implanted impurity ions and to densify the interlayer insulating film, the temperature is raised to 300 ° C. or higher, and heat treatment is performed for several tens of minutes to several hours. The purpose of activating the impurities is for the reason described in the first embodiment. In this example, heat treatment was performed at 300 ° C. for 1 hour under an atmosphere of oxygen containing 1% steam with a dew point of 80 ° C. The pressure is about 0.5 to 1.5 atmospheres in an oxygen-containing gas (preferably an oxygen concentration of 25 to 100%) containing about 35 to 100 degrees C. of dew point. The temperature is about 100 to 400 degrees C. When the temperature is about 30 minutes to 6 hours, the quality of the gate insulating film and the interlayer insulating film is improved, the etching rate is reduced, and the above problem is eliminated or alleviated.
[0071]
Finally, a contact hole 410 for wiring is formed on the source / drain, the source / drain is taken out, an electrode 411 and a wiring are formed by the PVD method, the CVD method, or the like to complete the TFT.
[0072]
In order to see the basic characteristics and reliability of the fabricated TFT, a BT test was attempted. A change in Ids-Vgs characteristics was measured when a DC of Vds = 5 V and Vgs = 18 V was continuously applied at a temperature of 150 ° C. Measurement time is 60 minutes. FIG. 6 shows a measurement example of the thin film transistor according to the present invention, and FIG. 7 shows a measurement example according to the prior art. Obviously, there is little deterioration compared with the conventional example. Also, the initial characteristics of the thin film transistor according to the present invention are superior. In order to compare these points, we tried to measure the interface state by the usual CV evaluation method. According to this, in the present invention, 4 × 10¹¹[cm^-2・ EV^-1In the conventional example, 1 × 10^{1 2}[cm^-2・ EV^-1] Clearly shows that the former has lower interface states and better characteristics.
[0073]
As can be seen from these results, according to the present invention, a TFT having excellent initial characteristics and reliability can be obtained.
[0074]
【The invention's effect】
As described above, the interface formation process and the gate insulation film formation process of the thin film transistor having the MOS type structure are continuously performed in the same apparatus, so that the excellent characteristics of the MOS interface and the gate insulation film are formed. Can be formed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a process according to a first embodiment of the present invention.
FIG. 2 illustrates an RF plasma apparatus.
FIG. 3 is an explanatory diagram of a process according to a second embodiment of the present invention.
FIG. 4 illustrates a structure of a thin film transistor using a polycrystalline semiconductor film.
FIG. 5 is an explanatory diagram of a process by a conventional method.
FIG. 6 is a characteristic curve of a TFT prepared according to the first embodiment of the present invention.
FIG. 7 is a characteristic curve of a TFT prepared according to the second embodiment of the present invention.
FIG. 8 is a diagram showing a characteristic curve of a TFT prepared by a conventional method.
[Explanation of symbols]
PbOD ■ <V recon membrane
11. Island-like silicon film
12 MOS interface
14 Gate insulation film
15. Source area
17. Drain region
20. Underlayer
30. substrate
61. Contact hole
70. Gate electrode

Claims (1)

In creating a semiconductor thin film transistor having a MOS type structure,
A base protective film forming step of forming a base protective film by depositing a silicon oxide film on a heated translucent substrate by a chemical vapor deposition method using plasma assist with TEOS as a raw material;
An amorphous semiconductor film forming step of forming an amorphous semiconductor film by depositing disilane as a source gas by low-pressure chemical vapor deposition on the formed base protective film;
A crystallization step of crystallizing the formed amorphous semiconductor film by laser irradiation to form a polycrystalline semiconductor film; and
Patterning a polycrystalline semiconductor film by a photolithography method;
A MOS interface forming step of forming a MOS interface by directly oxidizing a patterned polycrystalline semiconductor film by RF plasma in an oxygen atmosphere diluted with an inert gas;
On the formed MOS interface, using the same apparatus as the RF plasma apparatus used in the MOS interface forming process, an oxide film is formed by chemical vapor deposition using RF plasma continuously from the MOS interface forming process. A gate oxide film forming step of depositing and forming a gate oxide film;
Including
The MOS interface forming step includes a step of immersing and cleaning a translucent substrate including a polycrystalline semiconductor film in a solution obtained by mixing and heating H ₂ SO ₄ and H ₂ O ₂ after the crystallization step; The step of immersing the translucent substrate in a solution containing HF and H ₂ O to remove the oxide film on the surface of the polycrystalline semiconductor film; and the solution obtained by mixing and heating HCl, H ₂ O ₂ and H ₂ O A step of cleaning the surface of the polycrystalline semiconductor film by immersing the light-transmitting substrate, further fixing the cleaned light-transmitting substrate to a sample stage of an RF plasma apparatus, and heating the substrate to 20 ° C. to 600 ° C. Thereafter, an inert gas and oxygen are introduced from the gas supply hole of the RF plasma apparatus as oxygen amounts of 1% to 15%, and the exhaust gas flow rate is adjusted on the exhaust hole side of the RF plasma apparatus to adjust the pressure to 100 mTorr to 4000 mTorr. 0.1 W / cm ^A method for producing a thin film transistor, comprising: applying a RF electric field of ^{2 to} 1.5 W / cm ² to generate radical oxygen to oxidize a surface of a polycrystalline semiconductor film to form a MOS interface.

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