JP3237014B2 - Image recording device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus for recording a halftone image, and in particular, corrects multi-gradation input image data for each pixel, and corrects the corrected image. The present invention relates to an improvement in an image recording apparatus that performs image recording based on data.

[Prior Art] Generally, as a method of reproducing a halftone image by a laser printer, a dither matrix method (so-called area gradation method) in which gradation is expressed by a combination of a plurality of pixels, and a gradation is expressed in pixel units A density gradation method, and a combination of the area gradation method and the density gradation method are already known.

In the area gradation method, the number of gradations can be increased by lowering the screen ruling, but on the contrary, there is a problem that the resolution is reduced. On the other hand, the density gradation method can satisfy the demand for increasing the resolution, but conversely raises the problem that it is difficult to increase the number of gradations.

Therefore, conventionally, in order to increase both the number of gradations and the resolution, a method in which the area gradation method and the density gradation method using a screen having a high number of lines are combined is usually adopted.

Next, an example of a method combining the area gradation method and the density gradation method will be described.

For example, as a method for realizing the density gradation method, there is a pulse width modulation method that makes the laser lighting time variable within one pixel.

In this pulse width modulation method, the input image data is converted into density code data having a low number of gradations by appropriately dividing the number of density gradations of the multi-gradation input image data by a threshold value, and based on the density code data. The laser beam is turned on or off to form a latent image corresponding to the density information of the input image data on the photoreceptor (Japanese Patent Application Laid-Open No. Sho 63).
-74386).

In this case, in generating the density code data, when dividing the density gradation level of the input image data by a plurality of predetermined threshold values, the density gradation level of the input image data and the threshold value are determined. A difference error occurs between them, but when this difference error is not considered at all, the number of gradations is only the number of the set thresholds, and a problem occurs that the quality of the final halftone recorded image is significantly impaired.

Therefore, conventionally, the so-called error diffusion method of correcting the density gradation number of the target image data in consideration of the difference error and performing threshold processing on the corrected image data has been proposed. It is usually adopted as a legal amendment.

[Problems to be Solved by the Invention] By the way, such a conventional laser printer employs an error diffusion method as an area gradation method correction in generating the density code data, thereby improving halftone image quality. However, the first technical problem that a unique pattern (texture) by the error diffusion method appears remarkably and gives an unsightly feeling.

In addition, since the area gradation method for reproducing one gradation with a plurality of pixels is added, the second technical problem that the character image is likely to be deteriorated occurs.

That is, the present invention has been made to solve each of the above technical problems, and an image recording apparatus that further improves the reproducibility of a halftone image and maintains good halftone image quality. To provide.

[Means for Solving the Problems] In other words, the present invention for solving the first technical problem is that the multi-gradation input image data is corrected by the correcting device to which the error diffusion method is applied, and the corrected image data is corrected. In an image recording apparatus that performs image recording based on image data, the correction unit generates image data corresponding to a divided area by dividing a density gradation of multi-gradation input image data by a predetermined threshold, A threshold value is switched for each pixel to generate image data on which a predetermined screen pattern is superimposed; and a difference between the image data generated by the generation unit and the corresponding input image data is distributed to peripheral pixels. Error dispersing means.

Further, the invention for solving the first and second technical problems is to correct multi-gradation input image data by a correction means to which an error diffusion method is applied, and to record an image based on the corrected image data. In the image recording apparatus for performing the above, the correction means includes: a generation means for generating image data corresponding to the divided area by dividing the density gradation of the multi-gradation input image data by a predetermined threshold value; Initial error extracting means for extracting a difference between the generated image data and the corresponding input image data for each pixel, and a total initial error in a pixel matrix of a predetermined size composed of a plurality of pixels in each of the vertical and horizontal directions, and the addition result is obtained. Matrix error determination means and the error dispersion means for dispersing the error to a specific pixel in the pixel matrix based on the matrix error data It is obtained by provided.

In this aspect, from the viewpoint of obtaining a reproduced image more faithful to the original image, as the error dispersion means, a pixel matrix having a large initial error extracted by the initial error extraction means as a correction target pixel order of the pixel matrix is used. It is preferable to give priority.

 Here, typical aspects of each invention are shown below.

First, one aspect of the invention for solving the first technical problem is that, as shown in FIG. 1A, an image subjected to pulse width modulation corresponding to the density level of multi-tone input image data DT. Based on an image recording apparatus that turns on or off the beam of the beam scanning unit 1 based on the density signal SD, and visualizes the latent image formed on the photoconductor 2 by the beam scanning with the developing unit 3, Density gradation conversion means 4 for converting the number of density gradations of image data DT according to desired reproduction density characteristics
Density code generating means 5 for generating an image density code SC corresponding to the divided area by dividing the number of density gradations of the image data DT from the density gradation conversion means 4 by a predetermined threshold value; Multi-level modulation means 6 for modulating the pulse width of the image density signal SD based on the image density code SC;
The density code generating means 5 includes a threshold value switching means 7 for switching and setting a different threshold value for each adjacent pixel, and a threshold value corresponding to at least a pixel of interest and pixel data of a previous line corresponding to pixels located before and after the pixel of interest. Correction means 8 for adding the difference data to the current data of the pixel of interest with predetermined weighting, and dividing the number of density gradations of the pixel of interest corrected by the data correction means 8 by a corresponding threshold value into a pixel density code And a code setting means 9 for setting an SC.

One embodiment of the invention for solving the first and second technical problems has a basic configuration (beam scanning unit 1) similar to that shown in FIG. 1A, as shown in FIG. 1B. , Photoreceptor 2, developing means 3, density gradation conversion means 4, density code generation means
5, the multi-level modulation means 6) and the density code generation means 5
The initial density code setting means 11 that sets an initial density code SC0 corresponding to the segmented area when the image data of each pixel is divided by a predetermined threshold, and a threshold and image data corresponding to the initial density code SC0 Coding error data extracting means 12 for extracting coding error data CED comprising the difference of the coding error data CED extracted from the coding error extracting means 12 within a predetermined pixel matrix range. Matrix error determining means 13 for determining matrix error data MED based on
Code correction means 14 for selectively correcting the initial density code SC0 of each pixel in a predetermined pixel matrix range based on MED
Are provided.

In such technical means, the beam scanning unit 1 can be appropriately selected as long as it can scan the photosensitive member 2 with a beam, including a laser scanning unit. Further, the beam scanning unit 1 is operated based on the image density signal SD. Whether the beam is turned on or off with a pulse width corresponding to the image density signal SD is determined based on the relationship with the developing method. It is necessary to form a latent image such that a portion obtains an image recording density corresponding to the image density signal SD.

The photoreceptor 2 can be appropriately selected irrespective of a drum shape or a belt shape. On the other hand, if the developing means 3 can visualize the latent image on the photoreceptor 2, the developer or the developer can be used. A developing method and the like can be appropriately selected.

Further, the density gradation conversion means 4 may be a table in which the converted data is stored in advance, as long as the data can be converted in accordance with the reproduction density characteristics, or an arithmetic operation performed according to a predetermined arithmetic expression. The design can be changed as appropriate, such as by using a circuit.

Further, the density code generating means 5 only needs to include at least a code setting means for dividing the number of density gradations of the multi-gradation image data DT by a predetermined threshold value and forming an image density code. The design, the number of generated image density codes, and the generation method can be changed as appropriate.

For example, if the density code generating means 5 is of a type employing a line screen + error diffusion method, the data correction means 8 for realizing the error diffusion algorithm will be provided. Means 8 is to add difference data between the pixel data of the previous line corresponding to the pixel of interest and pixels located before and after the pixel of interest and the corresponding threshold to the current data of the pixel of interest with a predetermined weight. From the viewpoint of further suppressing the occurrence of, the difference data between the image data of the pixel immediately before the pixel of interest and the threshold value is added to the current data of the pixel of interest with a relatively large weight, in addition to the correction algorithm described above. Is preferred.

In particular, with regard to the threshold value switching means 7 of the density code generating means 5 in the mode of FIG. 1 (a), the setting level of each threshold value may be appropriately selected, but from the viewpoint of increasing the degree of texture reduction. It is preferable to select a threshold value by which a predetermined increment is added to the standard threshold value, and a threshold value by which the same amount of decrease is subtracted from the standard threshold value.

Further, in the density code generation means 5 in the embodiment of FIG. 1B, the size of the matrix and the correction algorithm by the code correction means 15 may be appropriately changed in design, but the reproduction more faithful to the original image can be performed. From the viewpoint of obtaining an image, it is preferable to give priority to a pixel having a large coding error data CED as a correction target pixel order of a predetermined pixel matrix.

The multi-level modulation means 6 may be appropriately designed if the pulse width of the image density signal SD based on the image density code SC can be variably set within a desired range. In this case, the pulse width of the image density signal SD is
The pulse width of the image density signal SD may be unequally changed in order to substantially correct the reproduced image characteristics in consideration of the reproduced image quality. Preferably, it is changed.

As for the method of generating the image density signal SD, for example, a reference pulse of the minimum unit required for setting the pulse width of the image density signal SD is generated, and the reference pulse is multiplied by an integer, The phase shift of the pulse signal based on the clock can be used, and the pulse width of the image density signal SD can be set appropriately according to the phase shift of the pulse width.

In this case, in the former type, the reference pulse is selected on the basis of the change mode of the density signal SD. However, if the frequency of the reference pulse is not set extremely high, the multi-level modulation means is used. Expensive EC as circuit configuration 6
This is preferable because it can be handled with inexpensive TTL without using L. On the other hand, in the latter type, for example, a delay unit can be used as a unit for extracting the phase shift of the pulse width, and the delay amount of the delay unit can be designed to be extracted by a desired arithmetic unit. is there. If the delay amount of the delay means is appropriately selected, the pulse width of the image density signal SD can be set to a desired value, so that it is easy and relatively inexpensive without being restricted by the former type. The circuit can be configured as follows.

The present invention is applicable to all image forming apparatuses such as laser printers and copiers. For example, the present invention has a plurality of developing units 3 using at least different developers, and is provided by a common or individual beam scanning unit 1. In a type in which a plurality of latent images are formed and each latent image is individually developed by the corresponding developing unit 3, basically, the density gradation converting unit 4,
It is necessary to design the density code generating means 5 and the multi-level modulation means 6 so as to provide a duplicate system corresponding to each developing means 3.

In this case, from the viewpoint of simplifying the configuration of the density gradation conversion means 4, the density code generation means 5, and the multi-level modulation means 6 of the plurality of systems, the density gradation conversion means 4, the density code generation means 5, It is preferable that the multi-level modulation means 6 is designed so as to be shared. As for the sharing means, a plurality of systems of image data DT are distinguished by, for example, color information, and a function corresponding to the image data DT in each color is provided. May be provided.

In the technical means as described above, according to the embodiment shown in FIG. 1A, when the density code generation means 5 generates the image density code SC, the multi-tone image data DT includes the line screen. By the + error diffusion method, the image is partitioned by a predetermined threshold value and converted into an image density code SC corresponding to the partitioned area.

At this time, a unique pattern (texture) is generated by the error diffusion method in the halftone image recorded by the above method, but in this embodiment, the threshold value is different for each adjacent pixel. On the other hand, a line screen pattern having half the number of lines of the sampling frequency is superimposed on the unique pattern, thereby suppressing the exposure of the unique pattern.

Further, according to the embodiment shown in FIG. 1 (b), when the density code generation means 5 generates the image density code SC, first, the multi-tone image data DT has a predetermined threshold value for each pixel unit. And the initial density code SC0 according to the area
Is set as

Next, when the coding error data CED including the difference between the image data DT and the threshold value at the time of generating the initial density code is calculated, the coding error data CED of each pixel is added in a predetermined pixel matrix range. , The matrix error data MED is determined. Then, the initial density code of each pixel is selectively corrected in the range of the pixel matrix based on the matrix error data MED.

At this time, since the image density code SC of each pixel is generated in a state where the overall correction based on the overall error of the pixel matrix range is performed, a case where individual correction is performed for each pixel by the line screen + error diffusion method In comparison with the above, the mesh of the line screen is not directly exposed, and a unique pattern by the error diffusion method does not occur.

In the halftone image reproduction method, a line screen with a high number of lines is used to increase the resolution, but the halftone image is faithfully reproduced, for example, a high density portion of a halftone image such as a photograph is crushed. A third technical problem arises that the reproduction is still insufficient.

Therefore, a reference invention for solving the third technical problem is an image recording apparatus that corrects multi-gradation input image data by density gradation conversion means and performs image recording based on the corrected image data. The density gradation converting means includes a range changing means for variably setting a density conversion range of image data according to a mode selection signal indicating one of a character mode and a photograph mode. The density conversion range of the photograph mode is set narrower than that of the photograph mode.

According to another aspect of the present invention, there is provided an image recording apparatus for performing pulse width modulation on multi-tone input image data by multi-level modulation means to record an image. The value modulating means is provided with a pulse width varying means in which the pulse width of the image output data is variably set in accordance with a mode selection signal indicating one of the character mode and the photograph mode. In comparison with this, the pulse width of the image output data in the photograph mode is set narrower.

Furthermore, the apparatus has a plurality of developing units using at least different developers, forms a plurality of latent images by a common or individual latent image forming unit, and develops each latent image individually by a corresponding developing unit. The image recording apparatus may be provided with a density gradation conversion means for converting the density gradation of the multi-gradation input image data in accordance with the characteristics of the plurality of developing means, respectively, or in correspondence with the characteristics of the plurality of developing means. It is preferable to provide a multi-level modulation means for pulse-width-modulating the multi-tone input image data.

In this type of aspect, from the viewpoint of simplifying the device configuration, for example, one density gradation conversion unit is shared for a plurality of systems of input image data, and this shared density gradation conversion unit Any density conversion range may be used as long as the density conversion range is determined based on the information and the density information of the image data is converted in the determined density conversion range. In addition, one generation unit that generates image data corresponding to the divided area by dividing the density gradation of the input image data of a plurality of systems by a predetermined threshold is shared. The density information of the image data is separated into a plurality of systems in accordance with the color information of the image data, and the separated density information of the plurality of systems is transferred to the multi-level modulation means of the plurality of systems, respectively. Means for extracting a same-system image data from a plurality of systems of input image data, and density information of a target pixel by referring to the same-system image data extracted by the same-system data extractor; May be provided.

 Here, typical aspects of each reference invention are shown below.

First, one embodiment of a reference invention for solving the third technical problem has a basic configuration (beam scanning unit 1, photosensitive Body 2, developing means 3, density gradation conversion means 4, density code generation means 5, and multi-level modulation means 6). The density gradation conversion means 4 has a mode indicating one of a character mode and a photograph mode. Select signal
Range changing means 16 for variably setting the density conversion range of the image data in accordance with the MS is provided, and the range changing means 16 provides a narrower density conversion range in the photographic mode than in the character mode.

Here, the range varying means in the mode of FIG. 1 (d)
With regard to 16, it is necessary to experimentally determine the density conversion range corresponding to the character mode and the photographic mode while considering the development characteristics and the characteristics of the multi-level modulation means 6.

According to the aspect shown in FIG. 1D, the density gradation conversion means 4 sets the density conversion range narrower in the photograph mode than in the character mode, so that the reproduced image is faithfully or compressed to the original image. It is reproduced with a different gradation range.

Another aspect of the invention for solving the third technical problem is, as shown in FIG. 1 (e), a basic configuration similar to that of FIG. Body 2, developing means 3, density gradation conversion means 4, density code generation means 5, and multi-level modulation means 6). The multi-level modulation means 6 has a mode selection indicating one of a character code and a photograph mode. There is provided a pulse width varying means 17 in which the pulse width of the image density signal SD is variably set in accordance with the signal MS. It is set.

Here, regarding the pulse width varying means 17 of the multi-level modulation means 6 according to the mode of FIG. 1 (e), a pulse width varying section is separately provided for variably setting the pulse width in the character mode and the photograph mode. Or may be configured to share one pulse width variable unit.

According to the mode shown in FIG. 1E, the multi-level modulation means 6 sets the pulse width of the image density signal SD to be narrower in the photograph mode than in the character mode, so that the reproduced image is faithful to the original image. Alternatively, it is reproduced in a compressed gradation range.

Further, as another reference invention for solving the third technical problem, as shown in FIG. 1 (c), the same basic configuration (beam scanning unit 1, photosensitive member 2, a developing means 3, a density gradation converting means 4, a density code generating means 5, and a multi-level modulation means 6). The density code generating means 5 includes at least a target pixel and pixels located before and after the target pixel. Data correction means 8 for adding the difference data between the corresponding pixel data of the previous line and the threshold to the current data of the target pixel with a predetermined weight, and the density gradation number of the target pixel corrected by the data correction means 8 A code setting means 9 for dividing the image by a threshold into an image density code;
Provided with a modulation pattern switching means 15 for switching the modulation pattern of the image density signal SD to one pixel unit or two pixel units in accordance with a mode selection signal MS indicating one of a character mode and a photograph mode. Is mentioned.

Here, regarding the modulation pattern switching means 15 of the multi-level modulation means 6 according to the embodiment of FIG. 1 (c), the modulation pattern of one pixel unit and two pixel units may be, for example, a pulse width in the case of one pixel unit. Are inflated in order from one direction,
In the case of a two-pixel unit, the pulse width can be appropriately selected, for example, by expanding the pulse width sequentially from both left and right directions.

According to the aspect shown in FIG. 1 (c), when the density code generating means 5 employs the line screen method, the multi-level modulation means 6 sets the number of lines of the line screen in the photograph mode. Since the processing is performed in a state where is switched to 1/2, it is possible to form an image that matches the spatial frequency characteristics of the electronic process, and the tone reproducibility in the high density image portion is improved.

Hereinafter, the present invention will be described in detail based on an embodiment shown in the accompanying drawings.

Example 1 Table of Contents I. Overall Configuration II. Image Processing Unit (1) Basic Configuration (2) Image Reading Unit (2-A) Full Color Sensor (2-B) Sensor Interface Circuit (3) Color Image Information Generation Circuit III. Image Output unit (1) Basic configuration (2) Data distribution circuit (3) TRC (4) Screen generator (4-A) Basic configuration (4-B) Threshold pattern setting circuit (4-B-1) Algorithm (4- B-2) Example of realization circuit (4-C) Error diffusion circuit (4-C-1) Algorithm (4-c-2) Basic configuration of realization circuit (4-C-3) Difference value generation circuit (4-C- 4) Digital filter, lookup table (4-C-5) Operation of error diffusion circuit (5) ROS controller (5-A) Basic configuration (5-B) Multi-level modulation circuit (5-B-1) Basic configuration (5-B-2) Decoder (5-B-3) Left / right gray generator (5-B-4) Left / right selection block, left / right switching signal generator (5-B-5) Selector (5-B-6) ) Operation of multi-level modulation circuit (5-B-7) Modified example VI. Operation of apparatus I. Overall configuration FIG. 2 shows the overall configuration of the present invention applied to a so-called one-pass two-color two-color copying machine. FIG. 3 is a block diagram illustrating, for example, reproducing a two-color image of red (sub color) and black (main color).

As shown in FIG. 2, the two-color copying machine reads a red and black two-color original image and generates two sets of image data as a pair of density data D and a color flag CF. And an image processing unit 20 for outputting after appropriately processing the color flag CF, and the image processing unit 20
A laser printer 110 as an image output unit that reproduces two sets of image data from a pair of density data D and a color flag CF, and visualizes the two sets of image data.
It is composed of

II. Image Processing Unit (1) Basic Configuration In FIG. 3, reference numeral 30 denotes a full-color sensor for optically scanning an original, and reference numeral 40 designates a read signal sequentially output from the full-color sensor 30 in a time division manner for each cell. Is a sensor interface circuit that converts color component data (green: G, blue: B, red: R) of each pixel unit and outputs them in parallel. The full color sensor 30 and the sensor interface circuit 40 read an image. Unit is configured. 70 is each color component data (G, B,
R) is a color image information generation circuit that determines which color of the original image is based on the color image information.
The tone density data D, a sub color flag SCF corresponding to a red (sub color) image, and a main color flag MCF corresponding to a black (main color) image are generated. Reference numeral 90 denotes density data D and a color flag from the color image information generation circuit 70.
This is an editing and processing circuit that performs editing and processing such as enlargement, reduction, and color inversion on SCF and MCF. In this case, since the editing and processing for the density data D8 bits and the color flags SCF and MCF2 bits need only be performed, the editing and processing are performed as compared with the type in which the editing and processing are performed on the two sets of image data (8 bits each). -The circuit configuration of the processing circuit 90 can be simplified.

The density data D and the color flags SCF and MCF from the editing / processing circuit 90 are sent to the laser printer 110 via the interface circuit 100.

In this embodiment, the color flag in the image processing unit 20 has a 2-bit configuration including the main color flag MCF of the sub color flag SCF, but the color flag CF provided to the laser printer 110 is In the interface circuit 100, the color can be changed to a 1-bit configuration expressing sub-colors and other colors.

(2) Image reading unit (2-A) Full-color sensor The full-color sensor 30 is, for example, as shown in FIG.
5 CCDs with a given pixel density (eg 16 dots / mm)
It has sensor chips 30 (1) to 30 (5), and arranges the CCD sensor chips 30 (1) to 30 (5) alternately back and forth with respect to the document scanning direction m, so as to be integrated in a so-called staggered manner. It is a thing.

Each CCD sensor chip 30 (1) to 30 (5)
As shown in the figure, green (G), blue (B), and red (R) filters (eg, gelatin filters) are sequentially applied to each light receiving surface of each cell (photoelectric conversion element) 31 that is obliquely partitioned. It is a coating arrangement. Then, the adjacent green filter cell 31G, blue filter cell 31B, and red filter cell 31R form a set, and an output signal of a level corresponding to the amount of light received from each cell 31 (corresponding to the document reflectance) is generated. The signal is processed as a signal for the pixel P.

(2-B) Sensor Interface Circuit The sensor interface circuit 40 basically includes a color component signal (G, B, R) based on output signals from the CCD sensor chips 30 (1) to 30 (5) arranged in a staggered manner. ) To correct each color component signal (G, B, R) serially processed as a signal from each cell of the CCD sensor chip 30 (1) to 30 (5) in the pixel P unit. And a correction function for a shift in the detection position of each color component signal (G, B, R) in one pixel P.

FIG. 6 is a circuit for realizing the function of aligning the outputs from the staggered CCD sensor chips on one line.

In the figure, each CCD sensor chip 30 (1) to 30
Signals output serially from (5) in units of cells are sequentially transmitted to the AD conversion circuit 42 via the amplifier circuits 41 (1) to 41 (5).
(1) through 42 (5) are input. And each AD
In the conversion circuits 42 (1) to 42 (5), a sensor output signal for each cell according to the amount of received light is output as 8-bit data, for example. Further, latch circuits 43 (1) to 43 (5) for timing adjustment are provided at the subsequent stage of the AD conversion circuits 42 (1) to 42 (5). For the systems of the CCD sensor chips 30 (2) and 30 (4) arranged ahead of the other CCD sensor chips with respect to the other CCD sensor chips, the first-in first-out system is provided after the corresponding latch circuits 43 (2) and 43 (4). FIF
O44, 45 are provided. The FIFOs 44 and 45 delay the output timing of the color component signals for the systems of the CCD sensor chips 30 (2) and 30 (4) and
This is for adjusting the output timing of the same line signal for the systems (1), 30 (3) and 30 (5).

Therefore, while the write timing signal is determined at a predetermined timing, the read timing (delay amount) is determined between the scan lines of the CCD sensor chips 30 (2) and 30 (4) and the scan lines of the other CCD sensor chips. It is determined based on the distance and the original scanning speed of the full-color sensor 30. For example, when the scanning speed is different according to the magnification of the image to be formed, the readout timing is controlled according to the magnification. As described above, when the read timing is made variable by the magnification or the like, the capacities of the FIFOs 44 and 45 are determined on the assumption that the read timing is the latest.

Further, latch circuits 46 (2) and 46 are provided at the subsequent stage of each of the FIFOs 44 and 45.
While (4) is provided, the CCD sensor chips 30 (1), 30
For the systems of (3) and 30 (5), the latch circuit 43 is used.
The subsequent latch circuits 46 (1), 46 (3), 46 (5) are directly connected to the subsequent stage of (1), 43 (3), 43 (5),
Leading CCD sensor chip 30 (2), 30 via 4,45
The color component signal of the system of (4) and the color component signal of the system of the other CCD sensor chip are connected to the respective latch circuits 46 (1) to 46 (46).
In (5), they are aligned as those of the same scanning line, and transferred to the subsequent stage at a predetermined timing. Each latch circuit 46
Looking at (1) to 46 (5), each color component signal is
G → B → R → G → B according to the cell arrangement of the sensor chip
The data is serially transferred in the order of → R →...

FIG. 7 is a circuit for realizing a function of converting each color component signal serially transferred in the system of each CCD sensor chip into a parallel signal for each pixel.

In the figure, a serial / parallel conversion circuit 50 (specifically, 50 (1) to 50 (5)) is provided corresponding to each of the CCD sensor chips 30 (1) to 30 (5).
The serial / parallel circuit 50 includes latch circuits 51G, 51B, and 51R to which color component signals (G, B, and R) serially transferred as described above are input in parallel. The latch circuit 51B synchronizes with a clock signal (B clock) which becomes active at the time of transfer of the color component signal B, and the latch circuit 51R synchronizes with a clock signal (G clock) which becomes active at the time of transfer of G. Each color component signal is latched in synchronization with a clock signal (R clock) that becomes active during transfer.

Further, at the subsequent stage of each latch circuit 51G, 51B, 51R, there is provided a tri-state latch circuit 52G, 52B, 52R for latching again for each pixel in order to adjust the rolling timing, and each tri-state latch circuit 52G, 52B, 52R is the above R
The latch data (color component signal) of the preceding stage is simultaneously re-latched at the falling edge of the clock. Further, the tri-state latch circuits 52G, 52B, 52
The driving / non-driving of R is enabled by an enable signal (i) (i = 1...).
5) is controlled.

The serial / parallel conversion circuits 50 (1) to 50
(5) At the subsequent stage, a memory circuit 54 and a timing control circuit 56 for controlling writing and reading of the memory circuit 54 are provided.

The memory circuit 54 has a dedicated memory for each color component (G, B, R), and writes the enable signal (i) in (1) → (2) → (3) →
The active state is switched in the order of (4) → (5),
In addition, by controlling the write address in accordance with a predetermined rule, one line of data is sequentially arranged in the memory for each color component (G, B, R). Then, by reading out the data of each color component from each dedicated memory sequentially in parallel, the color component data of each pixel is sequentially transferred from one end of one line to the subsequent stage.

Note that the resolution is converted at the memory circuit 54 by the difference between the write timing and the read timing in the timing control circuit 56. For example, a timing control circuit so that the resolution in the system after the memory circuit 54 is 400 SPI
Reference numeral 56 controls the read timing.

FIG. 8 shows a circuit for realizing a correction function for a shift in the detection position of each color component (G, B, R) in one pixel.

As shown in FIG. 4, since the reading position of each color component (G, B, R) is spatially shifted within one pixel due to the structure of the full-color sensor 30, the signal from each cell is directly used as a color component signal. When the processing is performed as described above, a phenomenon that another color pixel occurs at the boundary portion of the black image, that is, a so-called ghost occurs.
Therefore, this correction circuit is for making the reading positions of the respective color components apparently coincide with each other in order to prevent the occurrence of such a ghost.

Specifically, in the arrangement of each cell shown in FIG. 9, when the pixel Pn is focused on, the reading position of each color component is corrected so as to be virtually the position of the cell Gn. As the algorithm, a method is used in which the reading position of each color component is weighted and averaged so as to be the position of the cell Gn in consideration of the adjacent pixel Pn-1.

That is, Gn = Gn (1) Bn = (Bn-1 + 2Bn) / 3 (2) Rn (2Rn-1 + Rn) / 3 (3) Each color component data (Gn, Bn, Rn) Is to be obtained.

More specifically, the correction circuit shown in FIG. 8 is configured so that color component data output in pixel units by the circuit shown in FIG. 7 is input in parallel. And G
A latch circuit 58G is provided for the component system, and a latch circuit 58B is provided for the B component system. At the subsequent stage of the latch circuit 58B, the data latched by the next latch circuit 61 and the latch circuit 58B is 1 bit. A shifter 62 for shifting is provided, an adder 63 for adding the latch data of the latch circuit 61 and the shift data in the shifter 62, and a result of the addition in the adder 63 is used as an address input, and
Is provided with a look-up table (ROM) 64 for outputting the same. For the R component system, the latch circuit 58R
The next latch circuit 65R and a shifter 66 for shifting the data latched by the latch circuit 65 by one bit are provided at the subsequent stage of the latch circuit 58R, and the latch data of the latch circuit 58R is shifted by the shifter 66. An adder 67 for adding data and a look-up table (ROM) 68 for outputting 1/3 of the result of the addition by the adder 67 as an address input are provided.

With such a configuration, in the G component system, the above (1)
Since the expression is realized and shifting by one bit means twice the operation, in the system of the B component, the above expression (2) is expressed by R
In the component system, the above equation (3) is realized respectively.

Each of the color component signals for which the processing in the image reading section has been completed is transferred to a color image information generation circuit 70 described below after performing processing such as shading correction that is generally performed.

(3) Color Image Information Generating Circuit FIG. 10 shows a specific configuration of the color image information generating circuit 70.

In the figure, reference numeral 71 denotes input of G component data and R component data of the color component data transferred from the sensor interface circuit 40 in pixel units, and the difference (RG)
Is a subtraction circuit which receives the B component data and the R component data and calculates the difference (R−B). The subtraction results of the respective subtraction circuits 71 and 72 are input in parallel to the address end of a look-up table 73. The look-up table 73 determines the saturation C, hue and hue of the pixel based on the respective subtraction results. The output of the product of H (H + C) and color judgment is performed, and the reading is performed in units of 8 bits. For example, the upper 5 bits are assigned to the result of (H × C) and the lower 3 bits are assigned to the color judgment output. Have been.

The contents of the lookup table 73 are determined, for example, as follows.

As shown in FIG. 11, the difference (RG) between the red (R) color component and the green (G) color component is plotted on the vertical axis, and the red (R) color component and blue (B) Assuming a color space in which the difference (RB) from the component is set on the horizontal axis, an arbitrary color is specified based on the distance r from the origin O and the rotation angle θ.

In this case, the distance r is a factor that mainly determines the saturation, and the closer to the origin O in the color space, the closer to the achromatic color. The rotation angle θ is a factor mainly determining the hue. For example, "red", "magenta", "blue", "cyan", "green", and "yellow" are distributed in the color space at positions surrounded by broken lines in FIG.

From the relationship described above, (RG) data and (R-
B) Based on the data, Is determined, and color determination is performed at a position in the color space specified by the data r and θ.

Table 1 below shows an example of the color judgment data in this embodiment.

The saturation C is obtained by calculating (RG) data and (RB)
It is determined from the data in accordance with the relationship between the distance r from the origin and the saturation C determined by the arithmetic expression (4) of the first embodiment, for example, the relationship shown in FIG. 12 determined experimentally. In FIG. 12, when the distance r becomes smaller than the predetermined value R0, the saturation C is forcibly set to "0" as an achromatic color.

Further, the hue H is a relationship between the rotation angle θ and the hue determined by the above equation (5) from the (RG) data and the (RB) data, for example, as shown in FIG. 13 determined experimentally. Is determined according to the relationship. In FIG. 13, when the rotation angle θ is smaller than the predetermined value θ0, the hue H is forcibly set to “0”.

It should be noted that FIG. 12 and FIG.
The relationships shown in the figure are variously determined according to the color separation capability required for the system.

In FIG. 10, among the respective color component data input in parallel on a pixel basis, the G component data is input to a 0.6-times multiplication circuit 74, the B component data is input to a 0.1-times multiplication circuit 75, and R The component data is input to a multiplication circuit 76 of 0.3 times. Then, the multiplication results of the multiplication circuits 74, 75, and 76 are respectively input to the addition circuit 77, and the addition results V and V = 0.6G + 0.3R + 0.1B of the addition circuit 77 are provided as brightness data of the pixel at the subsequent stage. It is to be transferred.

The lightness data V is based on the fact that the spectral sensitivity curve of the G component signal in the image sensor (full color sensor 30) has a characteristic close to that of a human relative luminous efficiency curve, and the color data (G, B, R) Based on the G component data, it is generated by adding the values of the B component data and the R component data to its value. Each coefficient (multiplied value in each multiplying circuit) in the equation for determining the brightness V is finally determined by the spectral sensitivity characteristics of the image sensor, the spectral distribution of the exposure lamp, and the like.

Note that the brightness data V
, It is also possible to use only the G component data.

The output (H × C) relating to saturation and hue from the look-up table 73, the color judgment data and the brightness data V from the adder 77 are input to the next look-up table 78 as an address input. It has a function of outputting color density data Dc corresponding to the input.

 Specifically, color density data Dc determined according to Dc = K × C × H × V is output for each of the above inputs.

Here, K is a coefficient that varies depending on the color determination data. Since chromatic colors and achromatic colors feel brighter than chromatic colors, K is used to match the lightness levels of the chromatic colors and achromatic colors. The value is experimentally determined in advance in accordance with the determination color, and the value is set to a value within a range of, for example, about 1.1 to 1.3.

The color judgment output (3 bits) from the above-mentioned lookup table 73 and the color selection data set in the latch circuit 80 are input to the matching circuit 79, and when the color judgment output matches the color selection data, the matching circuit The output of 79 rises to high level. Since this color selection data is set in the latch circuit 80 based on an operation input by an operator or a setting input by a dip switch or the like, 3-bit data corresponding to a color to be reproduced as a sub-color (Table 1 of the first embodiment). See). The output of match circuit 79 is
It functions as a sub color flag SCF indicating whether it is a sub color (for example, red) set by color selection, and further,
This is the output selection signal (SEL) of the selection circuits 81 and 82.

The selection circuit 81 outputs the brightness data V according to the state of the selection signal.
And a function of switching between "0" data and "0" data when the selection signal is at a high level, and brightness data V when the selection signal is at a low level.

On the other hand, the selection circuit 82 stores the color density data Dc from the lookup table 78 and the selection circuit 81 in accordance with the state of the selection signal.
Has a function of switching the data from the selector circuit 81. When the selection signal is at a high level, the color density data Dc is output, and when the selection signal is at a low level, the data from the selection circuit 81 is output. .

In addition, the output bit of the selection circuit 81 is directly
And a main color flag indicating whether the output of the OR circuit 83 is a main color (for example, black) or not.
While functioning as the MCF, the output of the selection circuit 82 is transferred to the subsequent stage as density data D.

In the color image information generation circuit 70 as described above, in the main color (black) area of the original image, the output of the matching circuit 79 becomes low level, and the brightness data V from the addition circuit 77 is directly selected by the selection circuits 81 and 82. Are transferred to the subsequent stage as density data D.

At this time, since the brightness data V is not "0", the main color flag MCF goes to a high level, and since the output of the matching circuit 79 is at a low level, the sub color flag SCF goes to a low level (the main color flag SCF in FIG. 14). Area Em
reference).

In the sub color area (red) of the original image,
The output of the matching circuit 79 goes high, and the color density data Dc from the look-up table 78 is transferred to the subsequent stage as density data D via the selection circuit 82.

At this time, since the output of the selection circuit 81 is “0”, the main color flag MCF becomes low level, and the matching circuit 79
Since the output of is high level, the sub color flag SC
F goes high (sub-color area E in FIG. 14)
s).

Further, in the background area (density “0”) of the original image,
Since the output of the selection circuit 81 is “0” and the output of the matching circuit 79 is also low, the density data D becomes “0”, and both the main color flag MCF and the sub color flag SCF are low. (See the background area En in FIG. 14).

In this embodiment, the color flag of each image data of the document is represented by 2-bit data of the main color flag MCF and the sub color flag SCF as shown in Table 2 below.

Each of the arithmetic circuits is driven in synchronization with each pixel under the control of a timing control circuit (not shown), and the density data D and the color flags (MCF, SCF)
Are sequentially transferred to the subsequent editing / processing circuit 90 as data forming a pair of the same pixels.

III. Image Output Unit (1) Basic Configuration FIG. 15 shows a so-called one-pass, two-color (for example, red and black in this embodiment) laser printer 110 as an image output unit used in this embodiment.

In the figure, reference numeral 120 denotes, for example, a positively charged photoconductor,
Reference numeral 21 denotes a charging corotron for pre-charging the photoreceptor 120, 122 denotes a dual beam scanning unit (hereinafter referred to as ROS [Raster Output Scanner]) used in this embodiment, and 123 denotes a bias type using, for example, a positive red toner. A first developing device, 124 is a bias type second developing device using, for example, a black toner of negative polarity, 125 is a pre-transfer treatment corotron that aligns the polarity of the toner image on the photoconductor 120, and 126 is a photoconductor on the recording sheet 127. A transfer corotron for transferring the toner image on 120, 128 is a recording sheet electrostatically attached to the photoconductor 120 side
127 is a neutralizing corotron for removing 127, 129 is a photoconductor 120
A cleaner 130 for removing the upper residual toner, an eraser lamp 130 for removing the residual charge on the photoconductor 120, and a fixing device 131 for fixing the toner image on the recording sheet 127 after the transfer process.

The image reproduction characteristics of the recorded image density with respect to the input image density of the first developing device 123 and the second developing device
They are different as shown by Ys and Ym in the figure.

The details of the ROS 122 used in this embodiment will be described with reference to FIGS. 15 and 16.

In the figure, 141 is a semiconductor laser for image formation of the first color, 142 is a semiconductor laser for image formation of the second color, 143 is a polygon mirror that reflects beams Bm from both lasers 141 and 142 at different angles, and 144 is a mirror. The polygon motor, 145 is an fθ lens, 146 is a mirror for guiding the beam Bm from the laser 141 of the first color to the first exposure unit E1 located in front of the first developing unit 123 of the photoconductor 120, and 147 is a laser for the second color. Mirrors 148 and 149 for guiding the beam Bm from 142 to the second exposure unit E2 located after the first developing device 123 of the photoconductor 120 detect the scanning start positions of the first and second color laser beams, respectively.
SOS sensor.

The drive control system of the ROS 122 is configured as follows.

In FIG. 15, reference numeral 20 denotes an image processing unit that outputs multi-tone image data of the first color (red) and the second color (black) in a state where the data is separated into density data D and color flags CF.
150 is the density data D sent from the image processing unit 20
Image data Ds, D based on
m, and a first TRC (Ton) 151 and 152 for converting the density level of the image data Ds and Dm distributed by the data distribution circuit 150 according to the reproduced image density characteristic.
e Reproduction Controler), Second TRC, 153 and 15
4 is a first and second screen generator for separately processing each image data Ds, Dm and generating image density codes SCs, SCm corresponding to each image data, 155 is an image from the first screen generator 153 The FIFO 156 temporarily stores and outputs the density code SCs, and outputs the image density code SCm from the second screen generator 154 to the first exposure unit E1.
And a gap memory 157 for storing and outputting a scan time corresponding to the gap Gp between the first exposure unit E2 and the second exposure unit E2.
An S controller, 158 is a second ROS controller for driving and controlling the second color laser 142, 159 and 160 are respective laser drivers, and 161 is a motor driver of the polygon motor 144.

Note that the first ROS controller 157 controls the lasers 141 and 142 so that the exposure unit is an image unit, and the second ROS controller 158 is an unexposed unit as an image unit.

Next, a basic operation of the laser printer 110 according to this embodiment will be described.

First, the density data D and the color flag CF from the image processing unit 20 are distributed to two systems of image data Ds and Dm by the data distribution circuit 150, and are subjected to data conversion by the TRCs 151 and 152. At 153 and 154, the image density codes are converted into two systems of image density codes SCs and SCm, and thereafter, first through the FIFO 155 or the gap memory 156,
It is sent to the second ROS controller 157,158.

At this time, first, the first ROS controller 157
By driving the polygon motor 144 and the polygon motor 144, a latent image Z1 having an exposed portion as an image portion as shown in FIG. When the latent image Z1 is developed by the first developing device 123 under the first developing bias VB1, a first toner image T1 is formed as shown in FIG.

Thereafter, the second ROS controller 158 drives the laser 142 to form a latent image Z2 in which a non-exposed portion becomes an image portion as shown in FIG. 18B in the second exposed portion E2 of the photoconductor 120. You.
When the latent image Z2 is developed by the second developing device 124 under the second developing bias VB2, a second toner image T2 is formed as shown in FIG.

Then, after the toner images T1 and T2 are aligned in polarity by the pre-transfer treatment corotron 125, they are transferred to the recording sheet 127 by the transfer corotron 126, and then fixed by the fixing device 131. ing.

(2) Data distribution circuit FIG. 19 shows a specific configuration of the data distribution circuit 150.

That is, the data distribution circuit 150 outputs the color flag CF.
(In this embodiment, the pixels in the background area are treated as being included in the main color area, and the pixels in the sub color area are set to the high level, and the pixels in the other areas are set to the low level. ), Two selection circuits 171 and 172 whose outputs are selected from two systems of input signals (A and B).

In this case, the density data D is stored in the selection circuit 171.
Is input to the input terminal B of the selector circuit 172 and the input terminal A of the selection circuit 172, and "0" data is input to the input terminal A on the opposite side of the selection circuit 171 and the input terminal B on the opposite side of the selection circuit 172, respectively. ing. These selection circuits 171 and 172 select an input signal on the A side by a low level control input and an input signal on the B side by a high level control input, and the color flag CF is the control signal. The output of one selection circuit 171 is transferred as sub-color density data Ds, and the output of the other selection circuit 172 is transferred as main color density data Dm to the subsequent stage in pixel units.

(3) TRC The first TRC 151 cooperates with the first ROS controller 157 to obtain a desired recording image reproduction characteristic of the first developing unit 123, for example, a linear one as shown in the first quadrant (I) of FIG. A sub-color conversion table (look-up table) for pre-converting the sub-color density data Ds before coding it in the first screen generator 153;
The second TRC 152 cooperates with the second ROS controller 158 to set the recording image reproduction characteristic of the second developing device 124 to a desired one, for example, the second
A main color conversion table (lookup) for pre-converting the main color density data Dm before coding by the second screen generator 154, which is corrected to a linear one like the first quadrant (I) in FIG. Table).

More specifically, if the first TRC 151 assumes that the density data corresponding to the input image density, for example, the sub-color density data Ds is a curve like the fourth quadrant (IV) in FIG. 20, This sub-color density data Ds is density converted as shown by a dotted line in the third quadrant (III) of FIG. In this case, when the converted data is subjected to pulse width modulation by the first ROS controller 157 via the first screen generator 153, the characteristics of the input density data to the screen generator and the output image density (hereinafter abbreviated as SG-IOT characteristics) Is obtained as shown by the dotted line in the second quadrant (II) in FIG. 20, and as a result, the linear characteristic as shown in the first quadrant (I) in FIG. 20 is obtained.

The second TRC 152 stores density data corresponding to the input image density, for example, main color density data Dm in FIG.
Assuming that the curve is a quadrant (IV), the main color density data Dm is subjected to density conversion in the third quadrant (III) of FIG. 20 as shown by a solid line. In this case, when the converted data is pulse width modulated by the second ROS controller 158 via the second screen generator 154, the SG-
The IOT characteristic is obtained as shown by the solid line in the second quadrant (II) in FIG. 20, and as a result, the linear characteristic as shown in the first quadrant (I) in FIG. 20 is obtained.

The reason for performing data conversion in each of the TRCs 151 and 152 as described above is as follows.

That is, as described later, each of the above ROS controllers 1
As for the pulse width modulation characteristics of 57 and 158, the number of modulations of the pulse width is usually limited. Therefore, the SG-IO for linearly correcting the recorded image reproduction characteristics in the third quadrant of FIG.
Although it may be difficult to obtain T characteristics,
In this embodiment, since the data can be converted in advance by the TRCs 151 and 152, it is possible to easily obtain the SG-IOT characteristics required for linearly correcting the recorded image reproduction characteristics.

In this embodiment, the logarithmic amplifier is not provided in the sensor interface circuit 40.
Reference numeral 1152 also has a function of converting light amount data corresponding to the input image density into density data.

(4) Screen generator (4-A) Basic configuration Screen generators 153 and 154 in this embodiment
Is an image density code of 5 gradations (including the zero density level) from the input image data of 256 density gradations (including the zero density level)
It is output as SC (corresponding to SCs and SCm in FIG. 15).

FIG. 21 shows each screen generator according to this embodiment.
It is a block diagram which shows the basic structure of 153,154.

In the figure, reference numeral 180 denotes 8-bit input image data D
A buffer for temporarily storing T (corresponding to the sub-color density data Ds or the main color density data Dm) and then outputting the image data. The image data DT from the buffer 180 is input to the comparison circuit 240 via the error diffusion circuit 200. The error diffusion circuit 200 and the comparison circuit 240 have a threshold pattern setting circuit 1
After the threshold pattern THP set at 90 is input and error diffusion processing and comparison processing are performed at the error diffusion circuit 200 and the comparison circuit 240, respectively, the output from the comparison circuit 240 is output to the density code generator 250. The image density code SC (corresponding to the sub-color image density code SCs or the main color image density code SCm) is generated by performing a predetermined conversion.

(4-B) Threshold Pattern Setting Circuit (4-B-1) Algorithm In this embodiment, the threshold pattern setting circuit 190 sets a plurality of threshold values in encoding the multi-tone image data DT. And different A-sequence patterns and B-sequence patterns are provided for each adjacent pixel.

 First, an algorithm for setting a threshold will be described.

Now, for 256 gradation data (including “0” data), n
FIG. 22 (a) shows an example in which the number of thresholds is set.
As shown in the table, each threshold value TH R1, TH R2.
H Rn is reduced by a predetermined variation ΔTH to obtain an A-sequence pattern, while each threshold TH R1, TH
R2... TH Rn may be increased by a predetermined change ΔTH to form a B-sequence pattern.

More specifically, each of the threshold values TH of the standard pattern
R1, TH R2... TH Rn are set, for example, as in the following equation (6).

On the other hand, thresholds TH A1, TH A2,.
... TH An is set, for example, according to the following equation (7). However, the change ΔTH is 255 / (n × 4) (the same applies to the following B sequence pattern).

On the other hand, each threshold TH B1, TH B2... TH Bn of the B sequence pattern
Is set, for example, according to the following equation (8).

In this embodiment, in order to equally divide the area divided by each threshold value in both the A-sequence pattern and the B-sequence pattern, an imaginary threshold value represented by the following equation (9) is set. It has become so.

TH A0 = TH A1−255 / n TH An + 1 = TH An + 255 / n TH B0 = TH B1−255 / n TH Bn + 1 = TH Bn + 255 / n (9) In such a threshold value setting method, the threshold number n = FIG. 22 (b) shows the threshold value of FIG. 22. Each threshold value of the A-sequence pattern and the B-sequence pattern is expressed as shown in Table 3 below.

(4-B-2) Example of Realized Circuit FIG. 23 is a diagram showing a threshold pattern setting circuit 19 configured according to the algorithm described above.
A specific example of 0 is shown.

In the figure, the threshold pattern setting circuit
190 has six threshold setting units 191 (specifically,
191 (0) to 191 (5)), and each threshold setting section 191 includes an A-sequence threshold setting switch 192 for an A-sequence pattern, a B-sequence threshold setting switch 193 for a B-sequence pattern, and an A-sequence Threshold data TH Ai, TH set by threshold setting switch 192 and B-sequence threshold setting switch 193
A selector 194 for selecting Bi (i = 0... 5) and a flip-flop 195 for dividing a video clock signal (hereinafter referred to as a V clock signal) VCK by 2 to generate a selection signal for the selector 194. The threshold signals TH0 to TH5 from the respective threshold setting units 191 (0) to 191 (5) alternate between A sequence patterns (TH A0 to TH A5) and B sequence patterns (TH B0 to TH B5). Repeat.

(4-C) Error Diffusion Circuit (4-C-1) Algorithm The error diffusion circuit 200 used in the present embodiment is configured to separate the image data DT and the threshold TH generated when the image data DT is divided by the predetermined threshold TH. The image data DT is corrected so as to suppress the influence of the difference data (error data) between them.

FIG. 24 is an explanatory diagram showing an algorithm of the error diffusion circuit 200 according to this embodiment.

In the figure, the i-th pixel Pj (i) of the j-th line is set as a target pixel, and its image data is set as X, while the i−1, i, i + 1-th pixels Pj−1 (i) of the j−1 line are used. -1), Pj
-1 (i) and Pj-1 (i + 1) are represented by A, B, and C, respectively.
If the difference data of the pixel Pj (i−1) immediately before the pixel of interest Pj (i) is D, the corrected image data X ′ of the pixel of interest Pj (i) is expressed by the following equations (10) and (11). It is calculated. Note that Δ
X is difference correction data, and k1 to k4 are correction coefficients for performing weighting according to the degree of influence of the difference data of each pixel.

ΔX = k1A + k2B + k3C + k4D where Σki (i = 1 to 4) = 1 (10) X ′ = X + ΔX (11) In particular, in this embodiment, k1 = 0.2, k2 = 0.5, k3 =
0.2 and k4 are set to 0.1.

FIG. 25 shows the values of the difference data used in this embodiment and their polarities.

In the figure, NO.0 to NO.4 indicate the division number of the density gradation number of the image data DT, and in the case of the A-sequence pattern, NO.0: TH A0 to TH A1-1 NO.1: TH A1 to TH A2-1 NO.2: TH A2 to TH A3-1 NO.3: TH A3 to TH A4-1 NO.4: TH A4 to TH A5-1 NO.0: TH B0 to TH B1-1 NO.1: TH B1 to TH B2-1 NO.2: TH B2 to TH B3-1 NO.3: TH B3 to TH B4-1 NO.4 : TH B4 to TH B5-1.

The difference data ΔDT in each segmented area is based on the intermediate position image data (eg, (16 + 80) / 2 in the A-sequence pattern No. 1) located at the midpoint of each segmented area, The difference from the position image data is represented by ± polarity.

Such correction using the difference data ΔDT having ± polarity is preferable in that the output gradation characteristics with respect to the input gradation can be faithfully reproduced, as compared with, for example, correction using difference data having only + polarity or − polarity. .

(4-C-2) Basic Configuration of Realized Circuit Based on such a principle, the above-described error diffusion circuit 200 is configured as shown in FIG. 26, for example.

In FIG. 1, reference numeral 201 denotes an adder.
The one input terminal 01 receives 8-bit image data DT from the buffer 180. Also, the sign
Reference numeral 202 denotes a latch circuit that temporarily stores output data from the adder 201 and outputs the data. The output data of the latch circuit 202 is input to one input terminal of the adder 203. Further, reference numeral 204 denotes a latch circuit for temporarily storing the output data of the adder 203 and then outputting the data. The output data of the latch circuit 204 is sent to the comparison circuit 240.

Reference numeral 190 denotes a threshold pattern setting circuit for alternately setting each threshold data TH for dividing the number of density gradations of the image data DT into an A-sequence pattern and a B-sequence pattern. 206 denotes an image from the latch circuit 204. Using the data DT, the threshold data TH from the threshold pattern setting circuit 190, and the address data ADT described later as input data, difference data in a pixel one line before (corresponding to difference data A, B, and C shown in FIG. 24) The difference data ΔDT from the difference value generation circuit 206 is stored in the FIFO 207 for one line, and the difference data of the correction pixel for each pixel of interest is collected by the digital filter 208. Is to be included. The digital filter 208 performs a predetermined operation using the difference data A, B, and C of the correction pixel, and outputs data of k1A + k2B + k3C. It is designed to be input to the input terminal.

Reference numeral 209 denotes image data from the latch circuit 204.
DT and the threshold data TH from the threshold pattern setting circuit 190 as input data is a lookup table for generating correction data k4D of the pixel immediately before the target pixel, and the correction data k4D from the lookup table 209 is The signal is input to one input terminal of the adder 203.

(4-C-3) Difference Value Generation Circuit FIG. 27 shows a specific configuration of the difference value generation circuit 206.

In the figure, reference numerals 211 to 215 denote threshold data (for example, TH0 and TH1, TH3 and TH4) adjacent to each other of the respective threshold setting units 191 (0) to 191 (5) in the threshold pattern setting circuit 190. Adders to be added, 216 through 220 are dividers that divide the added data from the adders 211 through 215 by 、, and 221 through 225 select the divided data from the dividers 216 through 220 on the OC port. This is a latch circuit that latches when a signal is input.

Reference numeral 226 denotes output ports Q0 to Q0 in accordance with address data ADT (4-bit data in this embodiment) described later.
One of Q4 is a decoder selected as a select signal, and signals from Q0 to Q4 are input to OC ports of latch circuits 221 to 225 from output ports. The contents of the decoder 226 are shown in Table 4 below.

Further, reference numeral 227 denotes a subtractor for subtracting one of the selected latch circuits 221 to 225 from the number of density gradations of the input image data DT. The subtracter 227 outputs 7-bit difference data ΔDT and 1 The bit polarity data m is output.

In such a difference value generation circuit 206, the threshold pattern setting circuit 190, the adders 211 through
215 and dividers 216 to 220 are for calculating the intermediate position image data MDT in the respective divided areas NO.0 to NO.4 of the density gradation number of the image data DT. One of them is selected in accordance with the address data ADT, and the selected latch circuit latches the corresponding intermediate position image data MDT and sends it to the subtractor 227,
Reference numeral 227 outputs difference data ΔDT between the input image data DT and the intermediate position image data MDT together with the polarity data m.

(4-C-4) Digital Filter, Look-Up Table The digital filter 20 used in this embodiment
The details of 8 are shown in FIG.

In the figure, reference numerals 231 to 233 denote FIFCs shown in FIG.
A latch circuit of a three-stage configuration for sequentially latching the differential data ΔDT sequentially read out from the pixel unit 207 in pixel units.
Is the correction coefficient k for the output data of the first-stage latch circuit 231.
235 is a coefficient multiplier that performs an operation of multiplying the output data of the second-stage latch circuit 232 by the correction coefficient k2, and 236 is a coefficient multiplier that performs an operation of multiplying the correction data by the correction coefficient k2. A coefficient multiplier for performing an operation of multiplying the correction coefficient k3,
An adder 237 adds the output data of the coefficient multipliers 234 to 236.

Such a digital filter 208 causes the three-stage latch circuits 231 to 233 to latch the difference data A, B, and C (see FIG. 24) of the preceding three pixels, and the coefficient multipliers 234 to 236 Each difference data A, B, C and each correction coefficient k
After multiplying by 1, k2, and k3, they are added by an adder 237, and k1A + k2B + k3C is output.

Furthermore, the contents of the lookup table 209 are as follows:
Image data DT and threshold data TH as address signals,
The difference correction data k4D obtained by multiplying the difference data ΔDT (corresponding to D in FIG. 24) by the correction coefficient k4 is stored together with the polarity data in a readable manner.

(4-C-5) Operation of Error Diffusion Circuit Therefore, according to the error diffusion circuit 200 of this embodiment, as shown in FIG. When input to the terminal, the difference data of the three pixels one line before (A, B,
First correction difference data [k1A + k2B + k3C] obtained by multiplying the correction coefficient k1, k2, and k3 by the correction coefficient k1, k2, and k3 are output from the digital filter 208 and input to the other input terminal of the adder 201. On the other hand, the LUT 209 outputs second correction difference data [k4D] obtained by multiplying the difference data (corresponding to D in FIG. 24) of the pixel immediately before the target pixel by the correction coefficient k4.

In this state, in the adder 201, X + (k1A +
k2B + k3C), and this data is stored in the latch circuit.
At the stage of being input to one input terminal of the adder 203 through 202, the second correction difference data [k4D] is added, and the latched circuit 204 has corrected image data X ′ of the target pixel, that is, X + ΔX, (however, ΔX: k1A + k2B + k3C
+ K4D) is latched, and the corrected image data X 'is sent to the comparison circuit 240 at the subsequent stage.

(4-D) Comparison Circuit and Density Code Generator As shown in FIG. 29, the comparison circuit 240 includes four digital comparators 241 to 244, and one input terminal A of each comparator 241 has an error diffusion circuit. The corrected image data DT from 200 is input,
At the other input terminal B of each of the comparators 241 to 244, threshold data TH1 to TH4 (in this embodiment, A1 to T4) from the four threshold setting units 191 (1) to 191 (4) of the threshold pattern setting circuit 190 are provided. A series pattern and a B series pattern are alternately repeated in adjacent pixel units and output), and when A ≧ B, each comparator 24
The output of 1 to 244 is set to "1".

The comparators 241 to 244 output 4-bit address data ADT (specifically, [0000] [000
1] [0011] [0111] [1111]), and the 4-bit address data ADT is converted to 3 by the coder 251 constituting the density code generator 250 in order to simplify the subsequent processing.
Bit image density code SC (specifically, SC (0) = 000,
SC (1) = 001, SC (2) = 011, SC (3) = 101, SC (4)
= 111).

The area number of the input image data and the address data AD
The relationship between T and the image density code SC is as shown in Table 5 below.

(5) ROS Controller (5-A) Basic Configuration FIG. 30 schematically shows the first ROS controller 157 and the second ROS controller 158.

The first ROS controller 157 receives a predetermined V clock signal VC
A synchronous signal generating circuit 261 for generating K, and a polygon motor 14
4 and a FIFO synchronous with the V clock signal VCK from the synchronization signal generation circuit 261.
An image density code SC (corresponding to SCs) from 155 is taken in, and a multi-level modulation circuit 265 for modulating the pulse width of the image density signal SD in accordance with the image density code SC is provided.

The synchronizing signal generation circuit 261 is connected to the V clock signal VCK from the video clock generator 262 and the sensor amplifier.
This is to generate a synchronization signal in which the detection signal of the first SOS sensor 148 amplified in 263 is phase-matched. The polygon motor controller 264 controls the driving of the polygon motor 144 by sending a motor control clock signal SM to the motor driver 161. Further, the multi-level modulation circuit 265 controls the driving of the first laser 141 by transmitting the image density signal SD to the laser driver 159.

Further, the second ROS controller 158 has basically the same configuration as the first ROS controller 157 except that the polygon motor controller 264 is not provided, and the second ROS controller 158 is connected to the V clock signal VCK from the video clock generator 272. , Sensor amplifier
A synchronization signal is generated by synchronizing the detection signal of the second SOS sensor 149 amplified by 273 with a phase, and the image density code SC (corresponding to SCm) from the gap memory 156 is fetched and output at this synchronization signal timing. It comprises a signal generation circuit 271 and a multi-level modulation circuit 275 that modulates the pulse width of the image density signal SD based on the image density code SC output from the synchronization signal generation circuit 271.

(5-B) Multi-level modulation circuit (5-B-1) Basic configuration The multi-level modulation circuits 265 and 275 according to this embodiment perform optimal image reproduction according to a reproduction image mode (character mode or photograph mode). Since the basic configuration is substantially the same, the multilevel modulation circuit 265 will be described below as an example.

FIG. 31 is a block diagram showing details of the multi-level modulation circuit 265 according to this embodiment.

In the figure, reference numeral 281 denotes a 3-bit image density code S
This is an interface for taking C into the multi-level modulation circuit. The image density code SC taken in the interface 281 is latched by the latch circuit 282 in synchronization with the V clock signal VCK. And the latch circuit
The image density code SC from 282 is a P-ROM decoder
The selection code b (specifically, b (BK), b (GY
3), b (GY2), b (GY1), b (W)).

On the other hand, reference numeral 284 uses a phase shift of a pulse signal based on the V clock signal VCK to convert a modulation signal having a pulse width corresponding to a halftone image density code into two patterns (specifically, a pattern that spreads sequentially from the left side and a Left and right gray generators that are generated in
The left modulation signals LGY1 to LGY3 of the pattern spreading from the left and the right modulation signals RGY1 to RGY3 of the pattern spreading from the right from the left and right gray generator 284 are input to the left and right selection block 285. Reference numeral 286 denotes a mode select signal indicating either the character mode or the photograph mode.
A left / right switching signal generator for appropriately generating 1,0 left / right switching signals LRS according to the MS, and this left / right switching signal LRS is sent to the left / right selection block 285. Then, the left / right selection block 285 outputs the left modulation signal according to the left / right switching signal LRS.
LGY1 to LGY3 or right modulation signals RGY1 to RGY3 are selected and output, and either the left modulation signal or the right modulation signal is transmitted as modulation signals GY1 to GY3. Further, the modulation signals GY1 to GY3 from the left / right selection block 285, the modulation signal BK corresponding to the maximum image density code, and the modulation signal W corresponding to the zero image density code are input to the selector 287. One of the modulation signals is selectively operated by the selection code b of 283, and the selected modulation signal is generated as the image density signal SD.

(5-B-2) Decoder The contents of the decoder 283 used in this embodiment are shown in Table 6 below.

(5-B-3) Left and right gray generator FIG. 32 shows details of the left and right gray generator 284 used in this embodiment.

In the figure, reference numeral 301 denotes a frequency divider that divides the V clock signal VCK by half, and 302 and 303 delay the pulse signal from the frequency divider 301 by a plurality of predetermined delay times. And a second delay line, 304 is a temperature-stable chip composed of a delay line having the same configuration as the above-described delay lines 302, 303, 305 to 311 are CMOS gates for waveform shaping, 312 to 314 are EOR gates, and 315 to 317 are AND gates. It is.

In this embodiment, the first and second delay lines 30
2,303 is an inverter input tap 3 as shown in FIG.
02 and a plurality of delay elements 321 to 326 connected in series to the inverter input tap 320 (in this embodiment, the delay amount of each delay element is set to a predetermined value in advance).
, And inverter output taps 327 to 332 that are drawn from the terminal portions of the delay elements 321 to 326. The input tap position is indicated by IN, and the output tap position is indicated by TP (specifically, TP1 to TP6).

Then, the input tap IN of the first delay line 302
, An output from the frequency divider 301 is input, and an output from the output taps TP2 to TP4 of the first delay line 302 is input to one terminal of the EOR gates 312 to 314 via the CMOS gates 306 to 308. Meanwhile, the first delay line 302
The output from the output tap TP6 of the second delay line 303 is input to the input tap IN of the second delay line 303, and the output from the output tap TP3 to TP5 of the second delay line 303 is input to the AND gate 315 through the CMOS gate 309 to 311. 317 are input to one of the input terminals. The output from the output tap TP1 of the temperature stable chip 304 is
EOR gates 312 through 314 through 5 and AND gate 31
These are input to the other input terminals 5 to 317, respectively.

In such a circuit configuration, the outputs of the EOR gates 312 to 314 are provided as left modulation signals LGY1 to LGY3, and the outputs of the AND gates 315 to 317 are output as right modulation signals.
It is provided as RGY3, RGY2, RGY1.

(5-B-4) Left / right selection block and left / right switching signal generator FIG. 34 shows details of the left / right selection block 285 and the left / right switching signal generator 286 used in this embodiment.

In the figure, a left and right selection block 285 includes AND gates 341 to 346 to which left modulation signals LGY3, LGY2, LGY1 and right modulation signals RGY3, RGY2, RGY1 from the left and right gray generators 284 are input to one input terminal. Or gate 34
7 to 349 and an inverter 350 to which an output from the left / right switching signal generator 286 is input. The output from the left / right switching signal generator 286 is input to the other input terminal of the AND gates 341 to 343, and the output of the inverter 350 is input to the other input terminal of the AND gates 344 to 346. The outputs of the AND gates 341 and 344 are taken out as a modulation signal GY3 through an OR gate 347, the outputs of the AND gates 342 and 345 are taken out as a modulation signal GY2 through an OR gate 348, and the outputs of the AND gates 343 and 346 are taken out. Is extracted as a modulation signal GY1 through

The left / right switching signal generator 286 includes a flip-flop (hereinafter abbreviated as FF) 351 for dividing the V clock signal VCK by half, an output of the FF 351 and a mode select signal.
And a NAND gate 352 to which the MS is input.

(5-B-5) Selector FIG. 35 shows a selector 287 used in this embodiment.
The details are shown below.

In the figure, reference numerals 361 to 365 denote modulation signals GY1 to GY3 from the left / right selection block 285, a modulation signal BK corresponding to the maximum image density code, and a modulation signal W corresponding to the zero image density code, respectively. And a selection code b (specifically, b (8K), b (GY3), b (GY2), b (GY1), b
(W)) is an AND gate input to each of the other input terminals, and 366 is an OR gate for inputting the output from each AND gate, and only the AND gate corresponding to the high-level selection code is opened to open the AND gate. The modulated signal that has passed through the gate is output from the OR gate 366 as an image density signal SD (corresponding to the sub-color image density signal SDs).

In the multi-level modulation circuit 275 of the second ROS controller 158, unlike the first ROS controller 157, since the non-exposed portion is an image portion, the image density signal SD is, for example,
As indicated by a virtual line in FIG. 35, the output of the OR gate 366 is inverted by the inverter 367.

(5-B-6) Operation of Multi-Level Modulation Circuit The operation of the multi-level modulation circuit 265 of the first ROS controller 157 will be described with reference to the timing charts shown in FIGS. 36 and 37.

In FIG. 32, when a V clock signal VCK as a reference clock passes through a frequency divider 301, a V clock signal divided by a half is converted into a pulse signal (VC
(Equivalent to K / 2) and the temperature stable chip 304
The output from TP1 is delayed by a predetermined delay amount (DELAY0 in this embodiment).

On the other hand, the pulse signal VCK / 2 is
Output tap T of the first delay line 302
From P2, TP3, TP4, a predetermined delay amount (DELAY0 in this embodiment)
, Which are delayed by DELAY1, DELAY2, and DELAY3). Also, the second delay line
First delay line from 303 output taps TP3, TP4, TP5
A predetermined delay amount obtained by adding a delay amount between each input tap of the second delay line 303 and a delay amount between the input tap IN and the output tap TP5 of 302 (DELAY0 and DELAY0 respectively in this embodiment)
Pulse signals delayed by 4, DELAY5 and DELAY6).

In this case, the EOR gates 312 to 314 output left modulation signals LGY1 to LGY3 having pulse widths corresponding to the DELAY1 to DELAY3. On the other hand, from the AND gates 315 to 317, D
The right modulation signals RGY3, RGY2, RGY1 having a pulse width (corresponding to DELAY3 to DELAY1) obtained by subtracting ELAY4 to DELAY6 are output.

Here, it is assumed that the mode select signal MS indicates a character mode (in this embodiment, character mode: mode select signal MS = 0, photograph mode: mode select signal MS = 1).

At this time, as shown in FIG. 37 (a), the left / right switching signal LRS from the left / right switching signal generator 286 is always "1", and the left modulation signals LGY1 to LGY3 are directly used as the modulation signals GY1 to GY3.
It is output as Y3 and input to selector 287. Then, the selector 287 generates an image density signal SD pixel by pixel in accordance with the selection code from the decoder 283, sends it to the laser driver 159, and drives the first laser 141.

In such a driving operation process, the first laser 14
As shown in FIG. 38 (a), the lighting operation of 1 is a pattern (so-called sawtooth wave pattern) in which each pixel is always lit sequentially from the left side, so that one pixel forms one line, As a result, the resolution is increased, and fine lines such as characters can be satisfactorily reproduced.

On the other hand, assuming that the mode select signal MS indicates the photograph mode, the left / right switching signal LRS from the left / right switching signal generator 286 indicates “1” and “0” as shown in FIG. The output is alternately performed in each cycle of the V clock signal VCK (each pixel P unit), and the left modulation signals LGY1 to LGY3 are output.
And right modulation signals RGY1 to RGY3 are alternately selected as modulation signals GY1 to GY3 for each pixel P and input to the selector 287. Then, the selector 287 generates an image density signal SD pixel by pixel in accordance with the selection code from the decoder 283, sends it to the laser driver 159, and drives the first laser 141. In the multi-level modulation circuit 265 according to this embodiment, the right modulation signals RGY1 and RGY2 are generated only for every two pixels, but in the photo mode, the left modulation signal LGY1 is generated.
Also, since it is used alternately with LGY3, no particular inconvenience occurs.

In such a driving operation process, the first laser 14
The lighting operation 1 is a pattern (so-called triangular wave pattern) in which one of two adjacent pixels P is sequentially lit from the left side and the other is sequentially lit from the right side, as shown in FIG. 38 (b). As a result, a line is formed by the two pixels P, and the resolution is lower than that of the sawtooth wave pattern, but the gradation expression is improved, and a halftone image such as a photograph is reproduced well. Is done.

The multi-level modulation circuit 275 of the second ROS controller 158 operates in substantially the same manner as that of the first ROS controller 157.

In such multi-level modulation circuits 265 and 275, the respective DELAY1 to DELAY3 of the left and right gray generators 284 are set as follows.

Generally, the relationship between the density gradation number N of the input image data DT and the recording image density J is obtained as a non-linear development characteristic curve Y as shown by a solid line in FIG.

Under these circumstances, as shown by the imaginary line in FIG. 39, if the relationship between the image density code SC and the recorded image density is corrected to a linear development characteristic curve Y ', the image density code SC The density difference of the recorded image density J with respect to (0) to SC (4) can be set at substantially equal intervals,
It is considered that the gradation reproducibility of the recorded image can be improved accordingly.

From this point of view, the image density codes SC (1), SC (2), SC (3) on the corrected development characteristic curve Y '
By examining the recorded image density corresponding to, it is understood that the density corresponds to Y1, Y2, Y3 on the actual development characteristic curve Y. Therefore, the image density codes SC (1), SC
(2) When the pulse width of the image density signal SD corresponding to SC (3) is modulated, the recording image density corresponding to Y1, Y2, Y3 of the development characteristic curve Y may be obtained.

Therefore, it is necessary to modulate the pulse width of the image density signal SD with the ratio α of the density gradation number of the input image data corresponding to Y1 to Y3 of the development characteristic curve Y to the maximum density gradation number. The DELAY1 to DELAY3 are set according to the ratio α.

Further, in this embodiment, the frequency divider 301 is
As shown in the figure, the V clock signal VCK is frequency-divided by 1/2 to generate a pulse signal VCK / 2 over the entire range of one pixel P. Therefore, as in the above embodiment, each of the delay lines 302, 30
EOR gates 312 to 314 when extracting a predetermined delay amount from 3.
Thus, a simple circuit configuration using AND gates 315 to 317 is obtained.

More specifically, for example, as shown in FIG.
If the clock signal VCK itself is used as a modulation reference pulse signal, for example, when a pulse signal delayed by a predetermined DELAY from the first delay line 302 and a modulation reference pulse signal are input to an EOR gate, one pixel P is output to the EOR output. In addition, a pulse signal indicated by a two-dot chain line is also generated in addition to the signal indicated by the solid line in the range, and it is impossible to extract only the pulse signal corresponding to the DELAY. In this case, the EOR gate shown in the embodiment is used. It is necessary to take out a pulse signal corresponding to the above DELAY with a logic circuit configuration other than the above. The same applies to the case where a predetermined delay is taken out from the second delay line 303.

Further, in this embodiment, the first delay line 302
The reason why the temperature stable chip 304 having the same configuration as that described above is used is as follows.

For example, as shown in FIG. 41, when the modulation reference pulse signal VCK / 2 based on the V clock signal VCK passes through the first delay line 302, for example, it changes from a state shown by a solid line to a virtual line Since the temperature stabilization chip 304 causes a temperature change similar to that of the first delay line 302 even if the state changes to
K / 2 itself changes from the state shown by the solid line to the state shown by the imaginary line when passing through the temperature stabilizing chip 304, with substantially the same amount of displacement δ. Therefore, even if the output pulse signal fluctuates due to the temperature change of the delay line 302, the modulation reference pulse signal VCK / 2 and the delay line 302
The output pulse signal fluctuates while maintaining the relative positional relationship with the output pulse signal, and the output pulse width of the EOR gate to which both are input is kept constant without being affected by the temperature change. Since the modulation reference pulse signal VCK / 2 and the output pulse signal of the second delay line 303 also fluctuate while maintaining the relative positional relationship, the output pulse width of the AND gate to which both are input is also changed. It is kept constant without being affected by temperature changes.

Further, in this embodiment, since the CMOS gates 305 to 311 are used as the waveform shaping means, the fluctuation of the threshold position due to the temperature change is small. For this reason, as shown in FIG. 42, the threshold position (indicated by a dashed line in FIG. 42) may fluctuate, for example, when shaping the rising and falling portions of the output pulse signal of the delay line. Therefore, the pulse width of the output signal of the CMOS gate is kept stable.

(5-B-7) Modification In this embodiment, the delay amounts of the delay elements 321 to 322 of the delay lines 302 and 303 are appropriately set in advance. For example, as shown in FIG. Lines 371 to 373, for example, a delay line 371 having a uniform delay amount of each output tap O1 to O5 of 10 nsec. And a delay line 372, 373 having a uniform delay amount of each output tap O1 to O3 of 15 nsec. As a result, the delay amount of the taps L1 to L8 is set to 10, 15, 20, 25 ... 45 (nse
c.) It becomes possible to finely adjust the drawer tap
By appropriately selecting L1 to L8, a desired delay amount can be obtained.

In this embodiment, the left and right gray generators 284 described above are used to unequally divide the pulse width of the image density signal SD.
However, even when the pulse width of the image density signal SD is equally divided, the present invention can be applied by setting the delay amounts of the delay lines 302 and 303 equal.

IV. Operation of Apparatus Next, the operation of the laser printer according to this embodiment will be described.

In FIG. 15, density data D of input image data is divided into two sets of image density data Ds and D for sub-color and main color by a data distribution circuit 150 according to a color flag CF.
m, and are subjected to density conversion by the two TRCs 151 and 152, respectively, and then input to the two screen generators 153 and 154.

Then, each of the screen generators 153 and 154 outputs the input image density data Ds and Dm in a different threshold pattern (A sequence pattern, B sequence pattern) for each adjacent pixel.
Of the image density codes SCs and SCm corresponding to. The image density codes SCs and SCm are set corresponding to the number of sub-pixels PS when one pixel P is divided into four as shown in FIGS. 44 (a) and 44 (b).

After this, the image density code SCs for the sub-color is
The image density code SCm for the main color is input to the multi-level modulation circuit 265 of the first ROS controller 157 via 55.
The second ROS controller 158 via the gap memory 156
Is input to the multi-level modulation circuit 275.

Assuming now that the character mode is selected, the image density codes SCs (0) to SCs (4) for the sub-color are set to the 44th.
As shown in FIG. 3A, the image density signals SDs (0) (corresponding to 0), SDs (1) (corresponding to DELAY1), SDs (2) (DELAY2
), SDs (3) (corresponding to DELAY3), and SDs (4) (maximum pulse width). At this time, FIG.
Assuming that the image density signals SDs for the pixels Pi to Pi + 4 are SDs (0) to SDs (4), respectively, the first laser 141 corresponds to the respective image density signals SDs with respect to the photoconductor 120. Beam irradiation with a pulse width is performed to form latent images Zi + 1 to Zi + 4 in which the beam irradiation unit becomes an image unit. Each of the latent images Z is reversely developed with the red toner of the first developing device 123, and a first toner image T (specifically, Ti or Ti + 4) is formed on the photoconductor 120.

On the other hand, as shown in FIG. 44 (b), the image density signals SCm (0) to SCm (4) for the main color are image density signals SDm (0) (corresponding to the maximum pulse width) and SDm (1). (Equivalent to the pulse width obtained by subtracting DELAY1 from the maximum pulse width), SDm
(2) (equivalent to the pulse width obtained by subtracting DELAY2 from the maximum pulse width), SDm (3) (equivalent to the pulse width obtained by subtracting DELAY3 from the maximum pulse width), and SDm (4) (equivalent to 0) . At this time, if the image density signals SDm for the pixels Pi to Pi + 4 are SDm (0) to SDm (4), respectively, as shown in FIG.
120 is irradiated with a beam having a pulse width corresponding to each of the image density signals SDm, and a latent image Zi + in which a non-exposed portion becomes an image portion.
1 to Zi + 4 are formed. Each of the latent images Z is a second developing device.
The second toner image T (specifically, Ti to Ti + 4) is formed on the photoconductor 120 by regular development with the black toner 124.

Note that when the photograph mode is selected, as described above, the only difference is that the growth direction in the pixel P of the image density signal SD is alternately left and right for each adjacent pixel. Image forming operation is performed.

In such an image recording operation process, the image density signals SD (0) to SD (
The relationship between (4) and the recorded image density was examined and found to be
As shown by the phantom line in FIG. 46, it was confirmed that the image had extremely linear image reproduction characteristics.

Also, the above-described threshold pattern setting circuit
In the photo mode, images were recorded in the same manner as in the example and the comparative example with the threshold value of 190 fixed, as shown in FIGS. 47 (a) to 47 (d). It was confirmed that the eigenpattern (texture) by the error diffusion method was less noticeable in the example than in the comparative example.

FIG. 47 (a) shows an example of image recording output for an input pixel in which the input density level continuously changes from 0 to 128 in the embodiment, and FIG. 47 (b) shows the image recording output of FIG. In the example, an area where the input density level is about 5 to 70 is enlarged, white pixels are output in white, and gray pixels are output in black. FIG.
An example of an image recording output for an input pixel that continuously changes up to 128 is shown, and FIG. 11D is an enlarged image of the image recording output example of FIG. , White pixels are output in white, and gray pixels are output in black.

Embodiment 2 In this embodiment, the present invention is applied to a one-pass two-color type two-color copying machine as in Embodiment 1, and the basic configuration of the image processing unit 20 is the same as that of Embodiment 1. However, a laser printer 110 as an image output unit is different from that of the first embodiment.

In this embodiment, the laser printer 110 is
As shown in FIG. 8, it is composed of one look-up table or arithmetic circuit that converts and outputs the number of density gradations of the density data D using the density data D and the color flag CF from the image processing unit 20 as address signals. TRC381 and this TRC381
And a screen generator 382 for generating an image density code SC on a line screen employing an error diffusion method, and a color flag C from the screen generator 382 as an input signal.
A data distribution circuit 383 for distributing the image density code SCs for sub-color and the image density code SCm for main color according to F, and a color flag for the data distribution circuit 383
A buffer 384 for adjusting the CF transfer timing,
One image density code S from the data distribution circuit 383
First ROS controller that captures Cs via FIFO 155 and generates an image density signal SDs that is a drive signal for the first laser 141
157, and a second ROS controller 158 that takes in the other image density code SCm from the data distribution circuit 383 via the gap memory 156 and generates an image density signal SDm that is a drive signal of the second laser 142. I have.

In this embodiment, the TRC 381 implements the first TRC 151 and the second TRC 152 in the first embodiment with one look-up table, and the data distribution circuit 383 is the data distribution circuit 150 in the first embodiment. It has the same configuration as the above.

The other components similar to those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and the detailed description thereof will be omitted.

Next, the operation of the one-pass two-color type two-color copying machine according to this embodiment will be described.

First, when the density data D and the color flag CF output from the image processing unit 20 are input to the TRC 381, the TRC 381
Converts the density data D into an appropriate gradation level according to the color flag CF and outputs the converted data.

Next, the converted density data D is converted into an image density code SC by a screen generator 382, and the image density code SC is converted by a data distribution circuit 383 into a color flag CF.
After being distributed to the sub-image density code SCs and the main image density data SCm according to the first ROS controller 15 respectively.
7. Transferred to the second ROS controller 158 side.

Thereafter, through the same steps as in the first embodiment, the recording sheet 127
A two-color image is formed thereon.

In such an operation process, in the first embodiment,
Since the image density data D allocated to the two systems is coded in accordance with the color flag CF, when coding, a sub-color pixel appears in the main color area, or conversely. , There is a possibility that a main color pixel appears in the sub color area. In this embodiment, after coding the image density data D,
Since the colors are assigned to the main color and the sub color, there is no possibility that the main color area and the sub color area overlap.

Further, in this embodiment, the functions substantially similar to those of the first embodiment can be realized only by equipping the TRC 381 and the screen generator 382 together, so that the apparatus configuration is simplified as compared with the first embodiment. Can be achieved.

Embodiment 3 I. Basic Configuration In this embodiment, the present invention is applied to a two-color copying machine of a one-pass two-color system as in Embodiment 1, and the basic configuration is the same as that of Embodiment 1. Although it has a processing unit 20, a laser printer 110 as an image output unit is different from that of the first embodiment.

In this embodiment, the laser printer 110 is
As shown in FIG. 9, the density data D and the color flag CF from the image processing unit 20 are used as address signals to convert and output the number of density gradations of the density data D, and the corresponding color flag CF is left as it is. The TRC 401 (corresponding to the TRC 381 of the second embodiment) including one look-up table and an arithmetic circuit output in the state, the converted density data D and the color flag CF from the TRC 401 are used as input signals, and an error diffusion method is adopted. A screen generator 402 that generates the image density code SC on the line screen and outputs the corresponding color flag CF as it is, and converts the image density code SC from the screen generator 402 into a sub color according to the color flag CF. Data distribution circuit 403 (the data of the second embodiment) which distributes the data to the two systems of the image density code SCs for main use and the image density code SCm for main color. Divided circuit 383
) And one of the image density codes SCs from the data distribution circuit 403 via the FIFO 155,
The first RO that generates the image density signal SDs, which is the drive signal for 141
The S controller 157 and the other image density code SCm from the data distribution circuit 403 are fetched via the gap memory 156, and the image density signal S
A second ROS controller 158 for generating Dm.

The other components similar to those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and the detailed description thereof will be omitted.

II. Screen Generator (1) Basic Configuration FIG. 50 is a block diagram showing the basic configuration of the screen generator according to this embodiment.

In the figure, reference numeral 411 denotes a buffer for temporarily storing density data D. The density data D from this buffer 411 is input to a comparison circuit 413 via an error diffusion circuit 412. On the other hand, reference numeral 414 denotes a buffer for temporarily storing the color flag CF, and the color flag CF from the buffer 414 is input to the reference color flag extraction circuit 415, and the reference color flag extraction circuit 415 All the color flags CF that need to be referred to at 412 are extracted and sent to the error diffusion circuit 412, while the color flag of the target pixel (hereinafter referred to as the target color flag) is sent to the subsequent latch circuit 416. Then, the threshold pattern THP set by the threshold pattern setting circuit 417 having the same configuration as that of the first embodiment is input to the error diffusion circuit 412 and the comparison circuit 413, and the error diffusion circuit 412 and the comparison circuit 413 After the predetermined error diffusion process and the comparison process are performed respectively, the output from the comparison circuit 413 is input to the density code generator 418,
A predetermined conversion is performed to generate an image density code SC. Then, the density code generator 418
, And the color flag CF from the latch circuit 416 are output as a pair in synchronization with each pixel of interest.

(2) Error diffusion circuit (2-A) algorithm FIG. 51 (a) shows an algorithm of the error diffusion circuit 412 used in this embodiment.

In the figure, the i-th pixel Pj (i) of the j-th line is set as a target pixel, and its density data is set as X, while the i−1, i, i + 1-th pixels Pj−1 (i) of the j−1-th line are used. -1), Pj
-1 (i) and Pj-1 (i + 1) are represented by A, B, and C, respectively.
Assuming that D is the difference data of the pixel Pj (i−1) immediately before the pixel of interest Pj (i), the corrected density data X ′ of the pixel of interest Pj (i) is expressed by the following equations (12) and (13). It is calculated. Note that Δ
X is difference correction data, g1 to g4 are correction coefficients for weighting according to the degree of influence of the difference data of each pixel, and have a predetermined level of weighting only for difference data of the same system as the pixel of interest. The difference data of a different system from the target pixel is held at the 0 level.

ΔX = g1A + g2B + g3C + g4D where Σgi (i = 1 to 4) = 1 (when gi ≠ 0) X ′ = X + ΔX (13) In this embodiment, g1 = 0.2, g2 = 0.5, g3 = 0.2,
g4 = 0.1 is set.

Now, as shown in FIG. 51 (a), the pixel of interest Pj (i) is main color data (black in this embodiment), and peripheral pixels of the same system as the pixel of interest Pj (i) are Pj-i ( i-
Assuming that 1), Pi-1 (i), Pj (i-1),
The difference correction data ΔX is g1A + g2B + g4D, and the corrected density data X ′ is X + g1A + g2B + g4D.

That is, in this embodiment, only the difference data of the same system as the target pixel is to be corrected, and the difference data of the different system from the target pixel is ignored. In other words, the density data is different for the target pixel and the different system pixel. It is treated as "0".

(2-B) Example of Realized Circuit FIG. 51 (b) embodies the error diffusion circuit 412 according to the algorithm as described above.

In the figure, reference numeral 421 denotes an adder.
The 8-bit density data D from the buffer 411 is input to one of the input terminals 21. Reference numeral 422 denotes a latch circuit that temporarily stores output data from the adder 421 and then outputs the data. The output data of the latch circuit 422 is input to one input terminal of the adder 423. Further, reference numeral 424 denotes a latch circuit which temporarily stores the output data of the adder 423 and then outputs the data.
The output data of No. 4 is sent to the comparison circuit 413.

Reference numeral 426 denotes density data D from the latch circuit 424, threshold data TH and address data ADT from the threshold pattern setting circuit 417 (comparison circuit 413).
(See II 4-D in Example 1) as input data to generate difference values for generating difference data (corresponding to A, B, and C in FIG. 51 (a)) in the pixel one line before. A difference data ΔD from the difference value generation circuit 426.
T and the reference color flag CF from the reference color flag extraction circuit 415 are both stored in the FIFO 427 for one line, and then the difference data for correction and the color flag CF
Is taken into the digital filter 428.

The digital filter 428 performs a predetermined operation using the difference data A, B, and C of the correction pixel in the same system as the pixel of interest, and outputs data of g1A + g2B + g3C. The signal is input to the other input terminal of the adder 421.

In this embodiment, the digital filter 428
Are three-stage latch circuits 431 to 433 for sequentially latching the difference data ΔDT and the color flag CF for each pixel, and the difference data ΔD which is the output data of the first-stage latch circuit 431.
A coefficient multiplier 434 for multiplying T (corresponding to A in FIG. 51 (a)) by a correction coefficient g1, and a second-stage latch circuit 4
The output data of the coefficient multiplier 435 for performing an operation of multiplying the difference data ΔDT (corresponding to B in FIG. 51 (a)), which is the output data of 32, by the correction coefficient g2, and the third-stage latch circuit 433. When the coefficient multiplier 436 performs an operation of multiplying the difference data ΔDT (corresponding to C in FIG. 51 (a)) by the correction coefficient g3, and the color flag CF and the target color flag CF of the input difference data do not match. An EOR gate 4 that outputs a flag information signal FS for inhibiting operation to each of the coefficient multipliers 434 to 436
37 to 439, and an adder 440 for adding output data of the coefficient multipliers 434 to 436.

Such a digital filter 428 causes the three-stage latch circuits 431 to 433 to latch the three-pixel difference data A, B, and C and the respective color flags CF of the immediately preceding line, and the difference data of the same system as the target pixel. Coefficient multiplier 434 only for
Each difference data A, B, C and each correction coefficient at 436
After multiplying by g1, g2, and g3, they are added by an adder 340, and g1A + g2B + g3C is output (provided that the correction coefficient for difference data of the pixel of interest and a different system is substantially 0).

Furthermore, reference numeral 411 is a lookup table,
The difference data ΔDT (D in FIG. 51 (a)) is used as an address signal with the density data D, the threshold data TH, and the flag information signal FS indicating the relationship between the target color flag CF and the color flag CF forming a pair of the input density data D. ) Is multiplied by a correction coefficient g4 to read out the difference correction data g4D together with the polarity data. In this case, the flag information signal FS includes the target color flag CF and the input density data D.
Is generated by inputting the color flag CF and the color flag CF, which are paired with each other, to the EOR gate 442.
Thus, while g4D is output together with the polarity from the above-mentioned lookup table 441, when both do not match, it becomes "1" and the lookup table 441 always outputs "0".

Therefore, according to this embodiment, if the error diffusion process for the pixel pattern shown in FIG. 51A is taken as an example, the density data X of the target pixel and the output g1A + g2B (g3C = 0) from the digital filter 428 are obtained. At the stage where this data is input to one input terminal of the adder 423 via the latch circuit 422, the second difference correction data g4D is added, and the corrected density of the target pixel is added to the latch circuit 424. The data X '= X + g1A + g2B + g4D is latched, and the corrected data X' is sent to the comparison circuit 413 at the subsequent stage.

III. Features of the Apparatus According to the two-color copying machine of the one-pass two-color system according to the present embodiment, the same operation and effect as those of the second embodiment can be obtained.
In the second embodiment, since the image density data D is coded without distinguishing the main color pixel and the sub color pixel, the coding is performed in consideration of the image density of another system. On the other hand, in this embodiment, the image density data D can be coded in a state where the main color pixels and the sub color pixels are distinguished from each other. Thus, it is possible to accurately code only the image density data of the corresponding system.

Embodiment 4 4 The basic configuration of a two-color color copying machine according to this embodiment is substantially the same as that of Embodiment 1, but the first TRC 151 and the second TRC 152.
Has a different configuration. Note that, for convenience of description of this embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as in the first embodiment.

In this embodiment, as shown in FIG. 52, the first TRC 151 is used for a character to be subjected to density gradation conversion on the assumption that the image data DT (corresponding to the sub-color density data Ds) is a character image. Conversion table 451 and the above image data DT
A photo conversion table 452 in which density gradation conversion is performed on the assumption that is a photographic image, and an output terminal A or B is selected according to a mode select signal (character mode or photo mode selection signal) MS; Mode select signal MC
Is in the character mode, the input image data DT is transferred to the character conversion table 451 through the output terminal A. When the mode select signal MS is in the photograph mode, the input image data DT is transmitted to the photograph conversion table 452 through the output terminal B. And a selection circuit 453 for transferring the input image data DT.

In this embodiment, the data stored in the character conversion table 451 and the photo conversion table 452 are set, for example, as shown in FIG. In the figure, the density gradation conversion range of the photo conversion table 452 is set to be narrower than the density gradation conversion range of the character conversion table 451 with respect to the density gradation of the same input image data DT.

Next, a method of setting the density gradation conversion range will be described with reference to the photograph conversion table 452 as an example.

Now, in the first quadrant (I) of FIG. 54, the image reproduction characteristic of the normal first developing unit 123 is shown by a dotted line, and the image reproduction characteristic Yp to be reproduced in the photographic mode is shown by a solid line in the first quadrant (I). Assuming that the density data corresponding to the input image density is given by a curve such as the fourth quadrant (IV) in FIG. 54, if there is no TRC 151, the SG-IOT characteristics (input to the screen generator) The characteristic between the density data and the output image density) must be set as shown by the curve S 'in the second quadrant (II), but the pulse width of the image density signal SD of the multi-level modulation circuit 265 of the first ROS controller 157 is required. Is limited, the curve S 'may not be obtained.

In such a situation, if the data conversion of the first TRC 152 is set as a curve M in the third quadrant (III), the SG-IOT will be changed like a curve S in the second quadrant (II). By setting the characteristics to those that can be easily obtained along the pulse width modulation pattern of the multi-level modulation circuit 265, the desired image reproduction characteristics Yp can be obtained.

The method of setting the density gradation conversion range in the character conversion table 451 may be obtained by replacing the target density reproduction curve Yp in the first quadrant of FIG. 54 with that for characters.

On the other hand, the second TRC 152 has basically the same configuration as the first TRC 151 except that the specific storage data of each conversion table is different.

Therefore, according to the two-color color copying machine of this embodiment, when the photo mode is selected, the photo conversion table 452 is selected in each of the TRCs 151 and 152, and the input image data D
T is transferred to the respective screen generators 153 and 154 via the photo conversion table 452. Thereafter, as in the first embodiment, the sub-color image density code SCs and the main-color image density code SCm from the respective screen generators 153 and 154 are transmitted by the first ROS controller 157 and the second ROS controller 1.
After being converted into desired image density signals SDs and SDm through 58, the first laser 1 based on these image density signals SDs and SDm, respectively.
41, The output of the second laser 142 is pulse width modulated.

Now, assuming that the image of Example 1 is a comparative example and a reproduced image is selected when the photograph mode is selected, as shown in FIGS. 55 (a) and (b), the image of this example is It can be understood that the object has less collapse in the high density area of the photographic document and has a smooth density gradation.

If a character code is selected, the first and second TR
In C151 and 152, the character conversion table 451 (corresponding to that in the first embodiment) is selected, so that the same operation as in the first embodiment is performed, and the same character image quality as in the first embodiment is obtained.

Embodiment 5 The basic configuration of a two-color copying machine according to this embodiment is substantially the same as that of Embodiment 1, except that the configurations of the multi-level modulation circuits 265 and 275 of the first ROS controller 157 and the second ROS controller 158 are different. It has become. Note that, for convenience of description of this embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as in the first embodiment.

In this embodiment, the multi-level modulation circuit 265 of the first ROS controller 157 is configured as shown in FIG.

In the figure, reference numeral 461 denotes an interface for taking in the image density code SC (corresponding to the sub-color image density code SCs) into the multi-level modulation circuit 265, and the image density code SC taken in the interface 461. Are latched by the latch circuit 462 in synchronization with the V clock signal VCK. The image density code SC from the latch circuit 462 is selected by a decoder 463 comprising a P-ROM by a selection code b (specifically, b (BK), b (GY3), b (GY2), b (GY
1), b (W)). In this case, the contents of the decoder 463 are set to be the same as those in the first embodiment.

On the other hand, reference numeral 464 denotes a character gray generator for generating a modulation signal having a pulse width corresponding to a halftone image density code in a character image by utilizing a phase shift of a pulse signal based on the V clock signal VCK. Signal V
A photo gray generator for generating a modulation signal having a pulse width corresponding to a halftone image density code in a photo image by utilizing a phase shift of a pulse signal based on CK, and 466 generates a V clock signal VCK in response to a mode select signal MS. When the mode select signal MS is in the character mode, the V clock signal VCK is transferred to the character gray generator 464 through the output terminal A when the mode select signal MS is in the character mode. Is a selection circuit for transferring the V clock signal VCK to the photographic gray generator 465 through the output terminal B.

Then, the modulation signals GY1 to GY1 from the character gray generator 464 or the photo gray generator 465 are output.
GY3, the modulation signal BK corresponding to the maximum image density code and the modulation signal W corresponding to the zero image density code are selected by the selector 467.
The selector 467 has the same configuration as that of the first embodiment, and selects one of the selection signals according to the selection code b of the decoder 463. The signal is generated as an image density signal SD (corresponding to the sub-color image density signal SDs).

FIG. 57 shows the basic configuration of each gray generator 464, 465 used in this embodiment.

In the figure, reference numeral 471 denotes a frequency divider that divides the V clock signal by half, 472 denotes a delay line that delays the pulse signal from the frequency divider 471 by a plurality of predetermined delay times, and 473 denotes a delay line. A temperature stable chip composed of a delay line having the same configuration as the delay line 472, 474 to 477 are CMOS gates for waveform shaping, and 478 to 480 are EOR gates.

In this embodiment, the delay line 47
The basic configuration of the second embodiment is the same as that employed in the first embodiment. The three output taps TP2 to TP4 of the delay line 472 are used to generate halftone image density codes SC (1) to SC (1).
Modulated signals having three pulse widths corresponding to C (3) are generated. Note that TP1 is employed as an output tap of the temperature stabilizing chip 473.

In this embodiment, the delay amount between TP2 and TP1 of the delay line 472 of the character gray generator 464 is set to DELAY1 to DELAY3, and the delay amount of the TP2 to TP4 of the delay line 472 of the photo gray generator 465 is set to DELAY1 to DELAY3.
Assuming that the delay amount between TP1 and DELAY1 'or DELAY3', each delay amount satisfies the relationship of DELAY1> DELAY1 'DELAY2>DELAY2'DELAY3> DELAY3 ', and furthermore, character image reproduction characteristics and photographic image reproduction The characteristic is preset to such a value as to obtain a curve of Yc and Yp shown in FIG. 59.

In this embodiment, the delay amounts are set as follows, for example.

DELAY1 = 15 DELAY1 '= 10 DELAY2 = 25 DELAY2' = 20 DELAY3 = 35 DELAY3 '= 30 However, the unit is nsec., And the maximum pulse signal width is 55nse.
c.

Next, the operation of the two-color copying machine according to this embodiment, particularly on the image output unit side, will be described.

Now, focusing on the image recording of the first color, the image density code SC from the first screen generator 153 is the FIF
It is assumed that the input is made to the first ROS controller 157 via O155.

Here, assuming that the photo mode is selected, the multi-level modulation circuit 265 selects the photo gray generator 465. Then, in the photo gray generator 465, the V clock signal VCK is used as the reference clock by the frequency divider 471.
, A V clock signal divided by 1/2 is generated as a pulse signal (corresponding to VCK / 2) based on the reference clock.

When the pulse signal is input to the delay line 472, the pulse signal is output from the taps TP2 to TP4 of the delay line 472 with a predetermined delay. On the other hand, the pulse signal passing through the temperature stabilizing chip 473 and the pulse signal from each tap TP2 to TP4 of the delay line 473 are respectively passed through the CMOS gates 474 to 477 and then the EOR gate 4
78 to 480 are entered. Then, the modulation signals GY1, GY2, GY3 from each of the EOR gates 478 to 480 are respectively set to the above-mentioned DE.
The signal is output as a signal having a pulse width corresponding to LAY1 ′ to DELAY3 ′ and transferred to the selector 467.

On the other hand, as shown in FIG. 58, the image density code SC, specifically, one of SC (0) to SC (4) is a decoder.
It is converted into the selection code b in the 463 part, and this is
, A modulated signal corresponding to the selection code b
One of BK, GY1, GY2, GY3, W is selected and the image density signal
SD is output. At this time, the pulse widths of the image density signals SD (1) to SD (3) correspond to DELAY1 'to DELAY3' as shown by the dashed line in FIG.

When the character mode is selected, the character gray generator 464 is selected and the image density code SC is selected.
Image density signal SD (1) corresponding to (1) to SC (3)
Or the pulse width of SD (3) corresponds to DELAY1 to DELAY3.

When the output pulse width of the first laser 141 is modulated based on the image density signal SD generated in this way, as shown in FIG. 59, the image reproduction characteristic Yp corresponding to the photographic mode or the image corresponding to the character mode is obtained. The reproduction characteristic Yc is obtained. That is, the image reproduction characteristic Yp corresponding to the photograph mode has a lower output image density level than the image reproduction characteristic Yc corresponding to the character mode.

Here, the type without the photo gray generator 465, that is, the type in which the photo original is reproduced by the character gray generator 464 was used as a comparative example, and the reproduction characteristics of the photo original were examined. As shown in (b), it can be understood that the example of the present invention has less collapse of the high density area of the photographic document and has a smoother density gradation than the comparative example.

Embodiment 6 The basic configuration of a two-color copying machine according to this embodiment is substantially the same as that of Embodiment 5, but the configuration of the first and second screen generators 153 and 154 is Embodiment 4 (corresponding to Embodiment 1).
It is different.

First, the first and second screen generators 153, 154
Will be described.

Now, taking as an example a case where image data of 256 gradations is converted into a 2-bit image density code SC, as shown in FIG. 61 (a), three threshold data TH1 to TH3 (for example, 4
3, 128, 213), white area W (gradation number less than 43), gray 1 area G1 (gradation number 43 or more and less than 128), gray 2 area G2
(Gradation number 128 or more and less than 213), black area BK (gradation number 213 or more), and image density code SC corresponding to each area
(0) = "00", SC (1) = "01", SC (2) = "10", SC
(3) Convert to "11".

On the other hand, in each pixel, the input image data and the reference data MD of the area including the input image data (W: 0, G1: 255 × (1/3) = 85, G2: 255 × (2 / 3) = 170, B
K = 255) is defined as error data e. For example, when the density gradation number of the input image data is “160”, the error data e = 160−170 = −10 because the input image data is included in the gray 2 area G2.

Next, as shown in FIG. 61 (b), the error data e _mn generated at each of the pixels is converted into a matrix M of, for example, 4 × 4 pixels.
Integrated in a range of X, as shown by the following equation (14), it takes the summation to determine the matrix error data e _T.

e _T = Σe _mn (m, n = 1 to 4) (14) Thereafter, based on the value of the matrix error data e _T calculated by the above equation (14), the lighting conditions under the following conditions, in other words,
The image density code SC of each pixel is corrected.

(1) Correction condition a; -43 <e _T <43: No correction (2) Correction condition b; However, the pixels whose gradations are to be changed are selected in descending order of the + side error.

(3) Correction condition c; However, the pixels for which the gradation is to be changed are selected in descending order of the negative error.

Now, assuming that each image density code in the 4 × 4 pixel matrix MX is as shown in FIG. 61 (c),
Matrix error data e _T in the pixel matrix MX
There are 200, moreover, in the 61 view (b), + the ones of the side errors large is assumed to be error data e _22, e ₃₂ ... order, as indicated by hatching in the 61 view (d), image density code of the pixel corresponding to the error data e _22, e ₃₂ is up by one gradation.

Next, FIG. 62 shows a specific circuit for realizing the above algorithm.

In the figure, reference numeral 491 denotes an error / lighting condition calculation circuit for calculating error data e and lighting conditions (image density code SC) of each pixel, and 492 denotes four lines located at every fourth line (for example, i + 1 to i + 1 in FIG. 63). i + 4,1 + 9 to i + 1
An A-sequence line memory for reading error data e and image density code SC for two lines) and sequentially reading error data e and image density code SC for a 4 × 4 pixel matrix MX (see FIG. 63). Error data e and image density code SC for four lines (i + 5 to i + 7 lines in FIG. 63) other than the lines stored in the A-series line memory 492
B-sequence line memory for sequentially reading error data e and image density code SC for the size of a 4 × 4 pixel matrix MX, and 494 stores the error data e / image density code SC from the error / lighting condition calculation circuit 491. A line memory 49
2, a selector for distributing to any of the B-series line memories 493; 495, a timing generation circuit for controlling the write / read timing of the A-series line memory 492 and the B-series line memory 493; 496, the matrix error data e _T A correction condition determining circuit 497 that calculates and corrects the image density code SC according to the correction conditions a to c, 497 transmits data from the A-series line memory 492 or the B-series line memory 493 to the correction condition determining circuit 496 or the ROS interface. It is a selector for selectively transferring.

In the screen generators 153 and 154, first, the error data e / image density code SC of the pixel in the A-series line is calculated by the error / lighting condition calculation circuit 491, and is read into the A-series line memory 492.

Next, the error data e / image density code SC for each pixel matrix MX is transferred from the A-series line memory 492 to the correction condition determination circuit 496, and the correction condition determination circuit 496 corrects the image density code SC. The result is returned to the A-series line memory 492 again.

During this time, the error data e / image density code SC of the pixels in the B-series line are calculated by the error / lighting condition calculation circuit 491 and read into the B-series line memory 492.

Then, the corrected processing result is read from the A-series line memory 492, and is sequentially transferred to the ROS interface side line by line.

During this time, the pixel matrix M is
The X-unit error data e / image density code SC is transferred to the correction condition determination circuit 496, and the processing result is returned to the B-sequence line memory 492 again with the correction condition determination circuit 496 correcting the image density code SC.

By repeating such an operation thereafter, the image density code SC for the pixels of all lines is generated and transferred to the ROS interface side.

Therefore, in this example, a comparative example using the conventional line screen + error diffusion method was used as a comparative example, and when the reproduced images were compared with each other, the character image was deteriorated in the comparative example. This phenomenon was hardly observed in the embodiment.

[Effect of the Invention] As described above, according to the image recording apparatus of the first aspect, when correcting the input image data, the threshold value of the error diffusion method is switched for each pixel so that a predetermined screen pattern can be formed. Since the superimposition is performed, it is possible to suppress the exposed state of the unique pattern (texture) by the error diffusion method, and it is possible to effectively avoid the deterioration of the halftone image quality due to the texture.

According to the image recording apparatus of the second aspect, the image data of each pixel is generated in a state where the overall correction based on the overall error is performed in the pixel matrix range, and the stitches of the line screen are not directly exposed. In addition, since the generation of the texture by the error diffusion method is avoided, the deterioration of the character image caused by the line screen method can be effectively prevented.

In particular, according to the image recording apparatus of the third aspect, as a pixel to be corrected in the pixel matrix, a pixel having a large initial error is prioritized, so that it is possible to perform correction in descending order of need for correction. Thus, a reproduced image more faithful to the structure of the original image can be obtained, and moreover, moire can be suppressed as compared with a conventional dither matrix method or the like.

[Brief description of the drawings]

1 (a) to 1 (e) are explanatory views schematically showing an image recording apparatus according to a representative embodiment and a reference embodiment of the present invention.
FIG. 3 is a block diagram showing an overall configuration of the first embodiment, FIG. 3 is a block diagram schematically showing an image processing unit of the first embodiment, FIG. 4 is an explanatory diagram showing an overall configuration of a full-color sensor, and FIG.
The figure is an explanatory view showing the cell arrangement of the full-color sensor.
8 are circuit diagrams showing a configuration example of a sensor interface circuit, FIG. 9 is an explanatory diagram showing an example of a cell configuration in pixel units, FIG. 10 is an explanatory diagram showing a configuration example of a color image information generation circuit, FIG. 11 is an explanatory diagram showing a state of a discrimination color in a color space,
FIG. 12 is an explanatory diagram showing the relationship between the distance r from the origin in the color space and the saturation C, FIG. 13 is an explanatory diagram showing the relationship between the angle θ and the hue H in the color space, and FIG. FIG. 15 is an explanatory diagram schematically showing an image output unit, FIG. 16 is a perspective view schematically showing a ROS, FIG. 17 is a first developing device and a second developing device. 18 (a) and 18 (b) are explanatory diagrams showing an image forming process of an image output unit, FIG. 19 is an explanatory diagram showing a configuration example of a data distribution circuit, and FIG. FIG. 21 is a graph showing the characteristics of the first TRC and the second TRC, FIG. 21 is a block diagram showing the basic configuration of the first and second screen generators, and FIG. 22 (a) is an explanation showing the algorithm of the threshold pattern setting circuit FIG. 22, (b) is an explanatory view showing a specific example thereof, and FIG. 23 is a threshold. Block diagram illustrating a configuration example of a turn setting circuit diagram FIG. 24 illustrates an algorithm of the error diffusion circuit, FIG. 25 is 24
FIG. 26 is an explanatory diagram showing a method of calculating the value of the difference data and the polarity thereof, FIG. 26 is a block diagram showing details of the error diffusion circuit, FIG. 27 is a circuit diagram showing details of the difference value generating circuit of FIG. 26, FIG. 28 is a circuit diagram showing details of a digital filter, FIG. 29 is a circuit diagram showing details of a comparison circuit and a density code generator, FIG. 30 is a block diagram showing a basic configuration of first and second ROS controllers, FIG. 31 is a block diagram showing details of the multi-level modulation circuit, FIG. 32 is a circuit diagram showing details of the left and right gray generators in FIG. 31, FIG. 33 is an explanatory diagram showing a configuration example of a delay line, and FIG. Is a circuit diagram showing details of a left / right selection block and a left / right switching signal generator, FIG. 35 is a circuit diagram showing details of a selector, FIG. 36 is a timing chart showing operating states of a left / right gray generator, and FIG. (B) is a left / right selection block and 38 (a) is a timing chart showing the operation state of the left / right switching signal generator.
(B) is a schematic diagram showing an example of a pulse width modulation pattern in the character mode and the photograph mode. FIG. 39 is an explanatory diagram showing a method of setting a delay amount in a delay line of the left and right gray generators. FIG. 41 is an explanatory diagram showing the operation of the temperature stabilizing chips of the left and right gray generators, FIG. 41 is an explanatory diagram showing the operation of the CMOS gates of the left and right gray generators, FIG.
FIGS. 44A and 44B are explanatory diagrams showing modified examples of the delay lines of the left and right gray generators, FIGS. 44A and 44B are explanatory diagrams showing the operation of the image output unit according to the first embodiment up to the ROS controller, and FIGS. (B) is an explanatory view showing an image forming process on the photoreceptor, FIG. 46 is a graph showing the relationship between the image density signal and the recorded image density, and FIGS. 47 (a) and (b) are examples in the embodiment. FIGS. 47 (c) and (d) show the texture state (drawing substitute picture) and its partially enlarged view in the comparative example, and FIG. 48 (c) and (d) show the texture state in the comparative example. Is an explanatory view showing Embodiment 2 of the image recording apparatus according to the present invention, FIG. 49 is an explanatory view showing Embodiment 3 of the image recording apparatus according to the present invention, and FIG. 50 is a block diagram showing a basic configuration of the screen generator FIG. 51 (a) shows an error diffusion circuit. FIG. 51 (b) is a block diagram showing a configuration example of an error diffusion circuit, FIG. 52 is an explanatory diagram showing a TRC of Embodiment 4 of the image recording apparatus according to the present invention, and FIG. FIG. 54 is an explanatory view showing a specific example of the conversion table, FIG. 54 is an explanatory view showing a method of setting the contents of the conversion table, and FIGS. 55 (a) and (b) show the image reproducibility of the embodiment and the comparative example. FIG. 56 is a block diagram showing a multi-level modulation circuit of Embodiment 5 of the image recording apparatus according to the present invention, FIG. 57 is a circuit diagram showing details of each gray generator, and FIG. FIG. 59 is a graph showing image reproduction characteristics, FIGS. 60 (a) and 60 (b) are diagrams showing image reproducibility of the example and the comparative example, and FIGS. 61 (a) to (a). d) is an algorithm used in the screen generator of the sixth embodiment of the image recording apparatus according to the present invention. Explanatory view showing a rhythm, FIG. 62 is a block diagram showing a configuration example of a screen generator 63 is an explanatory diagram showing the sequence A line, B-series line, the concept of the pixel matrix. [Description of Signs] DT: Multi-tone input image data SC: Image density code SD: Image density signal MS: Mode selection signal 1: Beam scanning unit 2: Photoconductor 3: Developing means 4: ... density gradation conversion means 5 ... density code generation means 6 ... multi-level modulation means 7 ... threshold value switching means 8 ... data correction means 9 ... code setting means 11 ... initial density code setting means 12 ... code Error extracting means 13 matrix error determining means 14 code correcting means 15 modulation pattern switching means 16 range varying means 17 pulse width varying means

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-183260 (JP, A) JP-A-62-185465 (JP, A) JP-A-64-67345 (JP, A) 177653 (JP, A) JP-A-61-53874 (JP, A) JP-A-62-278871 (JP, A) JP-A-63-293062 (JP, A) JP-A-1-156070 (JP, A) JP-A-62-198265 (JP, A) JP-A-1-200781 (JP, A) JP-A-62-230163 (JP, A) JP-A-62-181573 (JP, A) JP-A-3-147480 (JP, A) JP-A-3-18177 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60 H04N 1 / 23-1/31

Claims (3)

(57) [Claims] 1. An image recording apparatus which corrects multi-tone input image data by a correction means to which an error diffusion method is applied and performs image recording based on the corrected image data. By dividing the density gradation of the tone input image data by a predetermined threshold, image data corresponding to the divided area is generated,
A threshold value is switched for each pixel to generate image data on which a predetermined screen pattern is superimposed; and a difference between the image data generated by the generation unit and input image data corresponding thereto is distributed to peripheral pixels. An image recording apparatus comprising: an error dispersion unit. 2. An image recording apparatus which corrects multi-gradation input image data by a correction means to which an error diffusion method is applied, and performs image recording based on the corrected image data. Generating means for generating image data corresponding to the divided area by dividing the density gradation of the input image data by a predetermined threshold value; and a difference between the image data generated by the generating means and the corresponding input image data. Error extraction means for extracting pixel by pixel, matrix error determination means for adding the total initial errors in a pixel matrix of a predetermined size composed of a plurality of pixels in each of the vertical and horizontal directions, and using the addition result as matrix error data; An image recording apparatus comprising: an error dispersing unit that disperses an error to a specific pixel in the pixel matrix based on data. 3. The image recording apparatus according to claim 2, wherein the error dispersing means gives priority to a pixel having a large initial error extracted by the initial error extracting means as a correction target pixel order of the pixel matrix. An image recording apparatus characterized by the above-mentioned.