JP3247453B2 - Circuit connection information extraction method from integrated circuit mask pattern - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for extracting circuit connection information from an integrated circuit mask pattern, and more particularly to a method for extracting a mask pattern as digital data and extracting circuit connection information using a computer.

[0002]

2. Description of the Related Art When designing an integrated circuit, first, a circuit diagram is created, and an integrated circuit mask pattern is designed based on the circuit diagram. When examining a circuit represented on the integrated circuit mask pattern (for example, collation with the original circuit diagram), a circuit connection indicating how each circuit element on the mask pattern is connected Information needs to be extracted. The degree of integration of integrated circuits is increasing year by year, and it is very difficult to manually extract such circuit connection information. Therefore, usually, an extraction operation using a computer is performed.

The process of extracting circuit connection information using a computer is performed by the following process. First, a designed integrated circuit mask pattern is digitized and taken into a computer as digital data (graphic data). When the mask pattern is defined with a hierarchical structure, the hierarchical information is expanded, and all the graphic patterns are expanded on a plane. Subsequently, an operation for recognizing each circuit element is performed on the developed graphic pattern. For example, for a MOS integrated circuit, a figure pattern obtained by performing an AND operation between a figure pattern of a diffusion layer and a figure pattern of a polysilicon layer can be recognized as a gate channel layer. After recognizing each circuit element by such a graphic operation, subsequently, the equipotential of each node is recognized, so that connection information between the circuit elements can be obtained. The recognition of the equipotential is performed by calculating the phase between the layers of the mask pattern. For example, if there is a contact hole graphic in an overlapping portion of two different conductive layers, it can be recognized that the two conductive layers have the same potential.

[0004]

SUMMARY OF THE INVENTION Large scale integrated circuits,
With miniaturization, integrated circuit mask patterns have become very complex. Therefore, a hierarchical design method is employed in order to efficiently design a mask pattern. In other words, the design is advanced step by step from a combination of simple ones to a more complex one, and a higher-level circuit is designed by converting the lower-level circuit into a macro. For example, basic logic gates such as a NOR gate and a NAND gate are designed by combining lower-level transistor elements, and a unit such as an ALU is designed by combining these logic gates. Further, by combining such units, a unit having a complicated function such as a microprocessor can be designed. The data amount of such a large-scale circuit can be reduced by employing a hierarchical expression.
An integrated circuit mask pattern designed in such a manner has a hierarchical structure.

However, in the conventional circuit connection information extracting method for an integrated circuit mask pattern, as described above, after the mask pattern is digitized and taken in, all the hierarchical information is expanded, and all the graphic patterns are expanded on a plane. Since the graphic operation and the phase operation are performed in this state, it takes a very long processing time. Also, the extracted circuit connection information is limited to the connection information for the lowest level hierarchy.

Accordingly, an object of the present invention is to provide a method capable of extracting desired circuit connection information in a short processing time by performing an efficient operation.

[0007]

Means for Solving the Problems (1) The first invention of the present application is to convert a mask pattern from an integrated circuit mask pattern into a mask pattern.
Processing to extract connection information for circuits represented by
Extract circuit connection information from integrated circuit mask pattern to be executed
In output method, digitizing an integrated circuit mask pattern
Digitizing means to capture as digital data
A cell that specifies a specific cell on the integrated circuit mask pattern
Designating means and each end for connecting to the outside of the designated cell
Same text for terminals that are equipotential for
Enter a text name for each terminal
Position information extracting means for extracting position information of
Through the mask pattern existing outside and inside the designated cell
Mask pattern and text name for wiring that passes
Extracts circuit connection information for each terminal with
Connection information extraction means for extracting
For multiple terminals with the same text name
Circuit connections to ensure a mutually conductive connection.
Circuit connection information having correction processing means for correcting connection information.
Prepare an information extraction device, and digitize the integrated circuit
The first to capture the mask pattern as digital data
Perform the steps and use the cell designator to
Perform a second step of entering the specification of a particular cell based on
Based on the operator's instruction
Enter the text name for each terminal,
Perform third step of extracting the position information, the connection information extracting hands
Performing a fourth stage of extracting circuit connection information by the stage;
Fifth stage in which the circuit connection information is corrected by the correction processing means
It is designed to be on the floor.

(2) The second invention of the present application is an integrated circuit mask.
From patterns to circuits expressed as mask patterns
IC that executes a process of extracting connection information about
In the circuit connection information extracting method of the disk pattern, each
A collection in which the text name of the terminal is added as a character code
Digitize integrated circuit mask pattern
The text name of each terminal together with the
Digitizing means for capturing data as an
Cell designation means to designate a specific cell on the turn, and designation
For each terminal that connects to the outside of the cell,
Position information extracting means for extracting position information, and a designated cell
Mask pattern outside the specified area and inside the specified cell
The mask pattern and each terminal for the wiring that passes
Connection information extraction means for extracting circuit connection information as an object
And the same text name in the extracted circuit connection information
For multiple terminals marked with,
Modify the circuit connection information so that the connection relationship is secured
Processing means, providing a circuit connection information extracting device having,
Terminals that have the same potential due to digitizing means are the same.
Integrated circuit mask pattern with the same text name
The performing a first step of capturing a digital data, Se
Specified by the operator
Performing a second step of inputting the specified cell position information extraction
Of each terminal for connection to the outside of the cell
Te performs third step of extracting each position information, contact
A fourth connection information extracting unit for extracting circuit connection information;
Perform the steps and correct the circuit connection information by the correction processing means
The fifth step is performed.

(3) The third invention of the present application is the method according to each of the above inventions, wherein the correction processing means comprises a plurality of designated cells.
If adjacent, based on the position information of each terminal,
Check if there are terminals that touch each other, and
For terminals that come into contact with
Modified the circuit connection information to secure
It is.

[0010]

In the method according to the present invention, a predetermined cell is designated by an operator before performing various arithmetic processes for extracting circuit connection information. The circuit connection information extraction processing is performed only for circuits outside the specified cell, and not performed for circuits inside the cell. However, a text name is given to the external connection terminal of the designated cell, and an equipotential process is performed based on the text name. Thus,
As for the outside of the designated cell, the circuit connection information for the lowest level hierarchy is extracted as in the conventional method, but the circuit connection information for the inside of the designated cell is not extracted. In other words, the connection information at the element level can be obtained outside the specified cell, but the specified cell remains as a cell as it is, and the connection information in a state where the element and the cell are mixed can be extracted. . For this reason, an efficient operation can be performed only on a necessary portion, and desired circuit connection information can be extracted in a short processing time.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a procedure of a method for extracting circuit connection information from an integrated circuit mask pattern according to one embodiment of the present invention. First, in step S1 of the first stage, a process of digitizing the integrated circuit mask pattern 1 and taking it as digital data in a computer is performed. The integrated circuit mask pattern 1 is designed based on the original circuit diagram. However, since the integrated circuit mask pattern 1 is usually designed hierarchically,
The mask pattern also has a hierarchical structure. In the conventional method, a hierarchical structure is developed for a mask pattern input as digital data, and processing for developing all graphic patterns of the lowest hierarchy on one plane is performed. It is not necessary to perform the processing of expanding the entire hierarchical structure, but only the necessary parts are expanded as described later.

Here, for convenience of explanation, the following description will be made taking a simple mask pattern as shown in FIG. 2 as an example. This mask pattern is designed with a hierarchical structure as shown in FIG. That is, the entire circuit, which is the highest hierarchy, is given the name TOP.
A cell A and a cell B are defined in the lower hierarchy, and a cell C and a cell D are defined as the lower hierarchy. The black dot at the lower left of each cell in FIG. 2 indicates the origin position of the imposition of each cell on the upper hierarchy. The spatial position of each cell on the mask pattern can be indicated by the coordinate value of the origin with respect to the cell in the upper hierarchy. Specifically, coordinate values indicating the imposition position as shown in FIG. 4 are defined.
In a mask pattern designed with a hierarchical structure, such a hierarchical structure of cells can be easily recognized.

In step S2 of the second stage, a desired cell is specified. This cell designation is performed based on the cell designation input from the operator. here,
The following description will be continued assuming that the operator has designated the cells A and D, and the designated cells A and D will be referred to as “designated cells”. Which cell is specified is determined based on the operator's intention, but usually specifies a cell for which it is not necessary to extract internal circuit connection information. Specifically, a cell that is a basic cell that has been used many times in the past and that is used frequently and is guaranteed to have no problem with the circuit operation of the cell is specified. It will be. For such a cell, there is no need to extract circuit connection information again. When the specification of the cell is completed, the hierarchical structure is expanded only outside the specified cell, and the hierarchical structure inside the specified cell is ignored. For example, cell A,
When D is designated, as shown in FIG. 5, the hierarchical structure is expanded only outside designated cells A and D indicated by solid lines, and the hierarchical structure inside designated cells A and D is ignored. As a result, the cell B is expanded and the cell C is ignored, and the hierarchical structure shown in FIG. 3 is changed to a structure as shown in FIG. The expanded cell B has a form included in the TOP.

In the subsequent step S3 of the third stage, a process of assigning a text name to each terminal for connection to the outside of the designated cell and extracting position information of each terminal is performed.
This process will be described with a specific example. Now, it is assumed that the designated cells A and D designated in step S2 are cells having a structure as shown in FIGS. 7A and 7B. The designated cell A includes a lower-level cell C, has a wiring layer CW inside, and is connected to wiring layers W1 to W4 outside the cell. On the other hand, the designated cell D has two transistor elements TR inside and is connected to wiring layers W5 and W6 outside the cell. In this way, a text name is given to each terminal for connecting to each wiring layer outside the cell. At this time, the same text name is assigned to the terminals having the same potential. For example, regarding the cell A, as shown in FIG. 7A, the terminal connected to the wiring layer W1 and the terminal connected to the wiring layer W2 are connected to each other by the wiring layer CW and thus have the same potential. Therefore, the same text name “a” is given to these terminals.
Thus, the four terminals of cell A are a, a,
Text names b and c are given, and two terminals of cell D are given text names a and b, respectively. At the same time, the position information of each of these terminals is extracted as coordinate values for the origin (the lower left point in this example) of each cell. Thus, a result as shown in FIG. 8 is obtained. In the above-described example, the input of the text name is performed by the operator. However, usually, the text name of each terminal is added as a character code to the mask pattern. Have the same text name. Therefore, if the text name added as the character code to the mask pattern is automatically taken in, the operator does not need to input the text name each time.

In the next step S4 of the fourth stage, the circuit connection information is extracted from the mask pattern outside the designated cell. In the above example, since the cells A and D are designated, the circuit connection information is extracted for the portion outside the designated cells A and D shown by hatching in FIG. This circuit connection information extraction processing may use exactly the same method as the conventional method. More specifically, an operation for recognizing each circuit element is performed. For example, for a MOS integrated circuit, a figure pattern obtained by performing an AND operation between a figure pattern of a diffusion layer and a figure pattern of a polysilicon layer can be recognized as a gate channel layer. After recognizing each circuit element by such a graphic operation, subsequently, the equipotential of each node is recognized, so that connection information between the circuit elements can be obtained. The recognition of the equipotential is performed by calculating the phase between the layers of the mask pattern. For example, as shown in FIG. 10, wiring layers W1 and W provided as two different graphic patterns
If the figure pattern CT of the contact hole exists in the overlapping region of 2, the wiring layers W1 and W2 can be recognized as having the same potential.

As described above, the process of step S4 is exactly the same as the conventional circuit connection information extraction process, except that the region to be extracted is limited to only the portion outside the designated cell. Are different. More specifically, the extraction processing is performed with the mask pattern data inside the designated cells A and D kept masked. In such an extraction process, the circuit connection information is not extracted inside the designated cell, so that the circuit connection information is divided at the boundary portion corresponding to the contour of the designated cell. For example, as shown in FIG.
Since the connection relation of the element 1 inside the cell A cannot be obtained, the connection information of the wiring layer W1 is separated at the boundary of the cell A. The same applies to the cell D shown in FIG. Therefore, for this divided portion, the connection relationship with each terminal of the cell is obtained based on the terminal position information extracted in step S3. That is,
As shown in FIG. 4, the absolute coordinates of the imposition position of each cell with respect to TOP, which is the highest hierarchy, can be obtained by using the information on the imposition position coordinates of each cell. For example, the absolute coordinates of the imposition position on the TOP for the designated cells A and D are as shown in FIG. After all, the terminal coordinates (coordinate values in the cell) of each terminal shown in FIG.
It is possible to convert to absolute coordinates for P. Therefore, for example, the terminals a, a, and
Since the absolute position coordinates of b and c are obtained, the wiring layers W1 to W4
Are connected to the terminals a, a, b, and c. Thus, for example, the wiring layer W1 is connected to the terminal a of the cell A, and the wiring layer W5 is connected to the terminal a of the cell D.
Connection information, such as connection to the server.

Incidentally, a power supply wiring layer generally passes through each cell constituting an integrated circuit. For example, the cell D 'shown in FIG. 13 is obtained by adding the power supply wiring layers Vdd and Gnd to the cell D shown in FIG. 7B, and these power supply wiring layers pass through the cell D', respectively. Arranged to be. Such a power supply wiring layer has no meaning with respect to the function of the cell D ', but has an important meaning for circuits outside the cell D'. That is, in FIG. 13, the wiring layers W7, W8, W9, W1
If 0 remains disconnected at the boundary of cell D ', correct circuit connection information cannot be obtained. Therefore, for such power supply wiring layers Vdd and Gnd, the cell D
Although it is a mask pattern inside ', it is convenient if it is set as a target of the circuit connection information extraction processing in step S4. Usually, such power supply wiring layers Vdd, Gn
Since d is given as a mask pattern arranged on a layer dedicated to power supply wiring, it is easy to distinguish it from other mask patterns in the cell D ′ and to include it in the circuit connection information extraction processing. As a result, regarding the cell D ′, as shown in FIG. 14, the terminals a and b and the power supply wiring layer Vd
Only d and Gnd may be included in the circuit connection information extraction processing. Generally, some wiring layers other than the power supply wiring layer simply pass through the cell. As described above, the wiring layer passing through the inside of the cell may be included in the circuit connection information extraction processing even if it is other than the power supply wiring layer. As described above, if the wiring layer passing through the cell is included in the extraction processing target, when performing the equipotential processing, FIG.
In the example of No. 4, it is recognized that the wiring layers W7, Vdd, and W8 have the same potential, and similarly, the wiring layers W9, Gnd, and W10 have the same potential.

Finally, in a fifth step S5, the circuit connection information obtained in the step S4 is corrected.
In other words, terminals to which the same text name is assigned in the same designated cell are assumed to be at the same potential, and a correction is made so that a mutually conductive connection relationship is obtained. For example, in FIG. 11, connection information indicating that both of the wiring layers W1 and W2 are connected to the terminal of the designated cell A to which the same text name a is assigned is obtained. In this case, since the wiring layers W1 and W2 have the same potential, these wiring layers are modified to have a connection relationship of conducting each other.

For example, as shown in FIG.
When two designated cells X and Y are adjacent to each other, it is checked whether there is a terminal that contacts each other based on the absolute position coordinates of the terminal of each designated cell, and the terminals that contact each other are electrically connected to each other. To ensure the connection relationship,
Modify the circuit connection information. In the example of FIG. 15, the terminals a and d are in contact with each other on the boundary line Z between the two cells. Therefore, a conductive connection between the terminal a and the terminal d is ensured. As a result, the wiring layers W1, W3, W
7 and W8, the circuit connection information is corrected so as to obtain a connection relationship of conducting.

Thus, the final circuit connection information is obtained. This circuit connection information is, so to speak, information in which element-level connection information and cell-level connection information are mixed. That is, the connection information at the element level is shown for the circuit in the hatched portion in FIG.
For D, only information indicating that the cells A and D are present at this position and information indicating the connection relationship between the external connection terminals of the cells A and D and the circuit in the hatched portion are shown. The connection information at the element level of the circuits inside A and D is omitted. By omitting the extraction of connection information for cells A and D that do not require detailed internal information, efficient extraction can be performed in a short time.

Although the present invention has been described based on the illustrated embodiment, the present invention is not limited to this embodiment. In particular, the above-described embodiment is for a very simple model for convenience of explanation, and the present invention is actually applied to a more complicated mask pattern.

[0022]

As described above, according to the present invention, in a method for extracting circuit connection information from an integrated circuit mask pattern,
A predetermined cell is designated in advance, and the circuit connection information is extracted only for the portion outside the designated cell.
Desired circuit connection information can be extracted.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing procedure of a circuit connection information extraction method from an integrated circuit mask pattern according to one embodiment of the present invention.

FIG. 2 is a diagram showing an example of a specific mask pattern having a hierarchical structure used for explaining the procedure of FIG. 1;

FIG. 3 is a diagram showing a hierarchical structure of the mask pattern shown in FIG. 2;

FIG. 4 is a table showing imposition positions of cells in the mask pattern shown in FIG. 2;

FIG. 5 is a diagram showing a state where a cell is specified for the mask pattern shown in FIG. 2;

FIG. 6 is a diagram showing a hierarchical structure after the cell designation shown in FIG. 5;

FIG. 7 is a diagram showing an internal structure of designated cells A and D.

FIG. 8 is a table showing an example of extracting data relating to external connection terminals for designated cells A and D shown in FIG. 7;

FIG. 9 is a diagram showing a portion outside cells A and D to be subjected to circuit connection information extraction processing.

FIG. 10 is a diagram showing one method of equipotential recognition in circuit connection information extraction processing.

FIG. 11 is a diagram showing information left on designated cells A and D when performing circuit connection information extraction processing.

FIG. 12 is a table showing imposition positions of designated cells A and D on a TOP obtained based on the table shown in FIG. 4;

FIG. 13 is a diagram showing a cell D ′ in which a power supply wiring layer passes.

FIG. 14 is a diagram showing information left when performing circuit connection information extraction processing for the cell D ′ shown in FIG. 13;

FIG. 15 is a diagram illustrating processing for recognizing adjacent terminals as equipotentials when two adjacent designated cells exist.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Integrated circuit mask pattern A-D, X, Y ... Cell ad ... External connection terminal W1-W10 ... Wiring layer CT ... Contact hole TR ... Transistor Vdd, Gnd ... Power supply wiring layer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-182873 (JP, A) JP-A-63-129466 (JP, A) JP-A-4-304562 (JP, A) JP-A-4- 172564 (JP, A) Junko Terao, et al., "Hierarchical Connection Verification in VLSI Layout Verification System FRIEND," IEICE Technical Report, IEICE, 1987, Vol. 86, No. 328, p. 9-15 (CAS86-204) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 666 JICST file (JOIS)

Claims (3)

(57) [Claims] An integrated circuit mask pattern is digitized.
Digitizing means for taking in as digital data, and specifying a specific cell on the integrated circuit mask pattern
Cell designating means and each terminal for connection to the outside of the designated cell
Therefore, terminals with the same potential have the same text name
Enter the text name for each
Position information extracting means for extracting position information; a mask pattern existing outside the designated cell;
Mask pattern for wiring passing inside the specified cell
And each terminal to which the above-mentioned text name is assigned
The connection information extracting means for extracting the circuit connection information and the same text name are added to the extracted circuit connection information.
For a given set of terminals, the connection
Modification to modify the circuit connection information so as to secure the engagement
And processing means, the circuit connection information extracting device having an integrated circuit mask pattern
From the diagram, the circuit expressed as a mask pattern
A method for extracting all connection information, wherein the digitizing means digitizes an integrated circuit mask pattern.
A first step of taking a barrel data, said cell specifying means, based on the instruction of the operator, especially
A second step of inputting the specification of the constant of the cell, said position information extracting means, based on the instruction of the operator
Enter the text name for each terminal,
A third step of extracting the connection information; and a fourth step of extracting the circuit connection information by the connection information extracting means.
And a fifth step in which the correction processing means corrects the circuit connection information.
Circuit connection information extraction method from the integrated circuit mask pattern and to execute the floor, the. 2. The text name of each terminal is represented by a character code.
Digitizes the added integrated circuit mask pattern
And the text of each terminal together with the integrated circuit mask pattern
Digitizing means for capturing a name as digital data, and designating a specific cell on the integrated circuit mask pattern
Cell designating means and each terminal for connection to the outside of the designated cell
A position information extracting unit for extracting position information, and a mask pattern existing outside the designated cell and
Mask pattern for wiring passing inside the specified cell
And extract circuit connection information for each terminal
The same text name is assigned to the connection information extracting means to be connected and the extracted circuit connection information.
For a given set of terminals, the connection
Modification to modify the circuit connection information so as to secure the engagement
And processing means, the circuit connection information extracting device having an integrated circuit mask pattern
From the diagram, the circuit expressed as a mask pattern
A process for extracting all connection information, wherein the digitizing means performs the same for terminals having the same potential.
Integrated circuit mask pattern with the same text name
A first step of capturing a digital data, said cell specifying means, based on the instruction of the operator, especially
A second step of inputting the designation of a fixed cell, and the position information extracting means includes
Third stage of extracting position information for each terminal
And a fourth step in which the connection information extracting means extracts circuit connection information.
And a fifth step in which the correction processing means corrects the circuit connection information.
Circuit connection information extraction method from the integrated circuit mask pattern and to execute the floor, the. 3. The extraction method according to claim 1, wherein the correction processing means determines whether the plurality of designated cells are adjacent to each other.
Are terminals that contact each other based on the position information of each terminal
Check for the presence of
In order to ensure a mutually conductive connection,
Integrated circuit mask for correcting circuit connection information
A method for extracting circuit connection information from patterns.