JP5805452B2 - LSI circuit diagram restoration device - Google Patents

Description

  The present invention relates to an LSI circuit diagram restoration device for restoring an LSI circuit diagram based on design data indicating an LSI layout pattern.

  An LSI is an aggregate of a large number of circuit elements, and the design data includes a large amount of information such as figures indicating areas such as semiconductor layers and conductor layers constituting the elements and coordinates indicating their arrangement. . In order to efficiently accommodate such an enormous amount of information, LSI design data is usually built with a hierarchical structure with cells as the smallest unit, and by developing this hierarchically structured design data, A layout pattern in which a large number of figures are arranged on a plane can be obtained.

  When manufacturing an LSI, it is important to display the layout pattern on a display screen and perform a confirmation operation or a verification operation. Therefore, a layout pattern display device that displays a layout pattern based on LSI design data has been conventionally used. For example, Patent Document 1 below discloses an apparatus that extracts a desired partial layout pattern from LSI design data and displays it on a screen. Further, Patent Document 2 discloses a layout verification device that expands and displays layout patterns of different hierarchies in and out of a window based on design data having a hierarchical structure. Describes that a netlist can be created.

  On the other hand, a technique for restoring individual element information from LSI design data has also been proposed. For example, Patent Document 3 below discloses a technology for performing equipotential tracking based on LSI design data and recognizing individual elements. Patent Document 4 discloses an electronic circuit restored from layout data. Later, a technique for searching for and reducing redundant elements is disclosed.

JP-A-3-83172 JP-A-4-85675 JP-A-4-262461 Japanese Patent Laid-Open No. 4-88482

  As described above, a device that creates a layout pattern by expanding a hierarchical structure based on LSI design data having a hierarchical structure with cells as a minimum unit and displays the layout pattern on a display screen has been conventionally used. ing. Also, several techniques for restoring the original circuit diagram from the layout pattern have been proposed by the above-mentioned Patent Document 4 and the like.

  However, the layout pattern developed on the plane is an aggregate of a large number of figures, and the concept of cells does not exist in the layout pattern itself. For this reason, it is difficult to accurately restore a circuit diagram from a layout pattern, and any of the methods proposed so far has a problem in practicality. In particular, with the conventionally proposed method, it is difficult to efficiently and accurately restore the circuit diagram in the vicinity of a specific part of the layout pattern in a state where a part of the layout pattern is displayed on the display screen. is there.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an LSI circuit diagram restoration apparatus capable of accurately restoring a circuit diagram of an arbitrary part of a layout pattern.

(1) According to a first aspect of the present invention, there is provided an LSI circuit diagram restoration device for restoring a circuit diagram of an LSI based on design data indicating an LSI layout pattern.
A cell configuration data storage unit for storing cell configuration data in which individual components constituting an LSI are recorded for each layer of a figure as a component;
A block for storing block configuration data including cell arrangement information indicating the position coordinates of each cell and inter-cell wiring information indicating a figure constituting the inter-cell wiring for a block in which a plurality of cells are arranged at predetermined positions. A configuration data storage;
A design data input unit for inputting data to the cell configuration data storage unit and the block configuration data storage unit;
A layout pattern display unit that draws a display target pattern on a plane based on the cell configuration data and the block configuration data, and displays the pattern as an image;
Among the layers included in the cell configuration data, the cell frame determination condition including information indicating a specific layer used for cell frame determination and the plurality of figures included in the cell configuration data and the block configuration data are equipotential to each other. Recognize a specific element based on equipotential tracking conditions indicating requirements, area recognition conditions for performing area recognition based on graphics included in cell configuration data, and connection relationships between multiple areas and terminal points A condition setting unit for setting element recognition conditions;
For each cell, a figure recorded in a specific layer used to determine the cell frame of the cell configuration data is extracted, a logical sum figure of the extracted figure is formed, and a circumscribed figure of this logical sum figure is obtained as a cell frame. A cell frame determination unit;
A terminal that recognizes the intersection line segment that is cut by the intersection figure for the intersection figure that intersects the cell frame among the figures included in the inter-cell wiring information, and determines the terminal point at one point on this intersection line segment A point determination unit;
An equipotential tracking unit that recognizes another figure that is equipotential as an equipotential figure with respect to a specific figure of interest constituting the layout pattern based on the equipotential tracking condition;
An area recognition unit for recognizing each element configuration area constituting an element for a graphic included in cell configuration data in a predetermined recognition target cell based on an area recognition condition;
The connection relationship between the plurality of element configuration regions recognized by the region recognition unit and the terminal points determined by the terminal point determination unit is electrically connected to the figures recognized as being equipotential to each other by the equipotential tracking unit. An element recognition unit that recognizes an element corresponding to a recognition target cell by checking with an element recognition condition while handling it as an object,
A circuit diagram display unit for displaying a logic circuit diagram for a display target circuit by associating an element recognized by the element recognition unit with a logic circuit symbol and associating inter-cell wiring information with a connection between logic circuit symbols;
A display target designating unit having a function of designating a display target pattern for the layout pattern display unit, and a function of designating a display target circuit for the circuit diagram display unit,
Provided,
The cell configuration data storage unit stores cell configuration data in which a figure as a component is recorded for each layer to which a predetermined identification code is attached,
The block configuration data storage unit stores wiring information including figures constituting the inter-cell wiring or inter-block wiring for each layer to which a predetermined identification code is attached,
The condition setting unit sets information indicating a contact layer including a figure indicating a contact for connecting between a plurality of layers together with information indicating a conductive layer as an equipotential tracking condition,
The equipotential tracking unit recognizes that the superimposed figure is equipotential when the figures belonging to a plurality of conductive layers with the same identification code are superimposed on each other, and is different from each other. When a figure belonging to multiple conductive layers with identification codes is superimposed in a plane, the superimposed figure is equipotential only if there is a figure belonging to the contact layer in the overlap area. It is intended to recognize that there is.

(2) According to a second aspect of the present invention, in the LSI circuit diagram restoration device according to the first aspect described above,
It has a hierarchical structure consisting of all n layers (where n ≧ 2) including the 1st to (n−1) th layers in which blocks are arranged and the nth layer in which cells are arranged. To handle the layout pattern of LSI
The cell configuration data storage unit stores cell configuration data in which individual components belonging to the nth layer are recorded as graphic elements for each layer.
The block configuration data storage unit stores block configuration data for blocks belonging to the i-th (1 ≦ i ≦ n−1) hierarchy, and in the case of i <n−1, Block arrangement information indicating position coordinates and inter-block wiring information indicating graphics constituting the inter-block wiring are stored. When i = n−1, a cell indicating the position coordinates of a cell belonging to a lower layer is stored. Placement information and inter-cell wiring information indicating a figure constituting inter-cell wiring are stored,
The terminal point determination unit determines the terminal points for the graphic included in the inter-block wiring information together with the terminal points for the graphic included in the inter-cell wiring information.

(3) According to a third aspect of the present invention, in the LSI circuit diagram restoring device according to the first or second aspect described above,
The cell configuration data storage unit stores cell configuration data in which a graphic composed of polygons constituted by sides parallel to the x axis or the y axis in the xy coordinate system is recorded,
The cell frame determination unit obtains a regular circumscribed rectangle formed by sides parallel to the x axis or the y axis as the cell frame.

(4) A fourth aspect of the present invention is an LSI circuit diagram restoration device according to the first to third aspects described above,
The condition setting unit sets the priority order for the combination of a pair of layers with different identification codes as equipotential tracking conditions,
When the equipotential tracking unit has two-dimensionally superimposed figures belonging to three or more layers with different identification codes attached, and there is a figure belonging to the contact layer in the overlapping area, Only the superimposed figure belonging to the pair of layers based on it is recognized as being equipotential.

(5) According to a fifth aspect of the present invention, in the LSI circuit diagram restoration device according to the first to fourth aspects described above,
The terminal point determination unit uses each crossed figure intersecting the cell frame as a target figure and gives an equipotential tracking instruction to the equipotential tracking unit, and any of the crossed figures recorded in the cell configuration data corresponding to the cell frame The intersection line segment is recognized only for the intersecting figure in which the figure becomes an equipotential figure.

(6) According to a sixth aspect of the present invention, in the above-described LSI circuit diagram restoration device according to the first to fifth aspects ,
The condition setting unit assigns the logical product area of figures belonging to different layers to a specific element configuration area, and the figure area belonging to the specific layer and including the recognized specific element configuration area. A rule associated with a specific element configuration region is set as a region recognition condition.

(7) According to a seventh aspect of the present invention, in the LSI circuit diagram restoration device according to the first to sixth aspects described above,
The condition setting unit sets, for each of a plurality of candidate elements, a rule indicating a mutual connection relationship between a plurality of element configuration regions and terminal points constituting the element as an element recognition condition. .

(8) An eighth aspect of the present invention is the LSI circuit diagram restoration device according to the first to seventh aspects described above,
The condition setting unit determines the region recognition conditions for recognizing the channel region, gate region, source / drain region, the mutual connection relationship between the channel region, gate region, source / drain region, and the connection relationship between these and the terminal points. Based on this, an element recognition condition for recognizing a logic element including a MOS transistor is set.

(9) According to a ninth aspect of the present invention, in the LSI circuit diagram restoration device according to the first to eighth aspects described above,
  The display target designating unit displays a part of the entire layout pattern as a display target pattern for the layout pattern display unit, and the circuit corresponding to the display target pattern is displayed for the circuit diagram display unit. And a function designated as a target circuit.

(10) According to a tenth aspect of the present invention, in the LSI circuit diagram restoration device for restoring the circuit diagram of the LSI based on the design data indicating the layout pattern of the LSI,
  A cell configuration data storage unit for storing cell configuration data in which individual components constituting an LSI are recorded for each layer of a figure as a component;
  A block for storing block configuration data including cell arrangement information indicating the position coordinates of each cell and inter-cell wiring information indicating a figure constituting the inter-cell wiring for a block in which a plurality of cells are arranged at predetermined positions. A configuration data storage;
  A design data input unit for inputting data to the cell configuration data storage unit and the block configuration data storage unit;
  A layout pattern display unit that draws a display target pattern on a plane based on the cell configuration data and the block configuration data, and displays the pattern as an image;
  Among the layers included in the cell configuration data, the cell frame determination condition including information indicating a specific layer used for cell frame determination and the plurality of figures included in the cell configuration data and the block configuration data are equipotential to each other. Recognize a specific element based on equipotential tracking conditions indicating requirements, area recognition conditions for performing area recognition based on graphics included in cell configuration data, and connection relationships between multiple areas and terminal points A condition setting unit for setting element recognition conditions;
  For each cell, a figure recorded in a specific layer used to determine the cell frame of the cell configuration data is extracted, a logical sum figure of the extracted figure is formed, and a circumscribed figure of this logical sum figure is obtained as a cell frame. A cell frame determination unit;
  A terminal that recognizes the intersection line segment that is cut by the intersection figure for the intersection figure that intersects the cell frame among the figures included in the inter-cell wiring information, and determines the terminal point at one point on this intersection line segment A point determination unit;
  An equipotential tracking unit that recognizes another figure that is equipotential as an equipotential figure with respect to a specific figure of interest constituting the layout pattern based on the equipotential tracking condition;
  An area recognition unit for recognizing each element configuration area constituting an element for a graphic included in cell configuration data in a predetermined recognition target cell based on an area recognition condition;
  The connection relationship between the plurality of element configuration regions recognized by the region recognition unit and the terminal points determined by the terminal point determination unit is electrically connected to the figures recognized as being equipotential to each other by the equipotential tracking unit. An element recognition unit that recognizes an element corresponding to a recognition target cell by checking with an element recognition condition while handling it as an object,
  A circuit diagram display unit for displaying a logic circuit diagram for a display target circuit by associating an element recognized by the element recognition unit with a logic circuit symbol and associating inter-cell wiring information with a connection between logic circuit symbols;
  A display target designating unit having a function of designating a display target pattern for the layout pattern display unit, and a function of designating a display target circuit for the circuit diagram display unit,
  Provided,
  The display target specification part
  A function for inputting an operator's instruction for designating a specific graphic on the display screen of the layout pattern, and a function for designating a part of a circuit related to the specific graphic as a display target circuit for the circuit diagram display unit. ,
  If the specific figure specified on the layout pattern is a figure in the cell frame, signals for n stages (n is an integer of 0 or more) upstream or downstream from the cell in the cell frame as the starting point To recognize the adjacent cell, specify that the cell that is the starting point and the circuit corresponding to the adjacent cell are the display target circuit,
  If the specific figure specified on the layout pattern is a figure that forms the wiring outside the cell frame, the signal is sent for n stages (n is an integer of 1 or more) upstream or downstream from the wiring. By tracing, the adjacent cell is recognized, and the designation that the circuit corresponding to the adjacent cell is the display target circuit is performed.

  (11) An eleventh aspect of the present invention is an LSI circuit diagram restoration device according to the tenth aspect described above,
  The circuit diagram display unit has a function of displaying on the circuit diagram a cell range frame for indicating a range of logic circuits belonging to the same cell.

(12) According to a twelfth aspect of the present invention, in the LSI circuit diagram restoring device according to the tenth or eleventh aspect described above,
The condition setting unit sets an element recognition condition for recognizing a specific element based on a connection relationship including a terminal point having at least two types of attributes of an input terminal and an output terminal,
The element recognition unit performs attribute recognition of the terminal points of each cell based on the element recognition conditions,
The circuit diagram display unit executes an inter-cell signal tracking process for tracking n stages of cells from the starting point in consideration of the attribute of the terminal point of each cell, and specifies the display target circuit.

(13) In a thirteenth aspect of the present invention, the LSI circuit diagram restoring apparatus according to the first to twelfth aspects described above is configured by incorporating a dedicated program into a computer.

  According to the LSI circuit diagram restoration device of the present invention, a circumscribed figure of a figure group recorded in a specific layer set as a cell frame determination condition is obtained as a cell frame, and the intersection of the cell frame and the wiring is obtained. A terminal point is determined at the position. For this reason, virtual cell frames and terminal points are defined on the layout pattern, and the concept of cells can be restored. Then, the individual element constituent areas constituting the elements are recognized for the graphic in the cell frame, and the elements are recognized based on the mutual connection relationship between these areas and the terminal points. Therefore, it becomes possible to recognize the element efficiently and accurately in cell units for the desired portion of the layout pattern, and the circuit diagram of an arbitrary part of the layout pattern can be restored efficiently and accurately. become.

It is a figure which shows an example of the hierarchical structure of the design data of general LSI. It is a figure which shows the specific content of the layout pattern data when the 3rd hierarchy as shown in FIG. 1 is defined. FIG. 3 is a plan view showing a specific example of block arrangement information and inter-block wiring information recorded in the highest hierarchy “TOP” shown in FIG. 1. FIG. 3 is a plan view showing a specific example of cell arrangement information and inter-cell wiring information recorded in “block A” which is one of the intermediate hierarchies shown in FIG. 1. It is a top view which shows the specific example of the cell pattern information recorded on "cell C101" which is one of the lowest hierarchies shown in FIG. It is a figure which shows the layer structure of the cell pattern information shown in FIG. 4 is a table showing a specific data configuration example corresponding to block arrangement information and inter-block wiring information for “TOP” shown in FIG. 3. 6 is a table showing a specific data configuration example corresponding to cell arrangement information and inter-cell wiring information for “block A” shown in FIG. 4. 6 is a table showing a specific data configuration example corresponding to cell pattern information for “cell C101” shown in FIG. 5. It is a circuit diagram of an inverter circuit. It is a top view which shows the example of a display of a simple layout pattern. It is a top view which shows the state which defined the cell frame and terminal point which concern on this invention on the layout pattern shown in FIG. 1 is a block diagram showing a configuration of an LSI circuit diagram restoration device according to a basic embodiment of the present invention; FIG. It is a top view which shows the figure group extracted by the cell frame determination part 600 from the layout pattern of the cell C101 shown in FIG. It is a top view which shows the logical sum figure of the figure group shown in FIG. It is a top view which shows the cell frame F calculated | required as a circumscribed rectangle of the logical sum figure shown in FIG. FIG. 17 is a plan view showing a state in which the cell frame F shown in FIG. 16 is superimposed on the layout pattern of the cell C101 shown in FIG. FIG. 6 is a plan view showing inter-cell wiring (indicated by a broken line) for the cell C101 shown in FIG. It is a top view which shows the state by which the terminal points T1-T4 were determined in the intersection position of the cell frame F and the wiring between cells. 6 is a plan view showing a state in which a cell frame F and terminal points T1 to T4 are superimposed on a layout pattern including the periphery of a cell C101 shown in FIG. FIG. 21 is a diagram showing logic circuit symbols and terminals of logic elements corresponding to the layout pattern shown in FIG. 20. It is a figure which shows an example of the equipotential tracking conditions set to the condition setting part 800 in the apparatus shown in FIG. It is sectional drawing which shows the layer structure corresponding to the priority of the contact shown in FIG.22 (c). It is a top view which shows the simple layout pattern for demonstrating the specific process by the equipotential tracking part 550 in the apparatus shown in FIG. FIG. 25 is a plan view showing a result of executing an equipotential tracking process on the layout pattern shown in FIG. 24. It is a top view explaining the process which determines a terminal point except the wiring which passes only a cell using an equipotential tracking process. It is a top view which shows the handling of the wiring w5 between the cells which pass the cell C101 shown in FIG. It is a figure which shows the relationship between the circuit diagram of a general MOS transistor, and an element structure area | region. It is a figure which shows an example of the area | region recognition conditions set to the condition setting part 800 in the apparatus shown in FIG. It is a top view which shows the result of having performed area | region recognition about the cell shown in FIG. FIG. 31 is a plan view showing a connection relationship between each terminal point and each element configuration region for the cell shown in FIG. 30. It is a figure which shows an example of the element recognition conditions set to the condition setting part 800 in the apparatus shown in FIG. FIG. 32 is a diagram in which connection relationships recognized for the cells shown in FIG. 31 are extracted and rewritten in correspondence with the transistor level circuit diagram. It is the top view which showed the terminal attribute recognized about each terminal point with a respectively different figure about the cell shown in FIG. It is a top view for demonstrating the concept of the signal tracking process between cells performed by the apparatus shown in FIG. It is a top view which shows the circuit diagram displayed by the circuit diagram display part 730 in the apparatus shown in FIG.

  Hereinafter, the present invention will be described based on the illustrated embodiments.

<<< §1. Structure of general LSI design data >>>
As already described, LSI design data is usually constructed with a hierarchical structure with cells as minimum units. Therefore, in order to obtain the layout pattern of the entire LSI, a process of developing design data having this hierarchical structure is required.

  FIG. 1 is a diagram showing an example of a hierarchical structure of general LSI design data. This example is a simple example consisting of three hierarchies, in which four blocks A to D in the intermediate hierarchy are located under the TOP in the highest hierarchy, and cells in the lowest hierarchy are located under each block. (Cells below blocks B to D are not shown).

  FIG. 2 is a diagram showing specific contents of layout pattern data when the three layers as shown in FIG. 1 are defined. First, block arrangement information and inter-block wiring information are accommodated in the highest hierarchy “TOP”. Here, the block arrangement information is information indicating the arrangement of the four blocks A to D in the intermediate hierarchy, and the inter-block wiring information is information indicating the wiring between the blocks A to D. On the other hand, cell arrangement information and inter-cell wiring information are accommodated in the intermediate layer “block”. Here, the cell arrangement information is information indicating the arrangement of each cell in the lowest hierarchy, and the inter-cell wiring information is information indicating the wiring between the cells. The cell pattern information is accommodated in the lowest hierarchy “cell”. This cell pattern information is obtained by recording, for each layer, information on a figure that is a constituent element of a cell.

  FIG. 3 is a plan view showing a specific example of block arrangement information (FIG. 3 (a)) and inter-block wiring information (FIG. 3 (b)) recorded in the highest hierarchy “TOP” shown in FIG. Here, the information on the highest layer is illustrated using an αβ two-dimensional coordinate system having an origin Q. This αβ two-dimensional coordinate system can be said to be a global coordinate system for displaying all layout patterns of LSI.

  First, the block arrangement information recorded in the highest hierarchy “TOP” is information indicating the arrangement of the four blocks A to D on the αβ two-dimensional coordinate system, as shown in FIG. In this example, each of the blocks A to D has a rectangular outline, and its lower left points Qa (α1, β1), Qb (α2, β2), Qc (α3, β3), Qd (α4, β4) This coordinate value is the entity data constituting the block arrangement information.

  On the other hand, the inter-block wiring information recorded in the highest hierarchy “TOP” is information indicating the wirings W1 to W3 between the blocks A to D as shown in FIG. The broken-line rectangle shown in FIG. 3B indicates the positions of the four blocks A to D shown in FIG. 3A. In this example, between the wiring W1 between the blocks AB and the block BD. The wiring W2 and the wiring W3 between the blocks CD are illustrated. The wirings W1 to W3 are all polygonal, and their shapes and positions are specified by the coordinate values of the vertices. That is, the entity data of the wiring W1 is the coordinate values of the four vertices P1 to P4, the entity data of the wiring W2 is the coordinate values of the four vertices P5 to P8, and the entity data of the wiring W3 is the coordinate values of the four vertices P9 to P12. .

  FIG. 4 shows a specific example of cell arrangement information (FIG. 4 (a)) and inter-cell wiring information (FIG. 4 (b)) recorded in “block A” which is one of the intermediate layers shown in FIG. It is a top view. Here, this intermediate layer information is illustrated using an XY two-dimensional coordinate system having an origin O. This XY two-dimensional coordinate system can be called a local coordinate system with respect to the global αβ two-dimensional coordinate system, and the origin O shown in FIG. 4 (a) is the αβ two-dimensional coordinate system shown in FIG. 3 (a). Is assigned to the point Qa. The coordinate axes X and Y are axes parallel to the coordinate axes α and β, respectively. The XY two-dimensional coordinate system shown in FIG. 4 (a) is in the block A shown by a rectangle in FIG. 3 (a). Is housed exactly like

  The cell arrangement information recorded in the intermediate layer “block A” is information indicating the arrangement of the three cells C101 to C103 on the XY two-dimensional coordinate system, as shown in FIG. In this example, each of the cells C101 to C103 has a rectangular outline, and the coordinate values of the lower left points R1 (X1, Y1), R2 (X2, Y2), R3 (X3, Y3) are the cell arrangement information. This is the entity data that constitutes.

  On the other hand, the inter-cell wiring information recorded in the intermediate layer “block A” is information indicating the wirings W4 and W5 between the cells C101 to C103, as shown in FIG. 4B shows the positions of the three cells C101 to C103 shown in FIG. 4A. In this example, the wiring W4 between the cells C101 / C102 and the cell The wiring W5 between C102 / C103 is illustrated. The wirings W4 and W5 are both polygonal, and their shapes and positions are specified by the coordinate values of the vertices. That is, the entity data of the wiring W4 is the coordinate values of the four vertices P21 to P24, and the entity data of the wiring W5 is the coordinate values of the six vertices P25 to P30.

  Similarly, cell arrangement information and inter-cell wiring information are prepared for the other blocks B to D in the intermediate layer, but illustration is omitted here.

  FIG. 5 is a plan view showing a specific example of cell pattern information recorded in “cell C101”, which is one of the lowest layers shown in FIG. The cell pattern information is information in which a graphic pattern as a constituent element of the cell C101 is recorded for each layer. Here, this cell pattern information is illustrated using an xy two-dimensional coordinate system having an origin o. The xy two-dimensional coordinate system indicated by lowercase letters can be said to be a local coordinate system with respect to the XY two-dimensional coordinate system indicated by uppercase letters, and the origin o shown in FIG. 5 is a point in the XY two-dimensional coordinate system shown in FIG. Assigned to R1. The coordinate axes x and y are axes parallel to the coordinate axes X and Y, respectively, and the xy two-dimensional coordinate system shown in FIG. 5 is completely accommodated in the cell C101 shown by a rectangle in FIG. Is done.

  The cell pattern information recorded in the lowest hierarchy “cell C101” is information indicating the shapes and positions of eleven figures f1 to f11 as shown in FIG. In this example, the graphics f1 to f11 are all rectangular, and the substance data of the cell pattern information is the coordinate value of each vertex on the xy two-dimensional coordinate system. The cell C101 illustrated here is actually an “inverter circuit” composed of a PMOS transistor and an NMOS transistor.

  The information indicating the eleven figures f1 to f11 shown in FIG. 5 is actually recorded in five layers having different constituent materials. FIG. 6 is a diagram showing a layer configuration of the cell pattern information shown in FIG. That is, in the “cell C101”, five layers of a polysilicon layer L1, a diffusion layer L2, a metal layer L3, a well layer L4, and a contact layer L5 are defined, and the pattern of the figure f1 is defined in the polysilicon layer L1. Information, pattern information of figures f2 and f3 in the diffusion layer L2, pattern information of figures f4 to f6 in the metal layer L3, pattern information of figure f7 in the well layer L4, and figures f8 to f11 in the contact layer L5 Each pattern information is recorded.

  Similarly, cell pattern information for configuring a circuit having a specific function is prepared for the other cells in the lowest layer, but illustration is omitted here. Eventually, in order to obtain the layout pattern of the entire LSI, the individual cell configuration figures illustrated in FIG. 5 are allocated in the individual cells illustrated in FIG. 4A, and the inter-cell wiring illustrated in FIG. The blocks are configured by assigning such blocks to the individual blocks illustrated in FIG. 3A and performing the inter-block wiring illustrated in FIG. 3B.

  As described above, the configuration example of the layout pattern with three layers as shown in FIG. 1 has been schematically described with reference to a plan view. In practice, each information is prepared as data using characters and numerical values. FIG. 7 is a table showing a specific data configuration example corresponding to block arrangement information and inter-block wiring information for “TOP” shown in FIG. As described above, the entity data of the block arrangement information includes, for example, the arrangement coordinates Qa (α1, β1) to Qd (α4) of the reference points such as the lower left corner on the αβ two-dimensional coordinate system for the four blocks A to D. The entity data of the inter-block wiring information is composed of the coordinates of the polygonal vertices P1 to P12 constituting the inter-block wirings W1 to W3.

  FIG. 8 is a table showing a specific data configuration example corresponding to the cell arrangement information and the inter-cell wiring information for “block A” shown in FIG. As described above, the substance data of the cell arrangement information is the arrangement coordinates R1 (X1, Y1) to R3 (X3, X3) of the reference points such as the lower left corner on the XY two-dimensional coordinate system for the three cells C101 to C103. Y3), and the substance data of the inter-cell wiring information is composed of the coordinate values (X, Y) of the polygonal vertices P21 to P30 constituting the inter-cell wirings W4 and W5.

  Further, FIG. 9 is a table showing a specific data configuration example corresponding to the cell pattern information for “cell C101” shown in FIG. As described above, the actual data of the cell pattern information is composed of vertex coordinates of individual figures recorded for each layer. In the table shown in FIG. 9, the vertex coordinates of the graphics f1 to f11 (coordinate values are not shown) are recorded in five layers L1 to L5, respectively.

<<< §2. Main points of the present invention >>
As described above, an LSI layout pattern is an aggregate of many figures. In §1, for the sake of convenience of explanation, a very simple configuration example is shown. However, an actual LSI layout pattern is composed of a collection of very complicated figures, and even if displayed on a display screen, it is intuitive. It is difficult to recognize circuit elements. Therefore, when a layout pattern is displayed on a display screen and a confirmation operation or a verification operation is performed, it is necessary to obtain a circuit diagram of a logic circuit in practice.

  For example, the graphic pattern of the cell C101 shown in FIG. 5 is actually a cell pattern that constitutes an “inverter circuit” as described above, and is expressed in the form shown in FIG. . That is, when a logical value A is given to the input terminal In, the logically inverted output is obtained at the output terminal Out. From the circuit diagram of FIG. 10, it is obvious that the logical element is an “inverter circuit”. However, in order to grasp the graphic pattern shown in FIG. 5 as the “inverter circuit” shown in FIG. Requires skill.

  Moreover, since FIG. 5 shows only the graphic pattern extracted from one cell C101, the recognition of the “inverter circuit” is relatively easy. However, in the actual layout pattern, many cells are used. The huge number of figures that make up the circuit are densely arranged, and the figures that make up the inter-cell wiring and inter-block wiring will also be mixed, so individual circuit elements can be recognized on the actual layout pattern. Is very difficult.

  FIG. 11 is a plan view showing a layout pattern in which six sets of cells C101 of the “inverter circuit” shown in FIG. 5 are arranged and further inter-cell wiring is added. If one looks at the layout pattern shown in FIG. 11 while referring to the cell pattern shown in FIG. 5, six sets of “inverter circuits” can be recognized. On the layout pattern of FIG. 11, the figure f7 (figure of the well layer L4) shown in FIG. 5 is merged into one figure extending in the horizontal direction. This is because at the stage where the cell C101 is arranged in the horizontal direction, the end of the figure f7 overlaps with the end of the figure f7 of another cell adjacent to the left and right, so that they merge with each other on the layout pattern in which the hierarchical structure is developed. It is.

  Similarly, when the figure in the cell and the figure of the inter-cell wiring are layers made of the same material, both are merged. Therefore, the layout pattern shown in FIG. 11 does not have information for dividing the section in units of “cells”, and it is difficult to visually grasp which part corresponds to one cell. is there. Actually, the concept of “cell” is an abstract concept introduced in order to efficiently express the layout pattern of the entire LSI using a hierarchical structure as shown in FIG. 1, and constitutes hardware called LSI. It is not an essential concept above. In other words, there is no physical structure corresponding to the abstract outline “cell” in the hardware structure called LSI, and of course, there is no entity in the layout pattern. A graphic showing the outline of the cell is never displayed.

  However, it is indispensable for an LSI designer to recognize individual circuit elements and their connection relations in order to confirm and verify a layout pattern during design. That is, the layout pattern shown in FIG. 11 is merely a collection of figures, but it is only meaningful for the designer to grasp this pattern as “6 sets of inverter circuits” and “wiring between them”. Analysis can be performed. Therefore, when a circuit designer displays a layout pattern as shown in FIG. 11 on a display screen and performs a confirmation operation or a verification operation, a circuit diagram of a logic circuit corresponding to the layout pattern is also displayed. The work of visually comparing the two is important.

  Of course, since the logic circuit realized by such a layout pattern is originally designed using a circuit diagram, if such a circuit diagram can be obtained, the layout pattern can be obtained with reference to the circuit diagram. It is possible to perform confirmation work and verification work. However, in general, in an LSI manufacturing process, a design department that designs a circuit and a manufacturing department that prints a layout pattern on a semiconductor wafer are often separated organizationally and geographically. In many cases, it is not possible to immediately obtain a circuit diagram from the design department when checking or verifying a layout pattern. Even if a circuit diagram can be obtained, as shown in FIG. 11, in the state where a part of the layout pattern is displayed, it takes a lot of labor to find a part of the circuit diagram corresponding thereto.

  The main point of the present invention is to perform a process of restoring a part of the original circuit diagram from the layout pattern (that is, a collection of a large number of figures) displayed on the display screen as shown in FIG. . Since the circuit diagram is obtained by connecting a plurality of logic elements along the signal flow, in order to restore the circuit diagram, it is also necessary to perform processing for tracing the signal flow on the layout pattern.

  As a method for tracing the flow of signals on a layout pattern, an equipotential tracking method is conventionally known. If this technique is used, for example, among a large number of figures constituting the layout pattern shown in FIG. 11, a figure that is equipotential with respect to a specific figure as a starting point is automatically recognized, and the like with respect to the starting point. It is also possible to display only a region having a potential in a special color. However, this equipotential tracking method basically uses a method of tracing a layer made of a conductive material on a semiconductor wafer, and a layer made of an insulating material is interposed in the middle. If not, signal tracking is not possible.

  For example, in the case of a MOS transistor, a gate insulating film is interposed between the gate electrode and the channel region, and even if the equipotential tracking is performed on the wiring connected to the gate electrode, the channel region leads to the source / drain electrode. It is not possible to track the signal path. Since the circuit diagram is a diagram showing the signal flow between the individual logic circuits, in order to restore the circuit diagram from the layout pattern, a process for recognizing individual elements on the layout pattern is indispensable. Here, a cell on LSI design data is a group of one or a plurality of elements, focusing on their logical functions, and is a great clue for recognizing individual elements. As in the example shown in FIG. 2, the layout pattern developed on the plane is an aggregate of many figures, and the concept of cells has already been lost.

  Therefore, the inventor of the present application first devised a method for recognizing elements in units of individual cells after restoring the concept of cells on the layout pattern. Specifically, in the present invention, first, using the layout pattern data, a cell frame indicating a virtual outline for each cell and a terminal point indicating a virtual connection position between the cell and the external wiring are provided. Define and perform element recognition on a cell basis based on figures and terminal points in individual cell frames, and further, restore the circuit diagram by following the flow of signals between logic elements based on inter-cell wiring The method is taken.

  FIG. 12 is a plan view showing a state in which cell frames and terminal figures according to the present invention are defined in the layout pattern shown in FIG. The frames indicated by bold rectangles in the figure are the cell frames F1 to F6 indicating the virtual outlines of the six sets of cells, and the x marks arranged on the cell frames indicate the virtual connection between each cell and the external wiring. Terminal points T11 to T64 indicating connection positions.

  Of course, the cell frames F1 to F6 and the terminal points T11 to T64 shown in FIG. 12 are not physical structures constituting an actual LSI, nor are substantial figures constituting a layout pattern. These cell frames F1 to F6 and terminal points T11 to T64 are generated as internal parameters of the circuit diagram restoring device, and are not actually displayed on the layout pattern (of course, as necessary. It can also be displayed on a layout pattern on the display screen). Generating such conceptual cell frames and terminal points as internal parameters of the apparatus is convenient for performing element recognition in cell units.

  For example, in FIG. 12, since the wirings W10 to W40 are located outside the cell frames F1 to F6, it can be immediately recognized that they are not constituent elements in the cell but are figures constituting inter-cell wiring. Here, the wirings W10, W20, W30, W40 extending in the horizontal direction in the figure, and the wirings W11-W16, W21-W26, W31-W36 extending in the vertical direction are signals and power lines supplied to each cell, and are small. A white square is a figure showing a contact.

  In addition, since the terminal point T13 on the cell frame F1, the terminal point T41 on the cell frame F4, and the wiring W30 are connected via the wiring W21, if equipotential tracking processing is performed, the terminal along the wiring W21 It can be understood that signal input / output or power supply to the positions of the points T13 and T41 is performed. Furthermore, as will be described later, if the attributes of the input terminal, output terminal, power supply terminal, and ground terminal are recognized for each terminal point, the direction of signal flow can be recognized, and between circuit elements can be recognized. It is also possible to analyze the signal flow in detail.

<<< §3. Basic configuration of apparatus according to the present invention >>
Next, the configuration of the LSI circuit diagram restoring device according to the basic embodiment of the present invention will be described. FIG. 13 is a block diagram showing a device configuration according to this basic embodiment. This device is a device for restoring a circuit diagram of an LSI based on design data indicating the layout pattern of the LSI. This device also has a function of displaying a layout pattern on a display screen based on design data, and can restore and display a circuit diagram in the vicinity of the currently displayed layout pattern in real time.

  As shown in FIG. 13, the display device includes a design data input unit 100, a block configuration data storage unit 200, a cell configuration data storage unit 300, a layout pattern display unit 400, a terminal point determination unit 500, an equipotential tracking unit 550, a cell. The frame determination unit 600, the circuit restoration unit 700, the condition setting unit 800, and the display target designating unit 900 are configured. Actually, this restoration apparatus is configured by incorporating a dedicated program into a computer, and each of the above-described constituent elements is realized as a function of a dedicated program using hardware resources of the computer.

  For example, the block configuration data storage unit 200, the cell configuration data storage unit 300, and the condition setting unit 800 are realized by a storage device such as a hard disk device and a program for causing the storage device to function. 900 is realized by hardware (for example, a keyboard and a mouse) that receives an input operation and an instruction operation from an operator (LSI designer) and a program for causing this to function. In addition, the layout pattern display unit 400, the terminal point determination unit 500, the equipotential tracking unit 550, the cell frame determination unit 600, and the circuit restoration unit 700 perform processing specific to each of hardware such as a CPU, a memory, and a display device. Is realized by the program. Hereinafter, the function of each component will be described in order.

  First, the design data input unit 100 is a component having a function of inputting data to the block configuration data storage unit 200 and the cell configuration data storage unit 300. Specifically, the design data input unit 100 can be configured by an input device such as a keyboard and a mouse and a man-machine interface program that specifies a data file to be input. The data stored in the block configuration data storage unit 200 and the cell configuration data storage unit 300 is the data input by the design data input unit 100.

  The block configuration data storage unit 200 includes, for a block formed by arranging a plurality of cells at predetermined positions, cell placement information indicating the position coordinates of each cell and inter-cell wiring information indicating a figure constituting the inter-cell wiring. It fulfills the function of storing the block configuration data including it. That is, in the example shown in FIG. 1, information indicating the internal structure of the blocks A to D is stored in the block configuration data storage unit 200 as block configuration data. For example, in the case of the block A, information shown in FIGS. 4A and 4B, more specifically, Data (block A) as shown in the table of FIG. 8 is stored.

  If necessary, a layer can be defined for the inter-cell wiring information, and the figures constituting the inter-cell wiring can be recorded for each layer. For example, when a wiring made of polysilicon and a wiring made of metal are shared, two types of layers, a layer L1 (polysilicon) and a layer L3 (metal), are defined, and individual figures constituting inter-cell wiring May be prepared as data belonging to one of the layers.

  On the other hand, the cell configuration data storage unit 300 has a function of storing cell configuration data in which a figure as a component is recorded for each layer for each cell constituting the LSI. That is, in the example shown in FIG. 1, information indicating the internal structure of each cell such as cells C101, C102,... Is stored in the cell configuration data storage unit 300 as cell configuration data. For example, in the case of the cell C101, cell pattern information shown in FIG. 5, more specifically, Data (cell C101) as shown in the table of FIG. 9 is stored.

  As in the example illustrated in FIG. 1, in the case of design data having three layers, information on the highest layer “TOP” is also stored in the block configuration data storage unit 200 as block configuration data. That is, information shown in FIGS. 3A and 3B, more specifically, Data (TOP) as shown in the table of FIG. 7 is also stored in the block configuration data storage unit 200. The highest hierarchy “TOP” is basically one block, and Data (TOP) is also stored in the storage unit 200 as block configuration data. Although not described here, in the case of design data having four or more layers, information (cell pattern information) regarding the lowest layer (cell) is stored in the cell configuration data storage unit 300, and all information regarding the upper layer is stored. It is stored in the block configuration data storage unit 200.

  In general, when handling an LSI layout pattern having a hierarchical structure composed of all n layers (where n ≧ 2), blocks are arranged in the first to (n−1) th layers, Since the cell is arranged in the nth hierarchy (lowest hierarchy), information on the 1st to (n-1) th hierarchy is stored in the block configuration data storage unit 200, and the nth hierarchy Information about the second hierarchy (the lowest hierarchy) is stored in the cell configuration data storage unit 300.

  In this case, the block configuration data for the block belonging to the i-th (1 ≦ i ≦ n−1) layer stored in the block configuration data storage unit 200 is the lower layer if i <n−1. 2 and the inter-block wiring information indicating the figure constituting the inter-block wiring (for example, when n = 3, the layer “TOP” shown in FIG. Information), i = n−1, it is constituted by cell arrangement information indicating the position coordinates of cells belonging to a lower hierarchy and inter-cell wiring information indicating a figure constituting the inter-cell wiring (for example, , N = 3, information on the hierarchy “block” shown in FIG. 2). On the other hand, the cell configuration data storage unit 300 stores cell configuration data in which a figure as a component is recorded for each layer for each cell belonging to the nth layer (FIG. 2). Information of hierarchy “cell” to show).

  The layout pattern display unit 400 draws a layout pattern on a plane based on the block configuration data stored in the block configuration data storage unit 200 and the cell configuration data stored in the cell configuration data storage unit 300. The function of displaying this as an image on the display screen is achieved. Since such a drawing function is a known function, a detailed description of the drawing method is omitted here.

  The functions of the design data input unit 100, the block configuration data storage unit 200, the cell configuration data storage unit 300, and the layout pattern display unit 400 shown in FIG. 13 have been described above. This is an element provided in the layout pattern display device. A feature of the present invention is that, in addition to this general layout pattern display device, a terminal point determination unit 500, an equipotential tracking unit 550, a cell frame determination unit 600, a circuit restoration unit 700, a condition setting unit 800, a display target designation unit 900 is added to configure an LSI circuit diagram restoration apparatus. Hereinafter, the function of each of these components will be described again.

<<< §4. Determination of cell frame and terminal point >>>
Here, functions of terminal point determination unit 500 and cell frame determination unit 600 will be described. Based on the cell frame determination conditions set in the condition setting unit 800, the cell frame determination unit 600 determines a cell frame indicating a virtual contour line of each cell included as a concept in the cell configuration data. The terminal point determination unit 500 has a function of determining a terminal point on the cell frame. As described in §2, the cell frame and terminal point determined here are not substantial figures constituting the layout pattern, but are used internally for the circuit diagram restoration device in order to perform element recognition in units of cells. It is defined as a parameter.

  First, specific contents of the cell frame determination process performed in the cell frame determination unit 600 will be described. The cell frame determination process is performed with reference to cell frame determination conditions set in advance in the condition setting unit 800. Here, the cell frame determination condition is defined by information indicating a specific layer used for cell frame determination among the layers included in the cell configuration data. Cell frame determination conditions to be set in the condition setting unit 800 differ depending on the type of LSI handled by this apparatus. Here, an example of setting the cell frame determination condition will be described by taking as an example a general LSI mainly including circuit elements using CMOS transistors.

  FIG. 5 shows the shapes and arrangements of the graphics f1 to f11 as the cell pattern information of the cell C101. These graphics belong to one of the five layers L1 to L5 as shown in FIG. 6, and are actually defined by graphic data recorded for each layer as shown in FIG. Each of the figures f1 to f11 shown in FIG. 5 is a constituent element of the cell C101, but the figure f7 (the figure constituting the well region for the N-type transistor) is shown in FIG. 11 on the layout pattern. As in the example, it is merged with the figure f7 of another cell adjacent to the left and right to form an elongated integrated figure extending across a plurality of cells arranged in the horizontal direction. This means that the graphic f7 is an inappropriate graphic for use in determining the cell frame (contour) of the unit cell.

  Also, the figures f8 to f11 shown in FIG. 5 are figures showing contacts. In an actual physical LSI, the figures f8 to f11 function as wirings extending in a direction perpendicular to the paper surface in order to electrically connect a plurality of layers. . For this reason, it is understood that the graphics f8 to f11 are graphics that are not useful for determining the cell frame (contour) of the unit cell.

  From this point of view, it can be seen that, for the cell C101 shown in FIG. 5, for example, if a cell frame is determined using the graphics f1 to f6, it is possible to determine an appropriate cell frame. That is, if the distribution region of the figures f1 to f6 is conceptually handled as the inside of the cell C101, an appropriate cell frame can be determined. Therefore, here, among the five layers shown in FIG. 6, three layers L1 (polysilicon), L2 (diffusion layer), and L3 (metal) are selected as specific layers used for determining the cell frame, and the cell Let's assume that it was set as a frame determination condition. The cell C101 shown in FIG. 5 is a cell that functions as an inverter circuit. Similarly, in the case of a general cell including a circuit element using a CMOS transistor, three cell layers L1, L2, and L3 are determined as cell frames. It is reasonable to set it as a condition.

  Therefore, in the apparatus shown in FIG. 13, when handling an LSI including a circuit element using a CMOS transistor, information indicating the three layers L1, L2, and L3 is sent to the condition setting unit 800 as a cell frame determination condition. Set as. These three layers are handled as extraction target layers in the cell frame determination process executed by the cell frame determination unit 600.

  That is, the cell frame determination unit 600 reads the cell configuration data from the cell configuration data storage unit 300 for each cell that is the target of the cell frame determination, and selects a specific layer (in the above example) set as the cell frame determination condition. In this case, the figure recorded in the three layers L1, L2, and L3) used for determining the cell frame is extracted, a logical sum figure of the extracted figure is formed, and the circumscribed figure of the logical sum figure is used as the cell frame. Execute the requested process.

  For example, for the cell C101, the cell frame determination unit 600 reads the cell configuration data (Data (cell C101)) shown in FIG. 9 from the cell configuration data storage unit 300. The graphics f1 to f6 recorded in the three layers L1, L2, and L3 are extracted. FIG. 14 is a plan view showing a group of figures extracted in this way. Then, the cell frame determination unit 600 performs processing for obtaining a graphic f (OR) as shown by hatching in FIG. 15 as a logical sum of these extracted graphics f1 to f6. The logical sum figure f (OR) indicates a conceptual area to be grasped as the internal area of the cell C101.

  Therefore, the cell frame determination unit 600 further executes processing for obtaining a circumscribed graphic of the logical OR graphic f (OR) as a cell frame. A cell frame F indicated by a bold line in FIG. 16 is a circumscribed figure obtained in this way, and shows a conceptual outline of the cell C101. In the example shown here, a circumscribed rectangle is used as the circumscribed figure. 17 is a plan view showing a state in which the cell frame F shown in FIG. 16 is superimposed on the layout pattern of the cell C101 shown in FIG. Since the layer L4 (well) is removed as the cell frame determination condition, the figure f7 is in a state of protruding from the cell frame F. As described above, the figure f7 is merged with the figure f7 of another cell adjacent to the left and right. There is no problem even if the cell frame F is straddled to form the layout pattern. Thus, the cell frame determination unit 600 can determine an appropriate cell frame.

  Note that the cell configuration data stored in the cell configuration data storage unit 300 is usually from a polygon formed by sides parallel to the x axis or y axis in the xy coordinate system, as in the example shown in FIG. It becomes the data which recorded the figure which becomes. In such a case, it is preferable that the circumscribed figure determined as the cell frame by the cell frame determining unit 600 is a regular circumscribed rectangle composed of sides parallel to the x axis or the y axis. The cell frame F shown in FIG. 16 constitutes a regular circumscribed rectangle for the logical sum figure f (OR), and the upper and lower sides are parallel to the x-axis and the left and right sides are parallel to the y-axis. When the figure constituting the cell is a figure made of a polygon constituted by sides parallel to the x-axis or y-axis, the cell frame is also constituted by a regular circumscribed rectangle constituted by sides parallel to the x-axis or y-axis. On the other hand, as seen in the example shown in FIG. 12, a cell frame having a simple shape suitable for arrangement on the layout pattern can be obtained.

  Note that the cell frame determination condition to be set in order to determine an appropriate cell frame is not necessarily determined as one, and various conditions that are considered appropriate are set according to the judgment of the operator (designer). It is possible. For example, in the above example, the information indicating the three layers L1, L2, and L3 is set as the cell frame determination condition, but the information indicating the four layers added with the layer L5 (contact) is further set as the cell frame determination condition. The same result can be obtained even if set as. Alternatively, in the above example, the same result can be obtained even if information indicating only the two layers L1 and L2 is set as the cell frame determination condition.

  Of course, there are cases where the shape and position of the obtained cell frame will change if the setting content of the cell frame determination condition changes, but since there is no `` correct cell frame '' in the first place, setting the cell frame determination condition Therefore, there is no problem even if the defined cell frame changes. As described above, in the present invention, the role of the cell frame F is to define a conceptual cell boundary position on the layout pattern, and to determine the terminal point described later. There is no problem if a cell frame is defined at a position indicating the rough cell area.

  Next, the specific content of the terminal point determination process performed in the terminal point determination part 500 is demonstrated. The terminal point determination unit 500 executes processing for generating terminal points on the cell frame F determined by the cell frame determination unit 600. For this purpose, the inter-cell wiring information stored in the block configuration data storage unit 200 is used. Here, for the cell C101 in the block A, specific processing for generating terminal points will be described by taking as an example the case where a cell frame F as shown in FIG. 17 is determined. The inter-cell wiring information in the block A indicates inter-cell wiring for a plurality of cells included in the block A as shown in FIG.

  Here, as such inter-cell wiring for the cell C101, it is assumed that graphic data indicating four wirings w1 to w4 as indicated by broken lines in FIG. 18 are recorded as inter-cell wiring information in the block A. . The inter-cell wiring is a wiring for electrically connecting a component in one cell and a component in another cell. The inter-cell wiring figure has an end portion in the cell. It is arranged so as to overlap the figure. Also in the example shown in FIG. 18, the ends of the wirings w1 to w4 are partially overlapped with the graphic in the cell. For this reason, the inter-cell wirings w1 to w4 for the cell C101 can be recognized as a figure intersecting the cell frame F.

  The terminal point determination unit 500 recognizes an intersection line segment in which the cell frame is cut out by the intersection pattern among the shapes included in the inter-cell wiring information and intersects with the cell frame, and one point on the intersection line segment. The terminal point is determined. FIG. 19 is a plan view showing a state in which terminal points T1 to T4 (points with X marks) are determined at the intersection positions of the cell frame F and the inter-cell wires w1 to w4. First, with respect to the cross graphic (inter-cell wiring w1 to w4) that intersects with the cell frame F, cross line segments H1 to H4 obtained by cutting the cell frame F with the cross graphic are recognized. Subsequently, terminal points T1 to T4 are determined at one point on each intersection line segment H1 to H4 (in the case of the embodiment shown here, the middle point of each intersection line segment). Actually, the coordinate values of the terminal points T1 to T4 are obtained by this terminal point determination process.

  FIG. 20 is a plan view showing a state in which the cell frame F and the terminal points T1 to T4 are arranged on the layout pattern including the periphery of the cell C101 shown in FIG. On the layout pattern, the hierarchical structure is expanded, and among the figures in the cell pattern information and the figures in the inter-cell wiring information, figures belonging to layers made of the same material form a fused pattern. In the example shown in FIG. 20 as well, the figures f4 and w1, the figures f1 and w2, the figures f5 and w3, and the figures f6 and w4 are figures belonging to layers made of the same material. A structured pattern figure is formed.

  A cell frame F shown by a bold line in FIG. 20 is the cell frame F shown in FIG. 17, and the four terminal points T1 to T4 shown in FIG. 20 are terminals determined by the procedure shown in FIG. Is a point. When such a cell frame F and terminal points T1 to T4 are obtained, it is possible to recognize the correspondence between each terminal on the logic circuit symbol constituting the circuit diagram and a specific position on the layout pattern.

  As described above, the logic circuit having the layout pattern shown in FIG. 20 is a circuit constituting the inverter circuit, and is represented by the logic circuit symbol shown in FIG. 21 on the circuit diagram. Here, the terminal In is an input terminal, the terminal Out is an output terminal, the terminal Vdd is a power supply terminal, and the terminal Gnd is a ground terminal. As described later in detail, in the present invention, element recognition in the cell is performed using information on the terminal points defined on the cell frame, so that each terminal point on the layout pattern and the logic circuit on the circuit diagram It is possible to associate the symbol with each terminal.

  For example, in the inverter circuit shown in FIG. 21, it can be recognized that the input terminal In corresponds to the terminal point T2 on the layout pattern shown in FIG. Similarly, it can be recognized that the output terminal Out corresponds to the terminal point T4, the power supply terminal Vdd corresponds to the terminal point T1, and the ground terminal Gnd corresponds to the terminal point T3 (details will be described later). In particular, the fact that the input terminal In and the output terminal Out can be recognized is important in tracing the signal flow. That is, in the circuit diagram shown in FIG. 21, the signal that has entered the input terminal In is output from the output terminal Out and transmitted to the logic circuit of the next stage. 20 can be recognized on the layout pattern shown in FIG.

  That is, in FIG. 20, since the input terminal In is the terminal point T2 and the output terminal Out is the terminal point T4, the signal transmitted through the inter-cell wiring w2 enters the logic circuit in the cell frame F, and between the cells. It can be recognized on the layout pattern that it is transmitted to the next-stage logic circuit through the wiring w4. Thus, the signal can be traced on the layout pattern displayed on the display screen. For example, the signal is traced downstream by three stages starting from the inverter circuit shown in FIG. It is also possible to recognize adjacent cells and restore a circuit diagram for only these adjacent cells.

  In the above-described example, the inter-cell wiring connecting the cells is described to perform the process of determining the intersection with the cell frame and generating the terminal point, but the block connecting the blocks to each other In the case where there is a possibility that the inter-wiring is connected to the constituent elements in the cell, the inter-block wiring may be determined by determining the intersection with the cell frame and determining the terminal point. That is, the terminal point determination unit 500 may determine the terminal points for the graphic included in the inter-block wiring information together with the terminal points for the graphic included in the inter-cell wiring information.

<<< §5. Equipotential tracking process >>>
Here, the equipotential tracking process performed by the equipotential tracking unit 550 will be described. The equipotential tracking unit 550 has a function of performing equipotential tracking processing for recognizing another figure having an equipotential as an equipotential figure with respect to a specific target figure constituting the layout pattern. In the case of the apparatus shown in FIG. 13, the result of the equipotential tracking process by the equipotential tracking unit 550 is used by the terminal point determination unit 500 and the circuit restoration unit 700. The terminal point determination unit 500 and the circuit restoration unit 700 designate a specific figure on the layout pattern as a target figure as necessary, and give an equipotential tracking instruction to the equipotential tracking unit 550.

  When the equipotential tracking unit 550 receives such an equipotential tracking instruction, the equipotential tracking unit 550 is a figure that becomes equipotential with respect to the designated figure of interest based on the equipotential tracking condition set in the condition setting unit 800. Is performed as an equipotential figure. In the condition setting unit 800, an equipotential tracking condition indicating a requirement that a plurality of figures included in the cell configuration data and the block configuration data become equipotential with each other is set in advance. Specifically, information indicating the conductive layer among the layers included in the cell configuration data and the block configuration data may be set in advance as an equipotential tracking condition. For example, when a metal layer is set as a conductive layer, if a figure belonging to the metal layer is designated as a target figure, a group of figures belonging to the metal layer and connected to the target figure is recognized as an equipotential figure. become.

  However, in general LSIs including CMOS transistors, a plurality of conductive layers are often used. In such a case, information indicating a contact layer including a figure indicating a contact for connecting the plurality of layers is set as the equipotential tracking condition together with information indicating the plurality of conductive layers. For example, when five layers as shown in FIG. 6 are defined, the equipotential tracking condition in which the layer L1 (polysilicon) and the layer L3 (metal) are conductive layers and the layer L5 (contact) is a contact layer. Should be set.

  Actually, identification codes such as L1, L2,... Are attached to each layer as illustrated in FIG. In this case, for the pattern in the cell, the inter-cell wiring, and the inter-block wiring, the same identification code is attached to the layers composed of the same material (if necessary, the layers are composed of the same material) Different types of identification codes are attached to the layers, and the layers may be distinguished, for example, as a metal 1 layer / metal 2 layer).

  In this way, cell configuration data storing a graphic as a component for each layer to which a predetermined identification code is attached is stored in the cell configuration data storage unit 300, and the block configuration data storage unit 200 stores a predetermined configuration code. For each layer to which the identification code is attached, wiring information including figures constituting the inter-cell wiring or inter-block wiring is stored, and the condition setting unit 800 includes the information indicating the conductive layer as an equipotential tracking condition. If the information indicating the contact layer including the graphic indicating the contact for connecting the plurality of layers is set, the equipotential tracking unit 550 recognizes the equipotential graphic based on the following criteria. be able to.

  First, when the figures belonging to a plurality of conductive layers with the same identification code are superimposed in a plane, it can be recognized that the superimposed figure is equipotential. For example, when the intra-cell graphic belonging to the layer L1 (polysilicon) and the inter-cell wiring graphic belonging to the layer L1 (polysilicon) overlap in a plane, these figures merge on the layout pattern. Therefore, it can be determined that both are equipotential. On the other hand, when figures belonging to multiple conductive layers with different identification codes are superimposed in a plane, the superimposed figure only if the figure belonging to the contact layer exists in the overlap area Can be recognized as being equipotential. This is because different layers are three-dimensionally separated from each other even if they are overlapped in a plane, so that they can be determined to be equipotential only if they are connected via contacts. It is. For example, when a figure belonging to the layer L1 (polysilicon) and a figure belonging to the layer L3 (metal) overlap in a plane, only when a figure belonging to the layer L5 (contact) exists in the overlapping region, It will be recognized that both are equipotential.

  When three or more figures belonging to different layers overlap in a plane and a contact is arranged in the overlapping area, the contact is usually a predetermined one of the three or more overlapping figures. In many cases, only two figures are connected. In such a case, in the condition setting unit 800, priority is set for a combination of a pair of conductive layers having different identification codes as equipotential tracking conditions, and the equipotential tracking unit 550 is set. However, when a figure belonging to three or more layers with different identification codes is superimposed in a planar manner and a figure belonging to a contact layer is present in the overlap region, a pair of It is only necessary to recognize that only the superimposed figures belonging to the layer are connected.

  FIG. 22 is a diagram illustrating an example of setting equipotential tracking conditions in consideration of such priorities. First, in condition (a), layer L1 (polysilicon) and layer L3 (metal) are set as information indicating the conductive layer. In the condition (b), the layer L5 (contact) is set as information indicating the contact layer. The condition (c) includes, as information indicating the priority of contacts, the first priority “L3 (metal) and L1 (polysilicon)” and the second priority “L3 (metal) and L2 (diffusion layer). "Is set.

  The information indicating the priority set as the condition (c) is based on the layer structure shown in FIG. FIG. 23 is a cross-sectional view of a physical layer structure, in which L3 (metal), L1 (polysilicon), and L2 (diffusion layer) are stacked in this order from the top. Actually, an insulating layer is formed in the space shown between the layers. The substance of the contacts C1 and C2 is a wiring made of a conductive material filled in a contact hole formed in the insulating layer. Assuming the structure as shown in the figure, when the layer L1 (polysilicon) is present below the layer L3 (metal), “L3 (metal) and L1 (polysilicon)” are formed by the contacts as in the contact C1. And will be connected. The first priority of the contact indicates a pair of layers connected in such a case. On the other hand, when the layer L1 (polysilicon) does not exist below the layer L3 (metal) and the layer L2 (diffusion layer) exists, “L3 (metal) and L2 (diffusion) are caused by the contact like the contact C2. Layer) ”. The second priority of the contact indicates a pair of layers connected in such a case.

  In the example shown here, since the layer L2 (diffusion layer) is not a conductive layer, in FIG. 23, part of the layer L2 (diffusion layer) and part of the layer L3 (metal) are connected by the contact C2. Even so, the entire layer L2 (diffusion layer) is not equipotential to the layer L3 (metal). However, since the lower end portion of the contact is equipotential with the layer L3 (metal), is the lower end of the contact connected to the layer L2 (diffusion layer) (in the case of the contact C2 in FIG. 23) or is connected? It is necessary to distinguish whether it is present (in the case of the contact C1 of FIG. 23) in performing element recognition processing described later. In this respect, the priority order of the condition (c) shown in FIG. 22 plays an important role.

  FIG. 24 is a plan view showing a simple layout pattern for explaining specific processing by the equipotential tracking unit 550. In this example, a plurality of figures belonging to four types of layers of L1 (polysilicon), L2 (diffusion layer), L3 (metal), and L5 (contact) are shown. Here, it is assumed that conditions (a), (b), and (c) as shown in FIG. 22 are set in the condition setting unit 800 as equipotential tracking conditions. Consider a case where an equipotential tracking instruction is given to the equipotential tracking unit 550 with the figure fz (L3 (metal)) shown in the upper right as a target figure.

  According to the equipotential tracking condition shown in FIG. 22, since the conductive layers are L1 and L3, the figure belongs to the layer L1 or L3 and is directly or indirectly connected to the target figure fz. The group will be recognized as an equipotential figure. As a result, the figure shown by hatching in FIG. 25 is recognized as the figure of interest and its equipotential figure. In this example, the four hatched rectangles are connected by three contacts. Note that, according to the condition (c) shown in FIG. 22, the central contact is recognized as a contact connecting L1 (polysilicon) and L3 (metal), and is not a contact connecting to L2 (diffusion layer). Is made.

<<< §6. Exclusion process of passing wiring >>>
Here, a process of excluding a wiring that simply passes through a cell using the above-described equipotential tracking process when the terminal point determination unit 500 determines a terminal point will be described.

  In §4, the procedure of terminal point determination processing by the terminal point determination unit 500 will be described based on the examples shown in FIGS. 18 and 19, and four terminal points T1 to T4 as illustrated in FIG. 20 are obtained. I explained that. In the example shown in FIG. 20, the four terminal points T1 to T4 all indicate appropriate terminals for inputting / outputting signals or supplying power to the cell C101.

  However, the wiring that intersects the cell frame is not necessarily a wiring for the cell, and may be a wiring that simply passes through the cell. For example, FIG. 26 shows three cells C11, C12, C13 arranged in the horizontal direction and two inter-cell wirings w12, w13. Here, it is assumed that the wiring w12 is a wiring for the internal element of the cell C12, and the wiring w13 is a wiring for the internal element of the cell C13. That is, the wiring w12 crosses the cell frame F11, but is not connected to any internal element of the cell C11, and merely crosses the cell C11. Similarly, the wiring w13 crosses the cell frames F11 and F12, but is not connected to any internal element of the cells C11 and C12, and simply crosses the cells C11 and C12.

  As described above, when there is a wiring that simply passes through the cell, if the terminal point determination unit 500 performs the terminal point determination processing using the algorithm described in §4, an inappropriate terminal point is generated. That is, in the example shown in FIG. 26, the terminal points T11 to T18 are defined at the intersections between the figures constituting the wirings w12 and w13 and the cell frames F11, F12, and F13. However, the illustrated terminal points T11 to T14, T16, and T17 are terminal points that are simply generated by intersections with the wirings that pass through the cells, and are not intended to be terminal points.

  In order to prevent the generation of such unnecessary terminal points, the terminal point determination unit 500 gives an equipotential tracking instruction to the equipotential tracking unit 550 with each intersecting figure intersecting the cell frame as a target figure, and Of these, it is only necessary to recognize the intersection line segment only for the intersecting figure in which any figure recorded in the cell configuration data corresponding to the cell frame becomes an equipotential figure.

  For example, in the example shown in FIG. 26, when the terminal point determination unit 500 determines the terminal point for the cell C11, the equipotential tracking unit 550 is instructed to perform equipotential tracking instruction to the equipotential tracking unit 550 using the figure constituting the wiring w12 as the target figure. give. As a result, since a figure that becomes an equipotential figure with respect to the figure of interest is not found in the cell C11, the intersection line segment of the wiring w12 is not recognized, and the terminal points T11 and T13 shown in the figure do not occur. Become. A similar result can be obtained by the equipotential tracking process using the figure constituting the wiring w13 as the figure of interest, so that the crossing line segment is not recognized for the wiring w13, and the terminal points T12 and T14 shown in the figure do not occur. Become.

  On the other hand, when the terminal point determination unit 500 determines the terminal point for the cell C12, if the equipotential tracking unit 550 is given an equipotential tracking instruction with the figure constituting the wiring w12 as the target figure, any of the cells in the cell C12 will be displayed. Since such a figure is discovered as an equipotential figure, the intersection line segment for the wiring w12 is recognized as usual, and the terminal point T15 shown in the figure is generated. On the other hand, in the equipotential tracking process in which the figure constituting the wiring w13 is the figure of interest, no equipotential figure is found, so the crossing line segment is not recognized for the wiring w13, and the illustrated terminal points T16 and T17 are shown. Will not occur.

  In addition, when the terminal point determination unit 500 generates a terminal point for the cell C13, if the equipotential tracking unit 550 is given an equipotential tracking instruction using the figure constituting the wiring w13 as a target figure, any of the cells in the cell C13 is displayed. Since such a figure is found as an equipotential figure, the intersection line segment for the wiring w13 is recognized as usual, and the terminal point T18 shown in the figure is generated.

  Thus, in the case of the example shown in FIG. 26, terminal points are generated only at the positions of terminal points T15 and T18, which are positions where terminal points should be generated, and generation of useless terminal points can be prevented.

  FIG. 27 is a plan view showing the handling of the inter-cell wiring w5 that passes through the cell C101 shown in FIG. In the case of this example, since the inter-cell wirings w1 to w4 are all connected to any graphic in the cell, any of the inter-cell wirings in the cell is performed by the equipotential tracking process using the inter-cell wiring as the target graphic. The figure will be found as an equipotential figure. Therefore, terminal points T1 to T4 are generated as usual. In contrast, the inter-cell wiring w5 (which belongs to a layer having an identification code different from the layer to which each figure in the cell belongs) is not connected to any figure in the cell, Even if the equipotential tracking process using the inter-cell wiring w5 as the target graphic is performed, the equipotential graphic is not found in the cell. Therefore, the terminal points T5 and T6 shown in the figure do not actually occur, and useless terminal points are not generated at these positions.

<<< §7. Region and element recognition and circuit restoration processing >>>
Here, the function of the circuit restoration unit 700 in the apparatus shown in FIG. 13 will be described. As illustrated, the circuit restoration unit 700 includes three components, that is, a region recognition unit 710, an element recognition unit 720, and a circuit diagram display unit 730, whose role is a display target designated by the display target designation unit 900. The circuit is to display the circuit diagram on the display screen. For this purpose, the circuit restoration unit 700 has a function of reading out necessary block configuration data from the block configuration data storage unit 200 and reading out necessary cell configuration data from the cell configuration data storage unit 300. Further, if necessary, an equipotential tracking instruction is given to the equipotential tracking unit 550 to recognize an equipotential figure that is equipotential to the figure of interest.

  On the other hand, in the condition setting unit 800, region recognition conditions and element recognition conditions are set in advance. Here, the region recognition condition is a condition for performing region recognition based on the graphic included in the cell configuration data, and the region recognition unit 710 determines whether or not the predetermined recognition target cell is based on the region recognition condition. For the graphic included in the cell configuration data, the function of recognizing the individual element configuration areas constituting the element is fulfilled. The element recognition condition is a condition for recognizing a specific element based on the connection relationship between a plurality of regions and terminal points. The element recognition unit 720 includes a plurality of element configuration regions recognized by the region recognition unit 710 and In the condition setting unit 800, the connection relationship between the terminal points determined by the terminal point determination unit 500 is handled as if the figures recognized as being equipotential to each other by the equipotential tracking unit 550 as being electrically connected. A function of recognizing the element corresponding to the recognition target cell is achieved by collating with the element recognition condition.

  As will be described later, when handling a logic element including a MOS transistor, the condition setting unit 800 recognizes a region recognition condition for recognizing a channel region, a gate region, and a source / drain region, a channel region, a gate region, and a source. The element recognition conditions for recognizing the logic element including the MOS transistor may be set based on the mutual connection relationship between the drain regions and the connection relationship between these and the terminal points.

  FIG. 28 is a diagram illustrating a relationship between a circuit diagram of a general MOS transistor and an element configuration region. The element configuration region forming the center of the MOS transistor is a channel region. In the case of a P-type MOS transistor, a P-type channel region is formed, and in the case of an N-type MOS transistor, an N-type channel region is formed. In the circuit diagram of FIG. 28, the center portion described as “P or N” among the symbols indicating the transistors corresponds to the channel region. On the other hand, the portion described as “G” in the figure is a gate region, and the two portions described as “SD” in the drawing are source / drain regions. Actually, two portions described as “SD” are one of a source region and the other a drain region, but the source / drain are interchangeable, and depending on the mounting state in the LSI, which is the source and which is which Since it is determined whether to become a drain, both are treated as a source / drain region without distinction here.

  In FIG. 28, for the sake of convenience, each part of the circuit diagram of the MOS transistor has been described by associating four element configuration regions, that is, a channel region, a gate region, and two source / drain regions. It corresponds to a region actually formed in a physical LSI, and can be defined as a combination of specific layers on a layout pattern.

  The area recognition condition set in the condition setting unit 800 can be said to be a condition in which each element configuration area is defined as a combination of such specific layers. FIG. 29 is a diagram illustrating an example of region recognition conditions set for an element formed of a CMOS circuit (a combination circuit of a P-type MOS transistor and an N-type MOS transistor). In this example, first, as the channel region P of the P-type MOS transistor, “L1 and L2 and L4 bar” (in the specification of the electronic application, the bar to be attached to the upper part of the symbol is “bar” after the symbol. The recognition condition “L1 and L2 and L4” is set as the channel region N of the N-type MOS transistor. Here, L1, L2, and L4 indicate figures belonging to each layer shown in FIG. 6, “and” indicates a logical product of figures belonging to each layer, and “L4 bar” indicates It shows that there is no figure belonging to the layer L4. Further, the recognition condition “L1 including the channel region” is set as the gate region G, and the recognition condition “L2 including the channel region” is set as the source / drain region SD.

  FIG. 30 is a plan view showing a result of region recognition performed by the region recognition unit 710 on the cells shown in FIG. 20 based on the region recognition conditions shown in FIG. A square area P shown by hatching is a logical product area of the figures f1 and f2, and is recognized as the channel area P of the P-type MOS transistor based on the condition described in the first line of FIG. It will be. That is, the square area P is a logical product area of the figure f1 belonging to the layer L1 and the figure f2 belonging to the layer L2, and the figure f7 belonging to the layer L4 does not exist. “L1andL2andL4” Satisfies the “bar” condition.

  A square area N shown by hatching is a logical product area of the figures f1 and f3, and is recognized as a channel area N of the N-type MOS transistor based on the condition described in the second line of FIG. Will be. That is, the square area N is a logical product area of the figure f1 belonging to the layer L1, the figure f3 belonging to the layer L2, and the figure f7 belonging to the layer L4, and satisfies the condition “L1 and L2 and L4”. ing.

  Thus, when the recognition of the channel regions P and N is completed, the region of the graphic belonging to the layer L1 including these channel regions P and N is recognized as the gate region G (condition described in the third line in FIG. 29), A region of a figure belonging to the layer L2 including the channel regions P and N is recognized as the source / drain region SD (condition described in the fourth line in FIG. 29). Specifically, in FIG. 30, the graphic f1 is recognized as the gate region G, and the graphic f2 and f3 are recognized as the source / drain region SD. The gate region G and the source / drain region SD partially include a channel region.

  The area recognition condition shown in FIG. 29 is, as a result, a rule (recognition condition described in the first and second lines) that associates a logical product area of figures belonging to different layers with a specific element configuration area, It is configured by a rule (recognition condition described in the third and fourth lines) that associates a graphic area that belongs to a specific layer and includes a recognized specific element configuration area with a specific element configuration area. It will be.

  In this way, if the element constituent regions of the MOS transistors can be recognized, it is possible to recognize the mutual connection relationship between each region and each terminal point by using the equipotential tracking processing by the equipotential tracking unit 550. Become. Specifically, in the cell pattern shown in FIG. 30, the terminal point T1 is connected to the graphic f2 (that is, the source / drain region SD) via the graphic f4, and the terminal point T2 is connected to the graphic f1 (that is, the gate region G). The terminal point T3 is connected to the figure f3 (that is, the source / drain region SD) via the figure f5, and the terminal point T4 is connected to the figures f2 and f3 (ie, the source / drain area via the figures w4 and f6). SD) can be recognized.

  FIG. 31 is a plan view showing a connection relationship between each of the terminal points T1 to T4 and each of the element constituent regions in the cell shown in FIG. Since it can also be recognized that the channel region P and the channel region N are connected as a result of the equipotential tracking process, each element between the channel region P and the channel region N and each of the terminal points T1 to T4 is eventually found. It can be recognized that there is a connection relationship drawn by a thick line through the configuration area. If this connection relation is collated with the connection relation shown in FIG. 28, it can be recognized that the upper half in the cell shown in FIG. 31 is a P-type MOS transistor circuit and the lower half is an N-type MOS transistor circuit. The terminal point T1 is a source / drain terminal of the P-type MOS transistor circuit, the terminal point T2 is a common gate terminal for the P-type MOS transistor circuit and the N-type MOS transistor circuit, and the terminal point T3 is a source of the N-type MOS transistor circuit. The drain terminal and terminal point T4 can recognize the correspondence relationship between the common source / drain terminal of the P-type MOS transistor circuit and the N-type MOS transistor circuit.

  In this way, the element recognition unit 720 performs processing for recognizing elements in units of cells based on the mutual connection relationship between the element configuration region recognized by the region recognition unit 710 and the terminal point determined by the terminal point determination unit 500. . For this purpose, a rule indicating the mutual connection relation between a plurality of element configuration regions and terminal points constituting the element is set as an element recognition condition for each of a plurality of candidate elements in the condition setting unit 800. Just keep it.

  FIG. 32 is a diagram illustrating an example of element recognition conditions set in the condition setting unit 800. Here, rules indicating the mutual connection relationship between element configuration regions and terminal points constituting the element are shown for three candidate elements (elements corresponding to one cell). 32A is a rule for an inverter circuit, FIG. 32B is a rule for a NAND circuit, and FIG. 32C is a rule for a NOR circuit. Here, for convenience of explanation, each connection rule is shown in a transistor level circuit diagram (in parentheses on the right side, and a logic circuit symbol is written), but the actual element recognition conditions are between specific areas. It is set as a rule (so-called net list) indicating a connection relationship.

  For example, in the case of the inverter circuit shown in FIG. 32A, in the upper half, “first source / drain region SD”, “second source / drain region SD”, “channel region P”, A P-type MOS transistor (PMOS) to which the “gate region G” is connected is configured, and in the lower half, the “first source / drain region SD” and the “second source” with respect to the “channel region N”. An N-type MOS transistor (NMOS) in which the drain region SD and the gate region G are connected is configured, and the “gate region G” of both transistors is connected to the input terminal “In” of the cell and the PMOS “ A power source Vdd is connected to the “first source / drain region SD”, a ground potential Gnd is connected to the “second source / drain region SD” of NMOS, and a “second source / drain of PMOS” is connected. A rule indicating a specific connection relationship that the region SD ”and the NMOS“ first source / drain region SD ”are connected to the output terminal“ Out ”of the cell is set as an element recognition condition.

  As described above, the element recognizing unit 720 assumes that the regions recognized as being equipotential to each other by the equipotential tracking unit 550 are electrically connected, and determines the connection relationship between the element constituent regions in each cell frame. recognize. For example, in the case of the example of the cell C101 shown in FIG. 31, it can be recognized that there is a connection relationship as shown by a bold line in the drawing between each region and each terminal point as described above. FIG. 33 is a diagram obtained by extracting the connection relationship between each region and each terminal point thus recognized and rewriting them in correspondence with the transistor level circuit diagram. Considering that the area recognition as described above has been performed on the layout pattern shown in FIG. 31, it can be easily understood that the connection relationship shown in FIG. 33 can be extracted from this layout pattern. The element recognizing unit 720 sets the connection relationship as shown in FIG. 33 (the mutual connection relationship between the element configuration region and the terminal point recognized from the actual pattern in the cell frame) to each individual element shown in FIG. A process of collating each of the connection relations set for (three elements in this example) is performed. If there is an element that matches the connection relationship, the circuit in the cell is recognized as the element.

  In the case of the above example, the connection relationship shown in FIG. 33 matches the inverter circuit shown in FIG. 32 (a) by checking the connection relationship shown in FIGS. 32 (a), (b) and (c). I understand that. Therefore, the cell C101 shown in FIG. 31 is recognized as an inverter circuit element by the element recognition unit 720. Moreover, if the connection relationship of FIG. 33 is compared with the connection relationship of FIG. 32A, the terminal point T1 corresponds to the power supply terminal “Vdd”, the terminal point T2 corresponds to the input terminal “In”, and the terminal point Since T3 corresponds to the ground terminal “Gnd” and the terminal point T4 corresponds to the output terminal “Out”, the circuit diagram shown in FIG. 21 can be restored based on the layout pattern shown in FIG. it can. Terminals T1 to T4 in this circuit diagram correspond to terminal points T1 to T4 defined on the layout pattern shown in FIG.

  The circuit diagram display unit 730 associates the element thus recognized by the element recognition unit 720 with the logic circuit symbol, and associates the inter-cell wiring information (or inter-block wiring information) with the connection between the logic circuit symbols. A logic circuit diagram for the circuit is created, and this is displayed as an image on the display screen. That is, the layout pattern shown in FIG. 31 may be associated with the logic circuit symbol “inverter circuit” shown in FIG. 21 and displayed on the circuit diagram. However, in the logic circuit diagram, it is usually not necessary to display the power supply terminal Vdd and the ground terminal Gnd. Therefore, in practice, it is sufficient to display a logic circuit symbol in which only the input terminal In and the output terminal Out are displayed. .

  The example in which element recognition is performed based on the layout pattern in one cell to be recognized and one logic circuit symbol is displayed has been described above. In the present invention, the input / output attributes of terminal points on the layout pattern are described. Therefore, it is possible to perform signal tracking processing that follows the signal flow on the layout pattern, and the circuit diagram display unit 730 follows the signal flow based on the result of the signal tracking processing. A circuit diagram for a specific cell can be created and displayed.

  FIG. 34 is a plan view showing terminal attributes recognized for individual terminal points with different graphics for the purpose of explanation. That is, in this example, four terminal points are displayed on the cell frame F, but the upper left terminal point (terminal point T1 in FIG. 31) is a white square indicating the power supply terminal “Vdd”. The upper right terminal point (terminal point T2 in FIG. 31) is a white triangle indicating the input terminal “In”, and the lower left terminal point (terminal point T3 in FIG. 31) is the ground terminal “Gnd”. The white circle and the lower right terminal point (terminal point T4 in FIG. 31) are respectively shown by white diamonds indicating the output terminal “Out”. Of course, in practice, the difference in the terminal attributes is recognized as a difference in some identification code in the element recognition unit 720.

  In the case of the example shown in FIG. 34, since the terminal point T2 indicated by the white triangle is the input terminal “In”, the inter-cell wiring w2 connected to the terminal point T2 is an input signal line. Since the terminal point T4 shown is the output terminal “Out”, the inter-cell wiring w4 connected thereto is an output signal line. Since the input / output signal line can be specified by using the input / output attribute of the terminal point in this way, the logic element in the preceding stage starts from this logic element, and traces the input signal line w2 upstream. The logic element in the subsequent stage can be specified by tracing the output signal line w4 downstream. Of course, the equipotential tracking process by the equipotential tracking unit 550 may be used for the process of tracing the wiring between cells.

  As described above, in tracing the logic element along the signal flow, it is only necessary to identify the terminal points having the attributes of the input terminal In and the output terminal Out. Therefore, the condition setting unit 800 includes the input terminal In and the output terminal Out. An element recognition condition for recognizing a specific element may be set based on a connection relationship including terminal points having at least two types of attributes. In the element recognition condition illustrated in FIG. 32, a connection relationship including terminal points having a total of four types of attributes including the power supply terminal Vdd and the ground terminal Gnd is defined. However, the element recognition condition relates to the power supply terminal Vdd and the ground terminal Gnd. The connection relationship may be omitted.

  If the element recognition unit 720 can perform at least two types of attribute recognition of the terminal point of each cell, that is, the input terminal In and the output terminal Out, the circuit diagram display unit 730 determines that n is determined from a predetermined starting point on the layout pattern. With the tracking range traced upstream or downstream by the cells of the stage as a display target circuit, the corresponding circuit diagram can be restored and displayed. For example, the circuit diagram display unit 730 performs circuit restoration display using a range traced downstream by n cells as a display target circuit from a predetermined starting point on the currently displayed layout pattern. When the instruction is given, the circuit diagram display unit 730 executes an inter-cell signal tracking process that tracks n stages of cells downstream from the starting point in consideration of the input / output attribute of the terminal point of each cell. Only the circuit diagram of the range can be extracted and displayed.

  FIG. 35 is a plan view for explaining the concept of such inter-cell signal tracking processing. In this example, for the sake of convenience, cell frames FF1 to FF6 for showing six cells CC1 to CC6 and a part of inter-cell wiring (wa to we) for connecting these cells to each other are shown ( Power supply wiring is not shown). In addition, the white figure drawn on each cell frame FF1-FF6 has shown the terminal point, and the shape has shown the attribute of the terminal point similarly to the example of FIG. Therefore, the inter-cell wiring is a line for transmitting a signal from a terminal point (output terminal) indicated by a white diamond to a terminal point (input terminal) indicated by a white triangle.

  Here, a case in which an instruction to perform circuit restoration display is given, with the range of the cell CC1 shown in the upper left of FIG. Consider as an example. In this case, the circuit diagram display unit 730 first traces the inter-cell wiring wa from the output terminal for the cell CC1 that is the starting point (that is, the inter-cell wiring wa arranged at the terminal point position having the output attribute). By performing the equipotential tracking process as the target graphic), the first stage downstream cell CC2 is reached. Subsequently, the inter-cell wiring wb is traced from the first-stage downstream cell CC2 to reach the second-stage downstream cell CC5. Finally, the inter-cell wiring wd from the second-stage downstream cell CC5 is finally reached. And we are followed to reach the third-stage downstream cells CC3 and CC6. After all, in this inter-cell signal tracking process, four sets of adjacent cells CC2, CC5, CC3, and CC6 are recognized by tracing signals for three stages downstream from the starting cell CC1. In this example, the cell CC4 at the lower left of the figure does not enter the tracking range in the inter-cell signal tracking process based on the above condition.

  FIG. 36 is a circuit diagram obtained when a portion that falls within the tracking range by the inter-cell signal tracking processing as described above is used as a display target circuit. Here, CC1 ′ to CC6 ′ indicated by alternate long and short dashed rectangles in FIG. 36 are cell range frames showing the corresponding relationship with the cells CC1 to CC6 shown in FIG. 35, and there is a correspondence within each cell range frame. The logic circuit symbol of the logic element in the cell to be displayed is displayed. Further, wa ′ to we ′ in FIG. 36 are connections corresponding to the inter-cell wirings wa to we shown in FIG. The circuit diagram display unit 730 associates the element recognized by the element recognition unit 720 with the logic circuit symbol and associates the inter-cell wiring information with the connection between the logic circuit symbols. It fulfilled the function of displaying a circuit diagram.

  In FIG. 36, cell range frames CC1 ′ to CC6 ′ are shown for convenience of explanation in order to show the correspondence with the cells CC1 to CC6 shown in FIG. 35, but actually these cell ranges are displayed. There is no need to display the frame on the circuit diagram. However, since this cell range frame can serve to indicate the range of logic circuits belonging to the same cell, if necessary, the cell range frames CC1 'to CC6' are displayed on the circuit diagram on the display screen. You may make it superimpose and display. If the cell range frame is superimposed on the circuit diagram, the operator (circuit designer) can easily grasp the individual logic circuits constituting the circuit diagram in units of cells.

  As described above, the example in which the display target circuit is the range traced downstream by three cells starting from the cell CC1 has been described. Of course, it is also possible to perform inter-cell signal tracking processing that goes upstream. . For example, in FIG. 35, in the case where the display target circuit is a range traced upstream from the cell CC6 by three cells, it is upstream of the cells CC5, CC4, CC2, CC1, and CC4 (not shown). A cell, a cell upstream of CC2 (not shown) is recognized as an adjacent cell on the upstream side, and a circuit diagram for these is displayed. Of course, it is also possible to perform inter-cell signal tracking processing within the range of ○ stage upstream and ○ stage downstream.

  Further, the starting point is not necessarily a specific cell, and an inter-cell wiring may be used as the starting point. For example, the same result as in FIG. 36 can be obtained when inter-cell signal tracking processing is performed by tracing the cell of three stages downstream from the inter-cell wiring wa.

<<< §8. Specification of display target >>>
Finally, the function of the display target specifying unit 900 in the apparatus shown in FIG. 13 will be described. The display target specifying unit 900 is a component having a function of specifying a display target pattern for the layout pattern display unit 400 and a function of specifying a display target circuit for the circuit diagram display unit 730. Is realized by hardware such as a keyboard and a mouse and a program for functioning the hardware.

  As already described, the layout pattern display unit 400 functions to display a layout pattern as shown in FIG. 11 on the display screen, for example. However, usually, all the LSI layout patterns (the layout pattern of the entire chip as the TOP layer) include a large number of figures and are displayed at once on a display screen having a limited display area. It is not possible. Therefore, practically, the layout pattern display unit 400 can display only a specific partial layout pattern at a time. The display target specifying unit 900 has a function of specifying a part of all layout patterns as a display target pattern with respect to the layout pattern display unit 400. The layout pattern display unit 400 performs processing for selectively displaying the designated display target pattern on the display screen.

  The most typical method of designating the display target pattern is a method of designating “which part of all layout patterns is displayed at which magnification”. In the embodiment shown here, the display target designating unit 900 has a function of designating a range of layout patterns to be displayed, and the layout pattern display unit 400 is a range designated from all layout patterns. Only the patterns inside are selectively output. More specifically, when the operator instructs the display target designating unit 900 to display a specific location at a specific magnification, the layout pattern display unit 400 responds to this instruction with the display target. Information necessary to display the changed layout pattern is read from the block configuration data storage unit 200 and the cell configuration data storage unit 300, and the layout pattern at the specified location is displayed at the specified magnification. become.

  The display target pattern specified by the display target specifying unit 900 is also transmitted to the cell frame determining unit 600. As described in detail in §4, the cell frame determination unit 600 performs a cell frame determination process for determining a cell frame for each cell. In practice, the cell frame determination unit 600 applies to the cells included in all layout patterns. There is no need to perform processing, and cell frame determination processing is performed only for cells that are included in the area displayed on the display screen and its neighboring areas (areas that may be tracked by the inter-cell signal tracking process described above). Is sufficient. Therefore, the cell frame determining unit 600 determines a cell frame for cells in a necessary area based on the display target pattern transmitted from the display target specifying unit 900. Of course, the terminal point determination process by the terminal point determination unit 500 is performed only for the cell frame determined by the cell frame determination unit 600.

  On the other hand, the circuit diagram display unit 730 functions to display, for example, a circuit diagram as shown in FIG. 36 on the display screen. The display of the layout pattern by the layout pattern display unit 400 and the display of the circuit diagram by the circuit diagram display unit 730 do not necessarily have to be performed simultaneously on the same screen. In an environment in which a plurality of displays are juxtaposed, it is preferable to perform these operations simultaneously on these screens. The role of the apparatus according to the present invention is to display a circuit diagram related to a part of the layout pattern currently displayed on the display screen by the layout pattern display unit 400, thereby confirming and verifying the layout pattern. In order to assist, it is preferable that an operator (circuit designer) can observe the layout pattern and its circuit diagram in comparison. In practice, a layout pattern display window and a circuit diagram display window may be displayed on the display screen, and the layout pattern and circuit diagram may be displayed in each window.

  In this way, from the viewpoint of displaying a circuit diagram to assist the checking and verification work for the layout pattern, the circuit to be displayed corresponds to the layout pattern displayed by the layout pattern display unit 400. Should be something. Therefore, the display target specifying unit 900 determines a predetermined display target circuit in association with the display target pattern specified for the layout pattern display unit 400, and performs processing for specifying this for the circuit diagram display unit 730. .

  The simplest method for determining a circuit to be displayed is a method in which a circuit corresponding to a layout pattern currently displayed on a display screen is used as a display target circuit as it is. If such a method is adopted, the display target designating unit 900 may always perform processing for designating the circuit corresponding to the display target pattern as the display target circuit for the circuit diagram display unit 730. In this case, a circuit diagram corresponding to the layout pattern displayed by the layout pattern display unit 400 is displayed by the circuit diagram display unit 730. In short, when an operator inputs to the display target specifying unit 900 to specify a layout pattern to be displayed, the layout pattern of the specified portion is displayed and a circuit diagram corresponding to the layout pattern is displayed. It will be displayed at the same time.

  On the other hand, the operator may intentionally input to specify the display target circuit. As an example, a function of inputting an operator's instruction for designating a specific graphic on the display screen of the layout pattern to the display target designating unit 900, and a part of the circuit related to the specific graphic to the circuit diagram display unit 730 Is provided as a display target circuit, the display target circuit can be specified in accordance with an instruction input from the operator. For example, in the state where the layout pattern as shown in FIG. 11 is displayed, when the operator performs an operation of clicking a specific figure on the layout pattern using the mouse, the instruction target specifying unit 900 By recognizing the specific figure and designating a circuit related to the cell including the specific figure or a cell located in the vicinity of the specific figure as a display target circuit, the operator can select the vicinity of the desired pattern on the layout pattern. The circuit diagram can be displayed.

  In addition, as described in §7, the circuit diagram display unit 730 has a function of performing inter-cell signal tracking processing, so that the operator can click on a specific figure on the layout pattern with the mouse. , Specifying the click position as the starting point, and performing inter-cell signal tracking processing that traces the signal for n stages upstream or downstream from this starting point, and indicating that the circuit within the tracking range is the display target circuit It is also possible to input. When such a display target circuit designating method is adopted, the display target designating unit 900 uses the cell frame information determined by the cell frame determining unit 600 to perform the following process based on the operator's designation input. Thus, the display target circuit may be designated on the circuit diagram display unit 730.

  First, if the specific figure specified by the operator on the layout pattern is a figure in the cell frame, n stages upstream or downstream from the cell in the cell frame (n is specified by the operator) The signal is traced only by an integer of 0 or more) to recognize an adjacent cell (meaning a cell adjacent in the signal flow, not a cell adjacent in the two-dimensional arrangement), and a starting point The circuit diagram display unit 730 may be instructed to designate the circuit corresponding to the cell and the adjacent cell as the display target circuit (in the case of n = 0, the inter-cell signal tracking process is not actually performed). Only the cell that is the starting point becomes the display target circuit).

  For example, in the conceptual diagram shown in FIG. 35, the operator designates a position corresponding to the cell frame FF1 as a starting point (actually, a mouse click is performed on the layout pattern displayed on the screen), and n = 3. If the instruction to perform signal tracking for three stages downstream is given, the display target designating unit 900 uses the starting position and the number of signal tracking stages as information for designating the display target circuit to the circuit diagram display unit 730. Can be transmitted. As described above, the circuit diagram display unit 730 performs inter-cell signal tracking processing based on such an instruction, and as a result, displays a circuit diagram as shown in FIG.

  On the other hand, when the specific figure designated by the operator on the layout pattern is a figure constituting the wiring outside the cell frame, n stages upstream (n is an integer of 1 or more) upstream or downstream from the wiring. It is only necessary to trace the signal only to recognize the adjacent cell and to give an instruction to the circuit diagram display unit 730 that the circuit corresponding to the adjacent cell is the display target circuit.

  For example, in the conceptual diagram shown in FIG. 35, the operator designates a position corresponding to the inter-cell wiring wa as a starting point (actually, a mouse click is performed on the layout pattern displayed on the screen), and n = 3 Assuming that an instruction to perform signal tracking for three stages downstream is given, the display target specifying unit 900 uses the start position and signal tracking as information for specifying the display target circuit to the circuit diagram display unit 730. The number of stages may be transmitted. Also in this case, the circuit diagram display unit 730 performs the inter-cell signal tracking process and displays the circuit diagram as shown in FIG. 36 as described above.

  A method for designating a display target circuit using such an inter-cell signal tracking processing function is extremely useful for a circuit designer to perform a confirmation operation and a verification operation on a layout pattern. The layout pattern itself is a collection of a large number of figures developed on a plane, but the circuit designer can use the above-described method to start a related area that is upstream or downstream from an arbitrary position on the layout pattern. Since the circuit diagram can be displayed as appropriate, the analysis of the layout pattern becomes very easy. For example, when there is a defect in the layout pattern, it is possible to trace on the layout pattern a portion where a logical operation may be defective due to the defect.

  In this way, the great effect of the present invention is that a circuit diagram of an arbitrary part of a currently displayed layout pattern can be restored efficiently and accurately. The present invention is particularly effective when a final check of a layout pattern is performed in a manufacturing department that prints a layout pattern on a semiconductor wafer. In the final check, it becomes possible to find the defective part at an early stage, so that it is possible to prevent the occurrence of defective products. Further, even when a defective portion is found, it is possible to easily determine whether or not the repair is possible using the redundant circuit by performing an analysis with reference to the restored circuit diagram.

100: design data input unit 200: block configuration data storage unit 300: cell configuration data storage unit 400: layout pattern display unit 500: terminal point determination unit 550: equipotential tracking unit 600: cell frame determination unit 700: circuit restoration unit 710 : Area recognition unit 720: element recognition unit 730: circuit diagram display unit 800: condition setting unit 900: display target designation unit A to D: blocks A to C: logical values C, C11 to C13, C101 to C103: cell C1, C2: Contacts CC1 to CC6: Cells CC1 'to CC6': Cell range frames F, F1 to F6, F11 to F13: Cell frames FF1 to FF6: Cell frames f1 to f11: Figure f (OR) constituting the cell: Logic Japanese figure fz: figure of interest G: MOS transistor gates H1 to H4: intersection line segments L1 to L5: layer N: N-type MOS transistor channel Region N1, N2: N-type MOS transistor O: origin of XY coordinate system defined in intermediate layer o: origin of xy coordinate system defined in lowest layer P: channel region P1-P12 of P-type MOS transistor: Points P1 and P2 on the αβ coordinate system: P-type MOS transistors P21 to P30: Points on the XY coordinate system Q: Origins Qa to Qd of the αβ coordinate system defined in the top layer Hierarchical points R1 to R1 on the αβ coordinate system R3: Points T1 to T64 on the XY coordinate system: Terminal point TOP: Block SD of the highest layer SD: Source / drain regions W1 to W3: Inter-block wirings W4 to W5: Inter-cell wirings W10 to W40: Wirings w1 to w5 w12, w13: inter-cell wiring wa-we: inter-cell wiring wa'-we ': connection between logic circuit symbols X: coordinate axes X1-X3 of the XY coordinate system defined in the intermediate hierarchy: one coordinate value on the coordinate axis X : Coordinate axis Y of the xy coordinate system defined in the lowest hierarchy: coordinate axes Y1 to Y3 of the XY coordinate system defined in the middle hierarchy: one coordinate value on the coordinate axis Y: y of the xy coordinate system defined in the lowest hierarchy Coordinate axis α: Coordinate axes α1 to α4 in the αβ coordinate system defined in the TOP hierarchy: 1 coordinate value on the coordinate axis α β: Coordinate axes β1 to β4 in the αβ coordinate system defined in the TOP hierarchy: 1 coordinate value on the coordinate axis β

Claims (13)

An LSI circuit diagram restoring device for restoring a circuit diagram of an LSI based on design data indicating a layout pattern of the LSI,
A cell configuration data storage unit for storing cell configuration data in which individual components constituting an LSI are recorded for each layer of a figure as a component;
A block for storing block configuration data including cell arrangement information indicating the position coordinates of each cell and inter-cell wiring information indicating a figure constituting the inter-cell wiring for a block in which a plurality of cells are arranged at predetermined positions. A configuration data storage;
A design data input unit for inputting data to the cell configuration data storage unit and the block configuration data storage unit;
Based on the cell configuration data and the block configuration data, a layout pattern display unit that draws a display target pattern on a plane and displays it as an image;
Among the layers included in the cell configuration data, a cell frame determination condition including information indicating a specific layer used for cell frame determination, and a plurality of figures included in the cell configuration data and the block configuration data are equal to each other. An equipotential tracking condition indicating a requirement for potential, a region recognition condition for performing region recognition based on a graphic included in the cell configuration data, and a specific relationship based on a connection relationship between a plurality of regions and terminal points A condition setting unit for setting an element recognition condition for recognizing the element;
For each cell, a figure recorded in a specific layer used for determining the cell frame of the cell configuration data is extracted, a logical sum figure of the extracted figure is formed, and the circumscribed figure of the logical sum figure is converted into a cell frame. A cell frame determination unit to be obtained as
Among the figures included in the inter-cell wiring information, for the intersecting figure that intersects the cell frame, the cell line recognizes an intersection line segment cut by the intersecting figure, and a terminal point is formed at one point on the intersection line segment. A terminal point determination unit for determining
Based on the equipotential tracking conditions, an equipotential tracking unit for recognizing another figure having an equipotential as an equipotential figure with respect to a specific figure of interest constituting the layout pattern,
Based on the region recognition conditions, for a figure included in the cell configuration data in a predetermined recognition target cell, a region recognition unit for recognizing each element configuration region that constitutes an element;
A connection relationship between a plurality of element configuration regions recognized by the region recognition unit and terminal points determined by the terminal point determination unit is electrically connected to a figure recognized as being equipotential to each other by the equipotential tracking unit. An element recognition unit that recognizes an element corresponding to the recognition target cell by matching with the element recognition condition while handling it as being connected,
A circuit diagram display unit for displaying a logic circuit diagram for a display target circuit by associating an element recognized by the element recognition unit with a logic circuit symbol and associating inter-cell wiring information with a connection between logic circuit symbols;
A display target designating unit having a function of designating a display target pattern for the layout pattern display unit and a function of designating a display target circuit for the circuit diagram display unit;
With
The cell configuration data storage unit stores cell configuration data in which a figure as a component is recorded for each layer to which a predetermined identification code is attached,
The block configuration data storage unit stores wiring information including a figure constituting a wiring between cells or wiring for each layer to which a predetermined identification code is attached,
The condition setting unit sets information indicating a contact layer including a figure indicating a contact for connecting a plurality of layers together with information indicating a conductive layer as an equipotential tracking condition,
The equipotential tracking unit recognizes that the superimposed figure is equipotential when the figures belonging to a plurality of conductive layers with the same identification code are superimposed in a plane, and If a figure belonging to a plurality of conductive layers with different identification codes is overlapped in a plane, the overlapped figure is equal only if a figure belonging to the contact layer exists in the overlap area. An LSI circuit diagram restoring device characterized by recognizing an electric potential. In the LSI circuit diagram restoration device according to claim 1,
It has a hierarchical structure consisting of all n layers (where n ≧ 2) including the 1st to (n−1) th layers in which blocks are arranged and the nth layer in which cells are arranged. To handle the layout pattern of LSI
The cell configuration data storage unit stores cell configuration data in which individual components belonging to the nth layer are recorded as graphic elements for each layer.
The block configuration data storage unit stores block configuration data for blocks belonging to the i-th (1 ≦ i ≦ n−1) hierarchy, and in the case of i <n−1, Block arrangement information indicating position coordinates and inter-block wiring information indicating graphics constituting the inter-block wiring are stored. When i = n−1, a cell indicating the position coordinates of a cell belonging to a lower layer is stored. Placement information and inter-cell wiring information indicating a figure constituting inter-cell wiring are stored,
An LSI circuit diagram restoring apparatus, wherein a terminal point determination unit determines a terminal point for a graphic included in inter-block wiring information together with a terminal point for a graphic included in the inter-cell wiring information. The LSI circuit diagram restoration device according to claim 1 or 2,
The cell configuration data storage unit stores cell configuration data in which a graphic composed of polygons constituted by sides parallel to the x axis or the y axis in the xy coordinate system is recorded,
An LSI circuit diagram restoration device, wherein the cell frame determination unit obtains a regular circumscribed rectangle formed by sides parallel to the x-axis or the y-axis as a cell frame. In the LSI circuit diagram restoration device according to any one of claims 1 to 3 ,
The condition setting unit sets the priority order for the combination of a pair of layers with different identification codes as equipotential tracking conditions,
If the equipotential tracking unit has a figure that belongs to three or more layers to which different identification codes are attached in a plane, and the figure that belongs to the contact layer exists in the overlap area, the priority order An LSI circuit diagram restoration apparatus, wherein only a superimposed figure belonging to a pair of layers based on the above is recognized as being equipotential. In the LSI circuit diagram restoration device according to any one of claims 1 to 4 ,
The terminal point determination unit gives each equipotential tracking instruction to the equipotential tracking unit with each intersecting figure intersecting the cell frame as a target figure, and is recorded in the cell configuration data corresponding to the cell frame among the intersecting figures. An LSI circuit diagram restoring apparatus characterized by recognizing an intersection line segment only for an intersection figure in which any figure becomes an equipotential figure. In the LSI circuit diagram restoration device according to any one of claims 1 to 5 ,
The condition setting unit assigns the logical product area of figures belonging to different layers to a specific element configuration area, and the figure area belonging to the specific layer and including the recognized specific element configuration area. An LSI circuit diagram restoration device, characterized in that a rule associated with a specific element configuration region is set as a region recognition condition. In the LSI circuit diagram restoration device according to any one of claims 1 to 6 ,
An LSI characterized in that a condition setting unit sets, as an element recognition condition, a rule indicating a mutual connection relationship between a plurality of element configuration regions and terminal points constituting each of the plurality of candidate elements. Circuit diagram restoration device. The LSI circuit diagram restoration device according to any one of claims 1 to 7 ,
Region recognition conditions for the condition setting unit to recognize the channel region, gate region, source / drain region, mutual connection relationship between the channel region, gate region, source / drain region, and connection relationship between these and terminal points And an element recognition condition for recognizing a logic element including a MOS transistor on the basis of the above. In the LSI circuit diagram restoration device according to any one of claims 1 to 8 ,
A display target designating unit designates a part of all layout patterns as a display target pattern for the layout pattern display unit, and a circuit corresponding to the display target pattern for the circuit diagram display unit. An LSI circuit diagram restoration device having a function of designating as a display target circuit. An LSI circuit diagram restoring device for restoring a circuit diagram of an LSI based on design data indicating a layout pattern of the LSI,
  A cell configuration data storage unit for storing cell configuration data in which individual components constituting an LSI are recorded for each layer of a figure as a component;
  A block for storing block configuration data including cell arrangement information indicating the position coordinates of each cell and inter-cell wiring information indicating a figure constituting the inter-cell wiring for a block in which a plurality of cells are arranged at predetermined positions. A configuration data storage;
  A design data input unit for inputting data to the cell configuration data storage unit and the block configuration data storage unit;
  Based on the cell configuration data and the block configuration data, a layout pattern display unit that draws a display target pattern on a plane and displays it as an image;
  Among the layers included in the cell configuration data, a cell frame determination condition including information indicating a specific layer used for cell frame determination, and a plurality of figures included in the cell configuration data and the block configuration data are equal to each other. An equipotential tracking condition indicating a requirement for potential, a region recognition condition for performing region recognition based on a graphic included in the cell configuration data, and a specific relationship based on a connection relationship between a plurality of regions and terminal points A condition setting unit for setting an element recognition condition for recognizing the element;
  For each cell, a figure recorded in a specific layer used for determining the cell frame of the cell configuration data is extracted, a logical sum figure of the extracted figure is formed, and the circumscribed figure of the logical sum figure is converted into a cell frame. A cell frame determination unit to be obtained as
  Among the figures included in the inter-cell wiring information, for the intersecting figure that intersects the cell frame, the cell line recognizes an intersection line segment cut by the intersecting figure, and a terminal point is formed at one point on the intersection line segment. A terminal point determination unit for determining
  Based on the equipotential tracking conditions, an equipotential tracking unit for recognizing another figure having an equipotential as an equipotential figure with respect to a specific figure of interest constituting the layout pattern,
  Based on the region recognition conditions, for a figure included in the cell configuration data in a predetermined recognition target cell, a region recognition unit for recognizing each element configuration region that constitutes an element;
  A connection relationship between a plurality of element configuration regions recognized by the region recognition unit and terminal points determined by the terminal point determination unit is electrically connected to a figure recognized as being equipotential to each other by the equipotential tracking unit. An element recognition unit that recognizes an element corresponding to the recognition target cell by matching with the element recognition condition while handling it as being connected,
  A circuit diagram display unit for displaying a logic circuit diagram for a display target circuit by associating an element recognized by the element recognition unit with a logic circuit symbol and associating inter-cell wiring information with a connection between logic circuit symbols;
  A display target designating unit having a function of designating a display target pattern for the layout pattern display unit and a function of designating a display target circuit for the circuit diagram display unit;
With
The display target designating unit
A function for inputting an operator's instruction for designating a specific graphic on the display screen of the layout pattern, and a function for designating a part of a circuit related to the specific graphic as a display target circuit to the circuit diagram display unit. And
  If the specific figure specified on the layout pattern is a figure in the cell frame, signals for n stages (n is an integer of 0 or more) upstream or downstream from the cell in the cell frame as the starting point To recognize the adjacent cell, and designate that the cell corresponding to the starting point and the circuit corresponding to the adjacent cell are the display target circuit,
  If the specific figure specified on the layout pattern is a figure that forms the wiring outside the cell frame, the signal is sent for n stages (n is an integer of 1 or more) upstream or downstream from the wiring. An LSI circuit diagram restoration apparatus characterized by tracing and recognizing an adjacent cell and specifying that a circuit corresponding to the adjacent cell is a display target circuit. The LSI circuit diagram restoration device according to claim 10 ,
An LSI circuit diagram restoring apparatus, wherein the circuit diagram display unit has a function of displaying a cell range frame for indicating a range of logic circuits belonging to the same cell on the circuit diagram. The LSI circuit diagram restoration device according to claim 10 or 11 ,
The condition setting unit sets an element recognition condition for recognizing a specific element based on a connection relationship including a terminal point having at least two types of attributes of an input terminal and an output terminal,
The element recognition unit performs attribute recognition of the terminal points of each cell based on the element recognition conditions,
The circuit diagram display unit executes an inter-cell signal tracking process for tracking n stages of cells from the starting point in consideration of the attribute of the terminal point of each cell, and specifies a display target circuit. Circuit diagram restoration device. A program for causing a computer to function as the LSI circuit diagram restoration device according to claim 1 .

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