JP3253482B2 - Color signal demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PAL system and a SEC system.
The present invention relates to a color signal demodulation circuit of an AM TV (television) receiver, and particularly to a function of adding a color signal around 1H (horizontal synchronization signal period) to reduce phase distortion when used in a PAL system. Can be done exactly, S
The present invention relates to a color signal demodulation circuit capable of converting an intermittent color signal into a continuous and uniform color signal when used in the ECAM system.

[0002]

2. Description of the Related Art In the PAL system, R-out of two color signals is used.
The Y signal is inverted every 1H and sent, and the RY signal is sent at a constant phase. Then, by adding the color signals of about 1H in the TV receiver, the phase distortion generated in the transmission system is reduced, and the hue fluctuation is prevented.

Conventionally, in the color signal demodulation circuit of the PAL system, the addition function has been performed on the RY signal and the BY signal before color demodulation. In that case, a glass delay line was used as a delay component. However, recently, CCDs (Charge Transfer Devices) have begun to be used as delay components. When a CCD is used, the color signal after color demodulation is delayed by 1H.

FIG. 2 shows a part of a TV receiver having such a PAL color signal demodulation circuit. A carrier color signal from an input terminal (1) is input to a BY demodulator (2). And RY demodulator (3). BY demodulator (2)
And the RY demodulator (3), to which different carrier waves are applied, are demodulated respectively. The demodulated outputs of the BY demodulator (2) and the RY demodulator (3) are led out of the IC (6) after unnecessary components are removed by the LPFs (4) and (5), and are output to the CCD IC ( 7) is applied. CCDIC
(7) delays the demodulated color difference signal for 1H period, and is delayed by the first and second CCD circuits (8) and (9).

First and second CCD circuits (8) and (9)
Is returned to the inside of the IC (6) again and is clamped by the first and second clamp circuits (10) and (11). First and second clamp circuits (10) and (11)
Are passed through LPFs (12) and (13) for removing unnecessary components caused by clocks of the first and second CCD circuits (8) and (9), and are output from the first and second adders ( 14) and (15).

On the other hand, the color difference signals from the LPFs (4) and (5) are directly applied to the first and second adders (14) and (15), whereby 1H of each color difference signal is applied.
The signals before and after are added. By this addition operation, phase distortion occurring in the transmission system is reduced, and hue fluctuation is prevented. Next, the operation will be described with reference to the solid line in FIG. Now, it is assumed that a carrier color signal indicated by a solid line in FIG. As shown, the RY signal is 1H
It arrives while reversing the phase every time.

On the other hand, the BY demodulator (2) shown in FIG.
Is applied with a carrier having a constant phase shown in FIG.
To the -Y demodulator (3), a carrier inverted every 1H shown in FIG. 3C is applied. The carrier wave of FIG.
The BY signal component of (a) is demodulated and the B signal shown in FIG.
The -Y signal is derived from the BY demodulator (2) in FIG.
3 (c) demodulates the RY signal component of FIG. 3 (a), and the RY signal shown in FIG. 3 (e) is output from the RY demodulator (3) of FIG. Derived. The same is performed at the 2H-th and the 3H-th in FIG. 3, and the demodulated outputs shown in FIGS. 3 (d) and 3 (e) are obtained.

Next, 1 shown in FIGS. 3D and 3E, respectively.
By adding the signals before and after H, a demodulated output can be obtained. That is, if the 1H and 2H signals in FIG.
Since both are in the 0-degree direction, a BY signal in the 0-degree direction shown in FIG. 3F is obtained. Similarly, if the 1H-th and 2H-th signals in FIG. 3E are added, since both signals are in the 90-degree direction, a BY signal in the 90-degree direction shown in FIG. 3G is obtained.

Next, the reduction of the phase distortion will be described.
Now, it is assumed that the phases of both the BY signal and the RY signal in FIG. 3A fluctuate in the counterclockwise direction, and each of them becomes a vector indicated by a dotted line. The carrier of FIG. 3B demodulates the BY ′ signal component of FIG. 3A, and the BY ′ signal shown in FIG. 3D is output from the BY demodulator (2) of FIG. Derived. at the same time,
The carrier wave of FIG. 3B demodulates the BY axis component of the RY ′ signal component of FIG. 3A and demodulates the RY ′ signal (distortion component) shown in FIG. 3D. Would. Similarly, FIG.
When the 2H carrier color signal of FIG. 3A is demodulated with the 2H carrier wave, the 2H signal of FIG. 3D is demodulated.

Here, when the signals of the 1H and 2H in FIG. 3D are vector-added, the signals of FIG. 3F are obtained. In FIG. 3 (f), the RY ′ signal (distortion component) of the first H and 2
The H-th RY ′ signal (distortion component) is canceled, and only the required BY ′ signal on the BY axis component can be detected. FIG.
The carrier wave of (c) demodulates the RY ′ signal component of FIG. 3A, and the RY ′ signal shown in FIG. 3E is derived from the RY demodulator (3) of FIG. You. At the same time, the carrier wave of FIG. 3C demodulates the RY axis component of the BY ′ signal component of FIG. 3A and demodulates the BY ′ signal shown in FIG. . Similarly, the signal shown in FIG. Vector addition of the 1H-th and 2H-th signals in FIG. 3 (e) results in the signal in FIG. 3 (g), and in this case also, the BY ′ signal, which is an unnecessary distortion component, is canceled.

Therefore, by the addition operation of the first and second adders (14) and (15), phase distortion occurring in the transmission system can be reduced, and hue fluctuation can be prevented. The demodulated RY signal and BY signal from the first and second adders (14) and (15) are matrixed by a matrix circuit (16), and the RY signal, BY signal and The GY signal is derived from the output terminals (17) to (19).

Therefore, according to the circuit of FIG. 2, it is possible to demodulate the PAL color signal.

[0013]

However, in the circuit of FIG. 2, a level fluctuation occurs between the input and output of the first and second CCD circuits (8) and (9), and the first and second adders (14) and There is a problem that the distortion component cannot be accurately canceled at the time of vector synthesis in (15).

That is, R- in the 0-degree direction in FIG.
There is a problem that the magnitudes of the Y 'signal vector and the RY' signal vector in the 180-degree direction are not equal, and a distortion component remains even after the cancellation.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and has been made in consideration of the above-described circumstances. A demodulator for demodulating a color difference signal of the SECAM system and an output signal of the demodulator are a BY signal and an RY signal.
Separating means for separating the signal into two signals, adding means for applying an ALC additional pulse to one of the color difference signals from the separating means,
The one color difference signal to which the ALC additional pulse has been applied is 1
A first CCD which delays the other color difference signal from the demodulator by an H period, a second CCD which delays the other color difference signal by 1H period,
The output signal of the CD is applied, the level of the output signal of the first CCD is level detected based on the level of the ALC additional pulse, and the level of its own output signal is output from the demodulator according to the level detection output. First to match signal level
ALC circuit and an output signal of the second CCD are applied,
A 2ALC circuit for adjusting the magnitude of its own output signal to the output signal level of the demodulator according to the level detection output of the first ALC circuit; one color difference signal from the demodulator and an output signal of the first ALC circuit And a second color difference signal from the demodulator and the second adder.
A second adder for adding the output signal of the LC circuit.

[0016]

According to the present invention, the ALC additional pulse is applied to a predetermined position of the demodulated PAL color signal before being applied to the CCD. Then, the level of the ALC additional pulse in the color signal derived from the CCD is detected, and the magnitude of the color signal derived from the CCD is returned to the magnitude before input to the CCD according to the detected output. Therefore, the levels of the color signals before and after the delay become equal, and if the two signals are added, the distortion correction of the PAL color signal can be accurately performed. Further, according to the present invention, an ALC additional pulse is added to one of the two color difference signals demodulated in the SECAM system, and the same addition as described above is performed. Therefore, the incoming intermittent color signal can be converted into a continuous color signal of uniform level. Therefore, the CCD can be used for both PAL distortion correction and SECAM signal continuity, and accurate distortion correction and signal continuity at the same level can be performed.

[0017]

1 shows a color signal demodulation circuit according to the present invention, wherein (20) is an input terminal to which a color video signal is applied, (21) is a sync separation circuit for separating a horizontal sync signal,
(22) is a frequency 32fH (f) synchronized with the horizontal synchronizing signal.
H is a frequency-divided output of a horizontal synchronization signal frequency and a horizontal AFC (automatic frequency control) circuit for generating a horizontal synchronization signal, (23)
Is a frequency dividing circuit that divides the frequency of the 32fH signal as a clock signal and is reset in accordance with the horizontal synchronization signal to generate a BGP (burst gate pulse) and an ALC additional pulse. (24) is a chroma signal extracting circuit, and (25) ) Is a burst extraction circuit for extracting a burst signal, (26) is a carrier generation circuit for generating a carrier according to the burst signal, and (2)
7) switch (28) according to the ALC additional pulse
Is switched to the a side to add an ALC additional pulse of 0.2 V of the reference power supply (36) to a predetermined position of the output signal of the BY demodulator (2). The level of the -Y signal is compared with the reference voltage Vref of the reference power supply (30) during the BGP period from the terminal (31), and the level of the BGP period of the BY signal is compared with the reference voltage Vref.
A clamp detection circuit for generating a detection output for setting to the ref level, a switch (34) is closed in response to the ALC additional pulse from the terminal (33), and a clamp detection circuit (32) is provided.
A detection circuit for extracting the 0.2 V ALC additional pulse applied in 7); (35) a reference voltage V of the reference power supply (30);
ref and 0.2 of the reference power supply (36) of the additional circuit (27).
The voltage obtained by adding V is compared with the detection output of the detection circuit (32) to generate a comparison output such that the ALC additional pulse detected by the detection circuit (32) returns to the original level of 0.2V. A comparator; (37) a holding capacitor; (38) and (39) first and second ALC circuits for changing the levels of the BY signal and the RY signal according to the voltage held by the capacitor (37); (100) is a terminal (101)
(Flyback pulse) is applied from IC
Within (6), a terminal for generating an SCP (Sandcastle pulse) indicating the generation timing of a horizontal synchronizing signal, a vertical synchronizing signal, and BGP, (102) an IC for generating a SECAM color signal, and (103) an SCP SCP discriminating circuit for generating BGP and ALC additional pulses in response to (10
4) is a SECAM demodulator that performs FM detection of the FM-modulated SECAM chrominance signal, and (105) is an ISAM according to BGP.
An ID circuit for generating a D (ident) signal, (106)
Is an ALC additional pulse generation circuit that generates an ALC additional pulse, (107) is a separation circuit that separates the output signal of the SECAM demodulator (104) into two signals, a BY signal and an RY signal, and (108) is BY from the separation circuit (107)
A switch for applying an ALC additional pulse to a predetermined position of a signal,
(109) and (110) are switches that are closed when a SACAM signal is reproduced, and (111) and (112) are switches that are closed when a PAL signal is reproduced.

In the circuit blocks shown in FIG. 1, the same circuit blocks as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In the PAL color video signal from the input terminal (20), the chroma signal is converted into a chroma signal extraction circuit (2).
It is extracted in 4) and applied to the BY demodulator (2) and the RY demodulator (3).

The PAL color video signal from the input terminal (20) is obtained by extracting a burst signal by a burst extraction circuit (25) and applying the burst signal to a carrier generation circuit (26). The BY demodulator (2) and the RY demodulator (3)
Carriers synchronized in each phase are applied from the carrier generation circuit (26) and are demodulated respectively. The PAL color video signal from the input terminal (20) is
A horizontal synchronizing signal is extracted by a sync separation circuit (21) and applied to a horizontal AFC circuit (22). Horizontal AFC circuit (2
2) is a PLL that locks the phase with the horizontal synchronizing signal, and applies a phase-locked signal of 32 fH to the clock signal and the horizontal synchronizing signal to the frequency dividing circuit (23). Dividing circuit (23)
Generates a frequency dividing function and a logical output of the frequency-divided signal. Since the signal is reset in accordance with the horizontal synchronizing signal and divides the frequency of the 32 fH signal, various signals with desired timing can be generated. BGP for terminal (40) and A for terminal (41)
An LC additional pulse is generated. The BGP of the terminal (40) is applied to the terminal (31), and the ALC additional pulse of the terminal (41) is applied to the terminal (33).

The switch (28) of the additional circuit (27) is switched in response to the ALC additional pulse from the terminal (41), and the 0.2 V ALC additional pulse of the reference power supply (36) is a part of the BY signal. Will be derived as This will be described with reference to FIGS. FIG. 4 (a)
4 shows a BY signal from a BY demodulator (2). A signal having the phase shown in FIG. 4D is generated from this signal as an ALC additional pulse, and is added to the signal shown in FIG.
Make a signal. The hatched portion of the signal in FIG.
This signal is an additional pulse.
Always constant. Therefore, this ALC additional pulse is converted to CC
D, so that if a level fluctuation occurs, it is returned to the original size. As a result, the RY signal also returns to its original size.

FIG. 5 shows a position where the ALC additional pulse is generated. FIG. 5A shows a video signal, and FIG.
(B) shows BGP. The ALC additional pulse is shown in FIG.
It occurs within period A of (a). The period A is a period from when the content of the video signal ends to when the next 1H burst signal starts. FIG. 5C shows the ALC in the period A.
3 shows an additional pulse.

The signal shown in FIG. 4 (b) is applied to the CCD IC (7), and when it is output, attenuation occurs as shown in FIG. 4 (c). And this attenuated signal is the first
The voltage is applied to the clamp circuit (10), the LPF (13), and the first ALC circuit (38). Note that the RY signal is also B
The signal is transmitted in the same manner as the -Y signal. Clamp detection circuit (2
9) compares the level of the BY signal from the LPF (13) with the reference voltage Vref of the reference power supply (30) during the BGP period from the terminal (31) and compares the level of the BY signal with the BGP.
A detection output for setting the level of the period to the level of the reference voltage Vref is applied to the first clamp circuit (10). Therefore, when the pedestal level is clamped to the reference voltage Vref, R
A -Y signal is generated from the first clamp circuit (10). The output of the clamp detection circuit (29) is also applied to the second clamp circuit (11), and the level of the RY signal is also adjusted in the same manner as the BY signal.

The output signal of the first ALC circuit (38) is applied to the detection circuit (32). The detection circuit (32) switches (3) in accordance with the ALC additional pulse from the terminal (33).
4) is closed, and the ALC additional pulse applied by the additional circuit (27) is extracted. The ALC additional pulse is 0.2 V
However, the level has decreased due to the influence of the CCDIC (7) and the LPF (12). Therefore, a voltage obtained by adding the reference voltage Vref of the reference power supply (30) and 0.2V of the reference power supply (36) of the additional circuit (27) is set as a reference voltage, and it is detected how much the level has dropped from this voltage. By doing so, the level-reduced signal is returned to the original signal. The comparator (35) applies the detection output to the holding capacitor (37), and outputs the first and second ALC circuits (38) and (3) based on the output voltage of the capacitor (37).
Adjustment is made so that the amplitude of 9) becomes large. As a result, at the output terminals of the first and second ALC circuits (38) and (39), the BY signal and the RY signal equal to the level before being input to the CCDIC (7) are obtained.

For this reason, signals of about 1H having the same level are applied to the first and second adders (14) and (15), and the first and second adders (14) and (15) add the signals. By the operation, phase distortion generated in the transmission system can be reduced, and hue fluctuation can be prevented. First and second adders (14) and (1)
The demodulated RY signal and BY signal from 5) are matrixed by a matrix circuit (16), and the RY signal, BY signal, and GY signal are output from the output terminals (17) to (17). 19).

Therefore, according to the circuit of FIG. 2, it is possible to demodulate the PAL color signal. FIG. 6 shows a specific circuit example of the detection circuit (32) and the comparator (35) of FIG. 1. A BY signal is supplied to a terminal (50) and a reference power supply (30) is supplied to a terminal (51). A reference voltage Vref is applied. The multiplication value of the current value of the constant current source (52) and the resistance (53) is 0.2.
V is set. Therefore, the transistor (54)
The comparison between the comparator and the transistor (55) is a comparison operation of the comparator (35). The ALC additional pulse is output from the switch (56).
Are opened and closed, and the comparison operation is performed only during the period in which the ALC additional pulse arrives, and the comparison output is output to the output terminal (57).

Next, the demodulation of the SACAM color signal will be described. When receiving the PAL signal, the switch (1
11) (112) is closed and switches (109) and (11)
0) was open. When it receives the SACAM signal, the switches (111) and (112) are opened and the switches (109) and (110) are closed. The SCP generated at the terminal (100) is applied to the SCP discriminating circuit (103). The SCP has the waveform shown in FIG. 7C, and is formed so that the BGP is superimposed during the FBP period. The FBP is configured so that the waveform is saturated at 4 V, and the BGP is configured so that the waveform is saturated at 6 V. I have. In FIG. 7C, a vertical synchronizing signal is also present, but at 2 V, and is not directly related to the operation of FIG.

The SCP shown in FIG. 7C is an SCP discriminating circuit (1
03), the SCP determination circuit (103)
The ALC additional pulse (FIG. 7 (d)) and BGP (FIG. 7
(B)) occurs. FIG. 8 is a diagram showing an SCP discriminating circuit (10
FIG. 7 (c) is applied to the input terminal (113) of the SCP shown in FIG. The reference voltage of the first comparator (114) is 3V, and the second comparator (1
The reference voltage of 15) is set to 5V. For this reason, an "H" level pulse is generated at the output terminal of the first comparator (114) at time t1 and at the output terminal of the second comparator (115) at time t2, and the edge detection circuit (1
16) and (117) detect the edge. Therefore, the signal of FIG. 7D is obtained at the Q output of the R-SFF (118). The signal shown in FIG. 7B is obtained at the output terminal (119) of the second comparator (115).

The ID circuit (105) responds to BGP according to
If the currently arriving color signal is a BY signal or an RY signal
It is determined whether the signal is a signal or not, and the separation circuit (107) is switched every 1H. This will be described with reference to FIG. SEC
When the signal shown in FIG. 9A is generated from the AM demodulator (104), the switch (1) is operated by the operation of the separation circuit (107).
09) is applied to the signal of FIG. 9C, and the signal of FIG. 9B is applied to the switch (110).

Here, the ALC additional pulse generation circuit (10
6) and the switch (108), an ALC additional pulse is added to the BY signal at the timing of FIG. The specific adding method is the same as that of PAL, and the description is omitted. The signals from the switches (109) and (110) are
The voltage is applied to the CCDIC (7), delayed and the terminal (1
20) Applied from (121) to IC (6) and applied to first and second adders (14) and (15). The BY signal that has passed through the first clamp circuit (10), the LPF (13), and the first ALC circuit (38) is returned to the signal level before being applied to the CCDIC (7), so that the first adder ( The levels of the two signals applied to 14) are equal. The BY signal of the same level is alternately applied to the first adder (14) every 1H, and the output thereof is a continuous BY signal as shown in FIG. 9D.

The same operation is performed for the second adder (15), and its output is a continuous R as shown in FIG.
-Y signal is obtained. Therefore, according to the circuit of FIG.
The intermittent color signal of the ECAM system can be converted into a color signal that is continuous and uniform in level. For this reason, CCDIC
(7) can be used for both PAL distortion correction and SECAM signal continuity, and accurate distortion correction and signal continuity with uniform levels can be performed.

In the SECAM system, the signal is averaged in the first and second adders (14) and (15), so that the output level is 1/2 that of PAL. Therefore, if the level of the detected color signal of PAL is set to 1V, that of SECAM is set to 2V. Then, the color signal processing circuits after the first and second adders (14) and (15) can be shared, and the number of circuit elements can be greatly reduced.

In the present invention, since SCP is used as the SECAM ALC additional pulse, the ALC additional pulse can be easily created. If there is no SCP,
It must be made as in the case of PAL, which leads to a significant increase in circuit elements. Note that BGP1 in FIG.
Is a BGP generated from the frequency divider (23), and IC
The rise is slower than the BGP2 of FIG. 7B derived to the outside of (6). This is the terminal (3
This is a BGP for internal use of the IC applied to 1), and is created so that the timing does not overlap with the ALC additional pulse.

[0033]

As described above, according to the present invention, the level of the PAL color signal before and after the delay can be equalized, and if the two signals are added, the color signal distortion can be accurately corrected. be able to. Further, according to the present invention, ALC is performed using an ALC additional pulse, so that a weak electric field or the like can be used.
ALC can be accurately performed even when the level of the color signal is not stable.

Further, according to the present invention, since ALC is performed on the color signal immediately before entering the adder, level fluctuations such as LPF can be corrected in addition to fluctuations of the CCD. Furthermore,
ADVANTAGE OF THE INVENTION According to this invention, the intermittent color signal of a SECAM system can be converted into the continuous color signal of uniform level. For this reason, the CCD can be used for both PAL distortion correction and SECAM signal continuity, and accurate distortion correction and signal continuity with uniform levels can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a color signal demodulation circuit according to the present invention.

FIG. 2 is a block diagram illustrating a conventional PAL color signal demodulation circuit.

FIG. 3 is a vector diagram for explaining the operation of FIG. 2;

FIG. 4 is a waveform chart for describing the operation of FIG. 1;

FIG. 5 is a waveform chart for describing the operation of FIG. 1;

FIG. 6 is a diagram showing a specific circuit example of a detection circuit (32) and a comparator (35) in FIG. 1;

FIG. 7 is a waveform chart for describing the operation of FIG. 1;

FIG. 8 is a diagram showing a specific circuit example of the SCP determination circuit (103) in FIG. 1;

FIG. 9 is a vector diagram for describing the operation of FIG. 1;

[Explanation of symbols]

 (2) BY demodulator (3) RY demodulator (8) First CCD circuit (9) Second CCD circuit (14) First adder (15) Second adder (38) First ALC circuit (39) ) Second ALC circuit (106) ALC additional pulse generation circuit (108) Switch

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-54-37534 (JP, A) JP-A-52-69227 (JP, A) JP-A-57-48890 (JP, A) 315158 (JP, A) JP-A-54-81029 (JP, A) JP-A-58-6481 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 9/66 H04N 9 / 64

Claims (3)

(57) [Claims] 1. A demodulator for demodulating a color difference signal of the SECAM system, separating means for separating an output signal of the demodulator into two signals of a BY signal and an RY signal, and one of the separating means. An adding means for adding an ALC additional pulse to the color difference signal;
A first CCD that delays by H period, a second CCD that delays the other color difference signal from the demodulator by 1H period, and receives an output of the first CCD as an input signal,
Signal is adjusted in amplitude based on the control signal, and the output signal level is adjusted.
A first ALC circuit for adjusting a bell to an output signal level of the demodulator, and an ALC additional pulse in an output signal of the first ALC circuit;
Level and the ALC additional pulse added by the additional means
And outputs the difference as the control signal.
A comparator and the second CLC in response to the control signal of the first ALC circuit.
A second ALC circuit for adjusting the magnitude of the output signal of the CD; a first adder for adding one color difference signal from the demodulator to an output signal of the first ALC circuit; and another color difference from the demodulator. A color signal demodulation circuit, comprising: a second adder for adding a signal and an output signal of the second ALC circuit. 2. A first demodulator for demodulating a first color difference signal of the PAL system, a second demodulator for demodulating a second color difference signal of the PAL system, and a first demodulator for outputting an output signal of the first demodulator. First adding means for applying the ALC additional pulse of the above, a third demodulator for demodulating the color difference signal of the SECAM system, and an output signal of the third demodulator as a BY signal and an RY signal.
A second ALC at a predetermined position of one of the signals from the separating means.
Second adding means for adding an additional pulse, and at the time of PAL reception , the output signal of the first demodulator to which the first ALC additional pulse has been added is delayed for 1H period,
At the time of CAM reception, the second AL from the third demodulator
A first CCD for delaying the one color difference signal to which the C additional pulse has been added for 1H period, an output signal of the second demodulator for 1H period when receiving PAL , and the other signal from the third demodulator for receiving SECAM. A second CCD for delaying the color difference signal by 1H period, and an output of the first CCD as an input signal;
1st AL which outputs the signal after adjusting the amplitude based on the control signal
C circuit, and at the time of PAL reception, the output signal of the first ALC circuit
The level of the first ALC additional pulse and the first
Level of the first ALC additional pulse added by the adding means.
And outputs the difference as the control signal.
At the time of AM reception, the output signal of the first ALC circuit
The level of the second ALC additional pulse and the second additional
Level of the second ALC additional pulse added by the means
And outputs the difference as the control signal.
And the second C signal in response to the control signal of the first ALC circuit.
A second 2ALC circuit for adjusting the size of the CD of the output signal, the first and the output signal of the first demodulator at the time of PAL reception
And the output signal of the ALC circuit, <br/> during SECAM receiving a first adder for adding the output signal of the first 1ALC circuit and an output signal of the third demodulator, when PAL receiver The output signal of the second demodulator and the second
A second adder for adding an output signal of the ALC circuit and adding an output signal of the third demodulator and an output signal of the second ALC circuit when receiving SECAM. Color signal demodulation circuit. 3. The color signal demodulation circuit according to claim 1, further comprising an additional pulse generator for generating an ALC additional pulse based on a generation timing of a sandcastle pulse.