JP3255084B2 - Package for electronic component, method of manufacturing the same, and electronic component - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for an electronic component, a method of manufacturing the same, and an electronic component, and more particularly to a multilayer package having an array of external connection terminals, a semiconductor device using the same, and a method of manufacturing the same. Is PGA plated by electrolytic plating
The present invention relates to a multilayer package with an array-like external connection terminal such as a (Pin Grid Array) or a BGA (Ball Grid Array), a method of manufacturing the same, and a semiconductor device using the multilayer package.

[0002]

2. Description of the Related Art In recent years, ICs and LSIs have been highly integrated,
More than 500 peripheral terminals have appeared on packages on which ICs and LSIs are mounted.

On the other hand, the speed of ICs and LSIs has been remarkably increased, and the number of packages has been increased in order to suppress deterioration of high-speed signals.

[0004] From these facts, a package is easily packaged from a QFP (Quad Flat Package) having external terminals formed on four sides, and the external terminals are taken out in an array to form a PGA or a multi-pin package. The mainstream is shifting to a multilayer package with terminals for external connection such as a BGA.

[0005] These multilayer packages with terminals for external connection are formed by wire bonding or TAB (Tape Aut).
It is connected to the IC by a method such as omated bonding or flip chip. A conductor portion (semiconductor element connection terminal, hereinafter referred to as a pad) exposed on the package surface for connection with the IC is subjected to plating. Also,
External connection terminals such as pins for connecting to a substrate such as a motherboard are also plated. These plating processes are performed to increase the reliability of the connection.

[0006] Plating is usually performed by forming a Ni film on the surface of a pad portion or a pin, and then forming an Au film thereon. As a plating method, there are two methods of electroless plating and electrolytic plating.

In the electroless plating, a package is immersed in a plating solution in which a metal is dissolved, and a plating film is formed on pad portions and pins of the package by an electrochemical action without using an external current. It is. This method not only eliminates the need for a plating electrode for passing an electric current from the outside, but also provides wiring (hereinafter referred to as a lead wire for plating) for electrically connecting the plating electrode to pads, pins, etc. inside the package. It is unnecessary and has an excellent advantage that plating can be performed only by immersing the package in a plating solution.

However, in the electroless plating process, the life of the plating solution is usually short, the speed of forming a plating film is about 1/10 slower than in the case of the electrolytic plating process, and the plating solution itself is expensive. In view of the above, there is a problem that the plating processing cost is increased.

On the other hand, electrolytic plating has a great advantage that it is inexpensive as compared with electroless plating in that the plating film formation speed is high and the plating solution itself is inexpensive. Is subjected to electrolytic plating.

However, in the electroplating process, a plating film is formed by passing a current through a plating solution, so that a plating electrode for connecting to a power supply and all pads and pins that require the plating process are applied. A plating lead wire for connecting the connected wiring to the plating electrode is required.

The lead wire for plating will be described in detail by taking a ceramic package as an example. FIG. 4 shows a conventional multilayer ceramic P having a plating electrode formed on a side surface of a package.
It is sectional drawing which showed the cross section of GA typically.

In a conventional multilayer ceramic PGA 200, an LSI 14 is mounted in a cavity 12 of a package body 10 made of ceramic. A large number of pins 61 to 6
5 are joined. Inside the package body 10,
A large number of signal lines 222 (only one is shown) are formed to connect a large number of pads (not shown) of the LSI 14 with a large number of pins 61 of the multilayer ceramic PGA 200, respectively. Is formed on the wiring layer 220. The signal line 222 is connected to the via hole 226 at the point E, and the via hole 226 is connected to the pin 61. The signal line 222 has a connection portion E with the via hole 226.
It extends further outward in the horizontal direction toward the outside of the package body 10, and is drawn out to the side surface 11 of the package body 10 of the multilayer ceramic PGA 200 as a lead wire 223 for plating. On the side surface 11 of the package body 10, a plating electrode 70 in which a number of such plating lead wires 223 are short-circuited is formed.

A ground wire 52 is provided over substantially the entire surface of the package body 10, and power supply wires 42 are provided on the four side portions 19 of the package body 10. Ground wiring 5
2 and power supply wiring 42 are via holes 54 and 4 respectively.
4 are connected to pins 62 and 64, respectively. The ground wiring 52 and the power supply wiring 42 are generally planar wirings having a size substantially equal to the package size, and a plating lead wire (not shown) for connecting to the plating electrode 70 exists, but has a length. Is short.

When two wiring layers for providing signal lines for connecting the LSI 14 and the pins are required, as shown in FIG. 5, for example, in addition to the signal lines 222 formed on the wiring layer 220, as shown in FIG. The signal line 232 is also provided in the wiring layer 230. This signal line 232 has a via hole 236 at point F.
, And the via hole 236 is connected to the pin 63. The signal line 232 extends further laterally toward the outside of the package body 10 than the connection portion F with the via hole 236, and serves as a lead wire 233 for plating to form a side surface 11 of the package body 10 of the multilayer ceramic PGA 200.
To the plating electrode 70 on the side surface 11.
Is connected to Other structures are the same as those of the multilayer ceramic PGA 200 shown in FIG.

When performing the electrolytic plating process, the plating electrode 70 is connected to an external power source, and the multilayer ceramic PG is connected.
By immersing A200 in the plating solution and passing a current,
Signal line 22 exposed outside package body 10
2, 232, etc., pad portions 221, 231 and pins 61-61.
65 is subjected to electrolytic plating. In this case, usually, first, after immersing in a plating solution for Ni plating to form a Ni plating film, immersing in a plating solution for Au plating,
An Au plating film is formed on the plating film. After the completion of the plating process, the plating electrode 70 was removed by a method such as polishing to separate the signal lines 222 and 232 from each other.

[0016]

As described above, conventionally, the signal lines 222 and 232 formed on the multilayer ceramic PGA 200 are provided with a lead for plating for electrolytic plating for the purpose other than the transmission of the original signal. Line 223,
233 had been extended.

However, as shown in FIGS. 4 and 5, the plating lead 22 extending to the signal lines 222 and 232 is used.
3 and 233, the lead wire for plating 2
23 and 233 become open stubs, which cause an increase in signal distortion and delay due to reflection.

In particular, in recent years, the clock frequency of ICs and LSIs has been increasing more and more, so that the influence of the lead wires 223 and 233 for plating on the electrical characteristics cannot be ignored, and the factors leading to malfunctions of the ICs and LSIs. There was a problem that is becoming.

As one of the methods for solving this problem, the above-mentioned electroless plating method can be adopted, but there is a disadvantage that the cost is increased.

Therefore, another method is disclosed in Japanese Patent Laid-Open No. 5-19 / 1993.
No. 8718 proposes a method of using external connection terminals (pins) of a multilayer ceramic package as electrodes for electrolytic plating. According to the publication, a thin metal sheet having a through hole with a diameter slightly smaller than the pin is formed as a jig for plating corresponding to the arrangement of pins, and when performing electrolytic plating, the plating jig is used. Each pin is stabbed from above to establish electrical connection between the pins, and one end of the pin is connected to a power source to perform plating.

However, in this method, a special plating jig as described above is required, which leads to an increase in cost, and among the external connection terminals, the pins of the pins which are brought into contact with the plating jig are used. There was a problem that a plating film was not formed at the tip.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-mentioned problems. It is possible to shorten the length of a plated lead wire or the like connected to a wiring that connects between an external connection terminal such as a pin and a ball, and as a result, for example,
Deterioration of electrical characteristics due to plating lead wire can be prevented,
It is an object of the present invention to provide an electronic component package that can be subjected to inexpensive electrolytic plating as in a conventional method, a method of manufacturing the same, and an electronic component using the package.

[0023]

In a package for an electronic component such as a multilayer package, the lead wire for plating is an open stub and acts as a capacitive load as described above. Capacitive loading slows down high speed signal transitions and increases signal distortion and delay. The larger the load capacity, the greater the effect on the signal, and the size is almost proportional to the length of the lead wire for plating.

In a multilayer package having external connection terminals such as pins and balls arranged in an array, the external connection terminals arranged closer to the package center than the external connection terminals closer to the outer periphery of the package. The signal line connected to the connection terminal has a longer lead wire for plating, and the electrical characteristics are more likely to deteriorate. In addition, the larger the package, the longer the lead wire for plating is, and the more likely it is to be affected by this.

Therefore, if the signal line wiring structure is designed so that the long plating lead line connected to the external connection terminal for the signal line arranged on the center side of the package can be shortened, the conventional inexpensive electrolytic plating process can be performed. It was thought that the above problem could be solved by the method.

In general, since the plating electrode is on the side surface of the package, the length of the lead wire for plating must be at least the distance from the terminal for external connection to the outer periphery of the package. This is because the branch point between the signal line and the lead wire for plating is placed in the via hole immediately below the external connection terminal.

If the branch point between the signal line and the lead wire for plating is moved further to the outer peripheral side of the package than the position of the terminal for external connection, the lead wire for plating becomes shorter. For this purpose, for example, the first sub-wiring is formed by using the first wiring layer on which the signal line is formed and extending the signal line further toward the outer periphery than the external connection terminal position. Then, the first via hole is used to draw out from the first wiring layer to the second wiring layer. Further, using the second wiring layer, a signal line is routed from the position of the first via hole to the position of the external connection terminal toward the center of the package to form a second sub-wiring. Further, a second sub-wiring is connected to the external connection terminal using a second via hole.

According to the multilayer package having such a configuration, the position of the first via hole, which is a branch point between the signal line and the lead wire for plating, can be located closer to the outer periphery of the package than the terminal for external connection. Thereby, the length of the lead wire for plating can be shortened. As a result, load capacitance can be reduced, signal distortion and delay can be reduced, and deterioration of electrical characteristics can be reduced. In addition, it is inexpensive because the same electrolytic plating treatment as in the conventional method can be applied.

However, in the present invention, the length of the lead wire for plating is shortened, but the length of the signal line itself is increased, so that the electrical characteristics are degraded if the first and second sub-wirings are performed unnecessarily. Could be done. Therefore, it is preferable to wire these first and second sub-wirings as follows.

In practicing the present invention, it is preferable to increase the electromagnetic coupling between the first sub wiring and the second sub wiring. As a result, the effective electrical parameters (effective inductance and ground capacitance) of the signal line are reduced, and signal distortion and signal delay can be suppressed.

There are two methods for strengthening the electromagnetic coupling between the first sub-wiring and the second sub-wiring.

One method is to make the first sub wiring and the second sub wiring adjacent to each other. For that purpose, it is preferable that the first wiring layer on which the first sub-wiring is formed and the second wiring layer on which the second sub-wiring is formed be adjacent to each other. In this case, it is preferable that the thickness of the dielectric between the first wiring layer and the second wiring layer be smaller than the line width of the signal line (preferably, the thickness is about half of the signal line width). The thinner the bond, the stronger the bond between them. However, if the thickness is too small, a problem of insulation occurs. Therefore, the thickness is preferably about 20 μm or more for a ceramic package and about 10 μm or more for a plastic package.

Another method is to wire the first sub wiring and the second sub wiring in an overlapping manner. When each sub-wiring passes directly above or below the other sub-wiring, the coupling between them becomes maximum.

If the present invention is carried out while paying attention to the above two points,
A multilayer package that is inexpensive and has little deterioration in electrical characteristics can be suitably realized.

The present invention is based on the above findings,
According to claim 1, there is provided a package for an electronic component, on which an electronic element is mounted to form an electronic component, for connecting a package body and an electronic element that is provided to be exposed from the package body and is connected to the electronic element. A terminal, an external connection terminal provided to be exposed from the package body, and a wiring for connecting between the electronic element connection terminal and the external connection terminal provided in the package body, A first wiring on an electronic element connection terminal side, a second wiring on the external connection terminal side, and a serial connection between the first wiring and the second wiring; A sub-wiring provided in the package main body , one end of which is connected to the first wiring and extends from the first wiring toward the outside of the package. Secondary wiring A second sub-wiring having one end connected to the second wiring and extending from the second wiring toward the outside of the package and provided in the package body; A sub-wiring having a connection portion connecting the other end of the wiring and the other end of the second sub-wiring,
And the package book from the sub-wiring.
Extending inside the package body to the outside of the body
And a lead wire for plating .

By providing such sub-wirings, for example, plating lead lines for electrolytic plating external connection terminals and electronic element connection terminals provided to be exposed from the package body are provided in the package body. In this case, the length of the plating lead line can be shortened by connecting the plating lead line to the sub wiring,
As a result, signal distortion and delay are reduced, and deterioration of electrical characteristics due to the lead wire for plating can be suppressed. In addition, by connecting such a lead wire for plating to a plating electrode provided so as to be exposed from the package body, an external connection terminal and an electronic element connection terminal can be easily and inexpensively connected through the plating electrode. It can be electroplated.

[0037]

According to claim 2 , the first sub-wiring is formed in a first wiring layer, and the second wiring layer is formed in a second wiring layer different from the first wiring layer. 2. The electronic component package according to claim 1, wherein the connecting portion is a via hole connecting the other end of the first sub-wiring and the other end of the second sub-wiring. 3. Provided.

According to a third aspect, when the electronic component package is viewed in a plan view, the first wiring extends from the electronic element connection terminal to the position of the external connection terminal or in the vicinity thereof. The first sub-wiring extends from or near the position of the external connection terminal toward the outside of the package, and the other end of the first sub-wiring and the second sub-wiring Are connected to each other by a first via hole, the second sub wiring extends from the first via hole to or near the position of the external connection terminal, and the second wiring is A second via hole provided at or near the position of the connection terminal, wherein the one end of the second sub-wiring and the external connection terminal are the second via hole;
3. The electronic component package according to claim 1, wherein the electronic component package is connected by a via hole.

Further, according to claim 4, for electronic components according to any one of claims 1 to 3 and the first auxiliary wiring and the second sub-wiring is characterized in that adjacent Package is provided.

According to the fifth aspect , the first sub-wiring is formed in a first wiring layer, and the second sub-wiring is formed in a second wiring layer different from the first wiring layer. The thickness of the dielectric layer formed between the first wiring layer and the second wiring layer is from about 20 μm to 1st and 2nd when the dielectric layer is ceramic. About half the line width of the wiring layer, and about 10 when the dielectric layer is plastic.
5. The electronic component package according to claim 4, wherein the thickness is from about μm to about half of the line width of the first and second wiring layers. 6.

By making the first sub wiring and the second sub wiring adjacent to each other, the electromagnetic coupling between the first sub wiring and the second sub wiring can be strengthened.
Effective electrical parameters (effective inductance and ground capacitance) of the first and second sub-wirings are reduced, and signal distortion and signal delay can be reduced.

Further, a first sub-wiring is formed in a first wiring layer, and a second sub-wiring is formed in a second wiring layer different from the first wiring layer.
When formed on the first wiring layer, the thickness of the dielectric layer existing between the first wiring layer and the second wiring layer may be smaller than the line width of the first and second sub-wirings. The thinner the film, the stronger the coupling between the two. Therefore, the thinner the better, the better the line width of the first and second sub-wirings is preferably about half or less. Preferably, the thickness is about 20 μm or more in the case of ceramic, and about 10 μm or more in the case where the dielectric layer is plastic.

According to claim 6 , the first sub-wiring is formed in a first wiring layer, and the second sub-wiring is formed in a second wiring layer different from the first wiring layer. The first sub-wiring and the second sub-wiring are formed so as to face each other, and when the electronic component package is viewed in a plan view, the first sub-wiring and the second sub-wiring are formed. The electronic component package according to any one of claims 1 to 5 , wherein the sub-wirings are arranged so as to overlap with each other.

With this arrangement, the first sub-wiring and the second sub-wiring pass each other directly above or below each other, so that the coupling between them becomes maximum.

Preferably, when the electronic component package is viewed in a plan view, one main surface of the first sub-wiring and one main surface of the second sub-wiring are arranged so as to overlap with each other.

According to a seventh aspect of the present invention, a plurality of the external connection terminals, the plurality of electronic element connection terminals, and the plurality of wirings are provided, and each of the plurality of electronic element connection terminals is connected to the plurality of external connection terminals. Corresponding to each of the terminals,
The plurality of wirings are respectively provided to connect between each of the plurality of electronic element connection terminals corresponding to each other and each of the plurality of external connection terminals, and the plurality of external connection At least one of the external connection terminals disposed at least inside the electronic component package among the terminals, and the one or more external connection terminals disposed inside the electronic component package.
1 corresponding to each of the above-described external connection terminals.
Each of the one or more sub-wirings is connected in series between the first wiring and the second wiring of each of the one or more wirings respectively connecting the electronic device connection terminals. The electronic component package according to any one of claims 1 to 6 , wherein the electronic component package is provided so as to be connected to the electronic component.

In a package including a plurality of external connection terminals and a plurality of corresponding electronic element connection terminals as described above, for example, an external connection terminal or an electronic element connection terminal provided to be exposed from the package body. When providing plating lead wires for electrolytic plating of terminals in the package body, plating provided for external connection terminals located inside the package rather than external connection terminals near the package outer periphery The length of the lead wire is longer and the electrical characteristics are likely to deteriorate. Therefore, by connecting the sub-wiring in series between the first wiring and the second wiring of the wiring corresponding to the external connection terminal arranged at least inside the electronic component package, the plating lead wire is provided. Since the length of the lead is long, the length of the lead wire for plating in the portion where the electrical characteristics are likely to deteriorate can be shortened, so that the electrical characteristics of the electronic component package can be prevented from deteriorating. The external connection terminals for connecting the sub-wirings need not be limited to those arranged inside the electronic component package, and the sub-wirings may be provided corresponding to all the external connection terminals.

Further, if a plating electrode commonly connected to a plurality of plating lead lines respectively corresponding to the plurality of external connection terminals is provided so as to be exposed from the package body, a plurality of external connection terminals are provided via the plating electrode. Terminals and a plurality of electronic element connection terminals corresponding thereto can be electrolytically plated at the same time.

Preferably, at least one of the external connection terminal and the electronic element connection terminal is subjected to electrolytic plating.

Preferably, both the external connection terminal and the electronic element connection terminal are subjected to electrolytic plating.

Preferably, at least one of a ground wiring and a power supply wiring is provided so as to cover the wiring and the sub wiring substantially entirely.

Note that both the ground wiring and the power supply wiring
It is more preferable that the wiring and the sub-wiring are provided so as to cover almost the entirety. More preferably, the wiring and the sub-wiring are provided so as to be sandwiched by both a ground wiring and a power supply wiring.

According to claim 8 , according to claims 1 to 7,
An electronic component comprising: the electronic component package according to any one of the above, and an electronic element mounted on the electronic component package.

According to a ninth aspect of the present invention, in a method of manufacturing an electronic component package in which an electronic element is mounted to constitute an electronic component, the package body is connected to the electronic element provided to be exposed from the package body. Electronic device connection terminal, an external connection terminal exposed from the package body, and connecting between the electronic element connection terminal and the external connection terminal provided in the package body. A wire connected in series between the first wire on the electronic element connection terminal side, the second wire on the external connection terminal side, and the first wire and the second wire; A sub-wiring provided in the package body, one end of which is connected to the first wiring and which extends from the first wiring to the outside of the package to form a sub-wiring. And a first sub-wiring provided inside the package main body, one end of which is connected to the second wiring and extends from the second wiring toward the outside of the package. A second sub-wiring, a sub-wiring having a connecting portion for connecting the other end of the first sub-wiring and the other end of the second sub-wiring, A lead wire for plating provided to extend inside the package body toward the outside of the package body, a plating electrode exposed from the package body and provided in connection with the lead wire for plating,
An electronic component, comprising: a step of preparing a package comprising: and a step of performing electrolytic plating on at least one of the external connection terminal and the electronic element connection terminal via the plating electrode. A method of manufacturing a package for use is provided.

With this configuration, the external connection terminal and the electronic element connection terminal can be electrolytically plated through the plating electrode exposed from the package body and the plating lead wire connected thereto. Electrolytic plating of external connection terminals and electronic element connection terminals can be performed easily and at low cost. Preferably, both the external connection terminal and the electronic element connection terminal are electrolytically plated.

In the electronic component package manufactured as described above, since the plating lead is connected to the sub wiring, the length of the plating lead is reduced. In addition, signal distortion and delay are reduced, and deterioration of electrical characteristics due to plating lead lines is suppressed.

According to the present invention, in a method of manufacturing an electronic component package in which an electronic element is mounted to constitute an electronic component, a package body is connected to the electronic element provided to be exposed from the package body. A plurality of electronic element connection terminals, and a plurality of external connection terminals provided so as to be exposed from the package body, wherein each of the plurality of external connection terminals is a plurality of the electronic element connection terminals. A plurality of external connection terminals provided corresponding to each of the plurality of external element terminals; and a plurality of wirings provided in the package body, wherein the plurality of wirings correspond to the plurality of electronic element connections, respectively. Connection between each of the external terminals and each of the plurality of external connection terminals, and each of the plurality of interconnections is a first interconnection on the electronic element connection terminal side. A second wiring on the side of the external connection terminal, and a plurality of sub-wirings provided in the package body, wherein each of the plurality of sub-wirings is connected to the first wiring of each of the plurality of wirings. Each of the plurality of sub-wirings is connected in series with the second wiring, and one end of each of the plurality of sub-wirings is connected to the first wiring and from the first wiring toward the outside of the package. A first sub-wiring extending in the package body and one end connected to the second wiring and extending from the second wiring toward the outside of the package; A plurality of sub-wirings each having a second sub-wiring provided in the main body, and a connection portion connecting the other end of the first sub-wiring and the other end of the second sub-wiring, Each of the plurality of wirings and the plurality of plating An out-ray,
The plurality of plating lead lines, wherein each of the plurality of plating lead lines is provided to extend inside the package body from each of the plurality of sub-wirings toward the outside of the package body; and A step of preparing a package including a plating electrode exposed from the main body and provided in common with the plurality of plating lead lines, and the plurality of external connection terminals and Performing an electrolytic plating on at least one of the plurality of electronic element connection terminals,
After the electrolytic plating, a step of cutting off the plating electrode and the plurality of plating leads.

As described above, by providing the plating electrodes which are commonly connected to the plurality of plating lead lines respectively corresponding to the plurality of external connection terminals and exposed from the package body, the plating electrodes and the plating lead lines are provided. A plurality of external connection terminals and a plurality of corresponding electronic element connection terminals can be easily and inexpensively electroplated simultaneously. Preferably, both the plurality of external connection terminals and the plurality of electronic element connection terminals respectively corresponding thereto are electrolytically plated.

In the electronic component package manufactured as described above, each of the plurality of plating leads is connected to each of the plurality of sub-wirings. The length is shortened, and as a result, signal distortion and delay are reduced, and deterioration of electrical characteristics due to the lead wire for plating is suppressed.

In the present invention, the electronic element is an IC, L
It is particularly suitably applied to a semiconductor active device such as SI.

Further, the present invention is suitably applied to a multilayer package having an array-like external connection terminal in which external connection terminals are provided in an array, and an electronic component using the same. It is particularly preferably applied.

[0063]

Embodiments of the present invention will now be described with reference to the drawings, taking a multilayer ceramic PGA as an example.

(First Embodiment) FIG. 1 is a schematic partial sectional view for explaining a multilayer ceramic PGA according to a first embodiment of the present invention, and shows a state at the stage of performing electrolytic plating. It is shown.

First, the multilayer ceramic PGA1 in this state
00 will be described first.

First, a slurry is prepared by mixing alumina powder, a sintering aid, a binder resin, a solvent such as xylene, and other additives.

Next, the slurry is applied in a sheet form on a polyester sheet or the like by a doctor blade method.
This is dried to produce a ceramic green sheet.

Next, the ceramic green sheet is cut into a predetermined size, subjected to a perforation process in accordance with each layer of the package, and printed with a conductor paste mainly composed of a high melting point metal such as tungsten in a predetermined pattern. Along with
The through-holes serving as via holes are filled with the conductive paste, and several to several tens of ceramic green sheets subjected to such treatment are laminated.

Next, heat treatment is performed in an inert gas atmosphere to decompose and eliminate the organic components such as the resin and the plasticizer in the ceramic green sheet, followed by firing to produce a multilayer ceramic substrate. The signal wiring 27, 28, 25, the power wiring 4
2, the conductor layers such as the ground wiring 52 and the lead electrode 23 for plating are formed, and the via holes 24, 26, 4
4, 54, etc. are also formed.

Next, a number of pins 61 to 65 serving as external connection terminals are joined to the pin joining surface 15 on the upper part of the multilayer ceramic substrate (package main body 10) manufactured as described above.

In the multilayer ceramic PGA 100 manufactured in this embodiment, an LSI 14 is mounted in a cavity 12 of a package body 10 made of ceramic.
This is a package having a structure called “cavity down” in which the mounting surface 13 of the SI 14 and the pins 61 to 65 are on the same surface side, and the signal wiring layers 122 and 124, the power supply wiring layer 40, and the ground wiring layer 50 are stacked at 55 mm. It is a 280 pin PGA with a corner.

The package body 10 contains an LSI 1
4 and a multi-layer ceramic PG
A100 has a large number of signal lines 20 formed for connection to a large number of pins 61 and the like.
Book only) is formed.

Of the many signal lines 20, the plurality of signal lines 20 corresponding to the pins 61 arranged at the center of the package body 10 are the signal lines 22 formed on the signal wiring layer 122.
And the signal lines 25 and 2 formed in the signal wiring layer 124
Via hole 24 connecting signal line 2 and signal line 25 and signal line 2
5 and a via hole 26 for connecting the pin 61. An inner portion of the signal line 22 is exposed inside the cavity 12 and serves as a pad 21.

The signal line 22 extends from the pad 21 to the position A of the pin 61 toward the outer peripheral side of the package body 10 from the signal line 27 which is the first wiring and the position A of the pin 61 to the package body 10. And a signal line 28 which is a first sub-wiring extending toward the outer peripheral side. The signal line 28 which is the first sub- wiring formed in the signal wiring layer 122 is formed at the position B by the second hole formed in the signal wiring layer 124 by the via hole 24 which is the connecting portion.
Are connected to a signal line 25 which is a sub-wiring. Signal line 2
5 is pulled back from the position B to the position A of the pin 61, and is connected to the pin 61 at the position A by the via hole 26 as the second wiring.

The signal wiring layer 122 is further provided with a lead wire 23 for plating, and the lead wire 23 for plating is drawn from the position B where the via hole 24 is provided to the side surface 11 of the package body 10. . Then, on the side surface 11 of the package body 10, the plating electrode 7 in which a large number of such plating lead wires 23 are short-circuited.
0 is formed. Note that the lead wire 11 for plating may be formed in the signal wiring layer 124.

Such signal lines 28 and 25 are provided on other signal lines 20, that is, a plurality of signal lines 20 corresponding to pins arranged on the outer peripheral side of the package main body 10 among many signal lines 20. 3, a signal line is drawn out to a position corresponding to a pin arranged on the outer peripheral side of the package body 10, and is connected to the pin by a via hole at that position, as shown in FIG. The plating lead line also extends from the position of the via hole to the side surface 11 of the package body and is connected to the plating electrode 70.

Ground wiring 52 is provided on ground wiring layer 50 over substantially the entire surface of package body 10, and power supply wiring 4 is provided.
Reference numeral 2 denotes four sides of the package body 10 (four sides excluding the center cavity 12 from the package body 10).
Nine power supply wiring layers 40 are provided over substantially the entire surface. The ground wiring 52 and the power supply wiring 42 are connected to pins 62 and 64 via via holes 54 and 44, respectively. The ground wiring 52 is a planar wiring that is substantially the same as the four side portions 19, and the power supply wiring 42 is a planar wiring that is substantially the same as the package size. There are wires (not shown), which are connected to the plating electrodes 70, which are short. Further, the signal lines 27, 28 and 25 are sandwiched substantially over the entire surface by the ground wiring 52 and the power supply wiring 42.

Next, the plating electrode 70 is connected to an external power supply, and nickel plating containing nickel sulfate and nickel chloride as main components is performed.
Immerse the multilayer ceramic PGA10 in the plating solution to a few μm
Is formed on the surfaces of all the pins 61 to 65 and the surfaces of all the pads 21. Next, the Ni coating is washed with pure water, and the multilayer ceramic PGA100 is immersed in a gold plating bath solution to form Au plating coatings having a thickness of several μm on the Ni coating surfaces of the pins 61 to 65 and the Ni coating surface of the pad 21, respectively. And then wash.

Thereafter, by removing the plating electrode 70 by a method such as polishing, the signal lines 20, the power supply wiring 42, and the ground wiring 52 are separated from each other to form a multilayer ceramic P.
The GA 100 is completed.

Finally, the LSI 14 is mounted on the LSI mounting surface 13 in the cavity 12, and the pad 21 and the LSI 14 are mounted.
Bonding wire 8 between the pad and a pad (not shown).
1 is bonded.

In this embodiment, the plating electrode 7
0 to the power supply, the plating electrode 70, the plating lead electrode 23, the ground wiring 52 and the power supply wiring 42.
Since the surfaces of all the pins 61 to 65 and the surfaces of all the pads 21 can be simultaneously electroplated via a lead wire (not shown) for plating, the plating can be performed easily and inexpensively.

Further, since no special jig for contacting the pins or the like is required, a plating film can be formed on the entire surface of the pins and pads.

Further, the lead wire 23 for plating is not located at the position A of the pin 61 but is located at a position
0, only extends from the position B on the outer peripheral side to the side surface 11, so that its length is short. As a result, the load capacitance of the lead wire 23 for plating is reduced, and signal distortion and delay are reduced. Deterioration of the electrical characteristics due to the lead wire for plating 23 is suppressed.

Then, between the position A and the position B,
The signal line 28 and the signal line 25 are arranged to face each other and to be parallel to each other with the ceramic layer 90 interposed therebetween. When the ceramic OGA 100 is viewed from above (the pin joint surface 15 side), the ceramic OGA 100 is in an overlapping state. Are located. The line widths of the signal line 28 and the signal line 25 are substantially the same. The ceramic layer 90 between the signal line 28 and the signal line 25
Is about half or less of the line width of the signal lines 28 and 25. Therefore, the electromagnetic coupling between the signal line 28 and the signal line 25 is strengthened. As a result, the effective electric parameters (effective inductance and ground capacitance) of the signal line 28 and the signal line 25 are reduced, and signal distortion and Signal delay is reduced. Therefore, the signal line 28 and the signal line 25 are
, The electrical characteristics are suppressed or prevented from deteriorating even if the length of the signal line 20 is increased.

The package body 1 of the signal lines 20
No signal lines 28 and 25 are provided on the signal line 20 corresponding to the pins arranged on the outer peripheral side of 0, but in this case, since the pins are arranged on the outer peripheral side, Even if the plated lead is extended from the pin position to the side surface 11 of the package body, its length is short. As a result, the load capacity of the plated lead is not large, and the signal distortion and delay are not large. Also, the deterioration of the electrical characteristics due to the lead wire for plating is not large. However, the signal lines 28 and 25 may be provided for all the pins connected to the signal lines in the same manner as the pins 61 arranged at the center of the package body 10.

(Second Embodiment) When a wiring layer for providing a signal line for connecting the LSI 14 and a pin is further required, as shown in FIG.
A signal line 30 is further provided in addition to the signal lines 20 formed on 22 and 124. The signal line 30 is connected to the signal wiring layer 13
2, a signal line 35 formed in the signal wiring layer 134, a via hole 34 connecting the signal line 32 and the signal line 35, and a via hole 36 connecting the signal line 35 and the pin 63. ing. The inner part of the signal line 32 is exposed inside the cavity 12 and serves as a pad 31. The pad 31 is bonded to a pad (not shown) of the LSI 14 with a bonding wire 82.

The signal line 32 extends from the pad 31 to the position C of the pin 63 toward the outer peripheral side of the package body 10 as the first wiring and the position C of the pin 63 to the signal line 37. And a signal line 38 which is a first sub-wiring extending toward the outer peripheral side. The signal line 38 formed in the signal wiring layer 132 is connected at a position D to the signal line 35 as a second sub wiring formed in the signal wiring layer 134 by a via hole 34 as a connection portion. The signal line 35 is pulled back from the position D to the position C of the pin 63, and is connected to the pin 63 at the position C by a via hole 36 as a second wiring.

The signal wiring layer 132 is further provided with a lead wire 33 for plating, and the lead wire 33 for plating is drawn from the position D where the via hole 34 is provided to the side surface 11 of the package body 10. . Then, the side surface 11 of the package body 10 is connected to the plating electrode 70. Note that the plating lead 33 may be formed in the signal wiring layer 134.

Another structure is the multilayer ceramic P shown in FIG.
Same as GA100.

Also in the present embodiment, the plating electrode 7
0 is connected to a power supply, and the surfaces of all the pins 61 to 65 are passed through the plating electrode 70, the plating lead lines 23 and 33, and the plating lead lines (not shown) for the ground wiring 52 and the power supply wiring 42. And all pads 21,
Since the surfaces of 31 can be electrolytically plated at the same time, plating can be performed easily and at low cost.

Further, since a special jig for contacting the pins and the like is not required, a plating film can be formed on the entire surface of the pins and the pads.

Further, the lead wire 23 for plating is not located at the position A of the pin 61 but at a position closer to the package body 1 than the position A.
0 only extends from the position B on the outer peripheral side to the side surface 11, and the lead wire 33 for plating is not at the position C of the pin 63 but at the position D on the outer peripheral side of the package body 10 from the position C. Therefore, the length of the plating lead lines 23 and 33 is short, and as a result, the load capacity of the plating lead lines 23 and 33 is reduced, and signal distortion and delay are reduced. Therefore, the deterioration of the electrical characteristics due to the lead wire for plating is suppressed.

Then, between the position A and the position B,
The signal line 28 and the signal line 25 are arranged to face each other and to be parallel to each other with the ceramic layer 90 interposed therebetween. When the ceramic OGA 100 is viewed from above (the pin joint surface 15 side), the ceramic OGA 100 is in an overlapping state. Are located. The line widths of the signal line 28 and the signal line 25 are substantially the same. The ceramic layer 90 between the signal line 28 and the signal line 25
Is about half or less of the line width of the signal lines 28 and 25. Between the position C and the position D, the signal line 38 and the signal line 35 sandwich the ceramic layer 92 therebetween.
The ceramic P
The GAs 100 are arranged in an overlapping state when viewed from above the paper. The line widths of the signal line 38 and the signal line 35 are substantially the same. The thickness of the ceramic layer 92 between the signal line 38 and the signal line 35 depends on the thickness of the signal line 38 or the signal line 3.
5 is almost half or less of the line width. Therefore, the electromagnetic coupling between the signal line 28 and the signal line 25 is strengthened. As a result, the effective electric parameters (effective inductance and ground capacitance) of the signal line 28 and the signal line 25 are reduced, and signal distortion and Signal delay is reduced. Also, the signal line 38
Electromagnetic coupling between the signal line 35 and the signal line 35 is increased, and as a result, effective electric parameters (effective inductance and ground capacitance) of the signal line 38 and the signal line 35 are reduced, and signal distortion and signal delay are reduced. . Therefore, even if the signal line 28 and the signal line 25 are provided and the signal line 20 is long, the signal line 38 and the signal line 35 are provided and the signal line 30 is long. Even so, the deterioration of the electrical characteristics is suppressed or prevented.

[0094]

Next, the lead wire for plating 23 formed in the multilayer ceramic PGA 100 of the first embodiment will be described.
The effect of the signal on the signal delay was analyzed and evaluated. The analysis target is
Multilayer ceramic PGA10 according to the first embodiment
0 from the pad 21 of one signal line 20 to the tip of the pin 61.

The frequency characteristic (10 MHz) of the S parameter of the signal line 20 is determined by the structural analysis using the finite element method.
３3 GHz), and based on the extracted signal waveform, an output signal waveform when a rectangular wave was input to the signal line 20 as an input signal was obtained from a circuit simulation to evaluate the signal delay. The conditions of the circuit simulation are as follows. The output resistance of the input signal is set to 50Ω, and the input signal is input from the pad 21 side.
The signal delay at the tip was evaluated. Note that the signal delay time is such that the rise of the output signal is 65 times the signal amplitude (1 V).
% (0.65 V).

The length of the analyzed signal line 20 is the signal line 22
Was 28 mm, the signal line 25 was 18 mm, their line width was 100 μm, the characteristic impedance was about 50Ω, and the length of the lead wire 23 for plating was 2 mm.
The thickness of the alumina ceramic 90 sandwiched between the signal lines 22 and 25 was 50 μm, which was half the signal line width.

The multilayer ceramic PG according to the present embodiment is
In order to compare the signal delay time of A100 with the conventional method, as a comparative example, the branch point of the signal line 222 and the plating lead line 223 shown in FIG. 4 is a via hole 226 formed immediately below the pin 61. Multilayer ceramic PG
The signal delay time was evaluated in the same manner for A200 plated.

Multilayer ceramic PGA200 according to comparative example
The position of the pin 61 was the same as that of the embodiment of the present invention, the length of the signal line 222 was 10 mm, its line width was 100 μm, and the length of the lead wire 223 for plating was 20 mm.

As a result of the analysis, the signal delay time of the multilayer ceramic PGA 100 according to the present example was smaller than that of the multilayer ceramic PGA 200 according to the comparative example by about 147 p (pico) seconds.

As is clear from the above results, in the case of the multilayer ceramic PGA 100 according to the present embodiment, the position B of the via hole 24 serving as a branch point of the signal line 22 and the lead wire 23 for plating is shifted from the position A of the pin 61. Also, since it was moved to the outer periphery of the PGA, the lead wire 23 for plating was shortened, and the load capacity was reduced, so that the signal delay time could be shortened as compared with the conventional method.

As described in detail above, in the multilayer package according to the present invention, in a multilayer package having an array of external connection terminals requiring plating, it is a branch point between a signal line and a plating lead line. By setting the via hole position closer to the package outer periphery than the pin position, the lead wire length for plating is shortened, and the load capacitance of the lead wire for plating is reduced, so that the signal delay time is reduced compared to the conventional method. Could be shortened.

Further, since the electroplating treatment is performed in exactly the same manner as in the conventional method, it can be manufactured at low cost.

[0103]

According to the electronic component package and electronic component of the present invention, since the sub-wiring is provided, for example, external connection terminals and electronic element connection terminals provided to be exposed from the package body are provided. When providing plating lead wires for electrolytic plating in the package body,
By connecting the plating lead to the sub-wiring, the length of the plating lead can be shortened. As a result, signal distortion and delay can be reduced, and deterioration of electrical characteristics due to the plating lead can be suppressed. . In addition, by connecting such a lead wire for plating to a plating electrode provided so as to be exposed from the package body, an external connection terminal and an electronic element connection terminal can be easily and inexpensively connected through the plating electrode. It can be electroplated.

Further, according to the method for manufacturing an electronic component package and the method for manufacturing an electronic component of the present invention, the plating electrode exposed from the package body and the plating lead wire connected to the plating electrode are provided. Since the external connection terminal and the electronic element connection terminal can be electrolytically plated, the external connection terminal and the electronic element connection terminal can be easily and inexpensively electroplated. In the electronic component package and electronic component manufactured as described above, since the plating lead wire is connected to the sub wiring, the length of the plating lead wire is reduced,
As a result, signal distortion and delay are reduced, and deterioration of electrical characteristics due to the lead wire for plating is suppressed.

[Brief description of the drawings]

FIG. 1 shows a multilayer ceramic P according to a first embodiment of the present invention.
FIG. 3 is a partial cross-sectional view for explaining a GA.

FIG. 2 shows a multilayer ceramic P according to a second embodiment of the present invention.
FIG. 3 is a partial cross-sectional view for explaining a GA.

FIG. 3 is a diagram illustrating a signal delay time according to an embodiment of the present invention.

FIG. 4 is a partial cross-sectional view illustrating an example of a conventional multilayer ceramic PGA.

FIG. 5 is a partial cross-sectional view for explaining another example of the conventional multilayer ceramic PGA.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Package main body 11 ... Side surface 12 ... Cavity 13 ... LSI mounting surface 14 ... LSI 15 ... Pin joining surface 19 ... Side part 20, 22, 25, 27, 28, 30, 32, 35, 3
7, 38, 222, 232 ... signal lines 21, 31, 221, 231 ... pads 23, 33, 223, 233 ... plating lead lines 24, 26, 34, 36, 44, 54, 226, 236
... via hole 40 ... power supply wiring layer 42 ... power supply wiring 50 ... ground wiring layer 52 ... ground wiring 61-65 ... pin 70 ... plating electrode 90,92 ... ceramic layer 100,200 ... multilayer ceramic PGA 122,124,132,134 ... Signal wiring layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 23/12 H01L 23/50

Claims (9)

(57) [Claims] An electronic component package comprising an electronic component mounted thereon to constitute an electronic component, comprising: a package body; and an electronic element connection terminal provided to be exposed from the package body and connected to the electronic element. An external connection terminal provided to be exposed from the package body; and a wiring provided in the package body to connect between the electronic element connection terminal and the external connection terminal, wherein the electronic element first wiring of the connection terminal side, and the external connection terminal side second wiring, provided in the package body is connected in series between the first wiring and the second wiring in was sub-wiring
A first sub-wiring having one end connected to the first wiring and extending from the first wiring toward the outside of the package and provided in the package body; A second sub-wiring connected to a second wiring and extending from the second wiring toward the outside of the package and provided in the package body; and the other end of the first sub-wiring. When a connecting portion for connecting the other end of the second sub-wiring, the the sub wiring having a said wiring having a front toward the outside of the package body from the sub-wiring
A plating pull extending through the package body
And a lead wire . 2. The method according to claim 1, wherein the first sub-wiring is formed in a first wiring layer.
Wherein the second sub-wiring is different from the first wiring layer.
2 is formed on the second wiring layer, and the connection portion is formed on the first sub-wiring.
Is connected to the other end of the second sub-wiring.
Electronic component package according to claim 1, wherein the Oh Rukoto via holes. 3. A plan view of the electronic component package.
When the first wiring is connected to the electronic element connection terminal.
Extending to or near the position of the external connection terminal from
And the first sub-wiring is located at the position of the external connection terminal.
Extends from the vicinity to the outside of the package
The other end of the first sub-wiring and the second sub-wiring
The other end is connected by a first via hole, and the second
The sub-wiring extends from the first via hole to the external connection terminal.
, Or the vicinity thereof, and the second wiring
The third terminal provided at or near the position of the external connection terminal
2 via holes, the one end of the second sub-wiring and
The external connection terminal is connected by the second via hole.
Electronic component package according to claim 1, wherein that it has been continued. 4. The semiconductor device according to claim 1, wherein said first sub wiring and said second sub wiring are
Electronic component package according to any one of claims 1 to 3, wherein that you have adjacent. 5. The semiconductor device according to claim 1, wherein said first sub-wiring is formed in a first wiring layer.
Wherein the second sub-wiring is different from the first wiring layer.
2 and the first wiring layer and the second wiring layer.
The thickness of the dielectric layer existing between the dielectric layer and the wiring layer is
When the layer is ceramic, the thickness is about 20 μm to
About half the line width of the second wiring layer and the dielectric layer
In the case of a plastic, the first and second
2 about the electronic component package of claim 4, wherein half characterized by der Rukoto line width of the wiring layer. 6. The first sub-wiring is formed in a first wiring layer, and the second sub-wiring is formed in a second wiring layer different from the first wiring layer. The sub-wiring and the second
The sub-wirings are arranged facing each other, and the electronic component
When the package is viewed in plan, the first sub-wiring is
The second electronic component package according to any one of claims 1 to 5 sub-wiring and is characterized that you have been disposed to overlap. 7. The external connection terminal and the electronic element connection
A plurality of terminals and the wiring are provided, and each of the plurality of electronic element connection terminals is connected to the plurality of external devices.
The plurality of electronic element connection terminals respectively corresponding to the connection terminals and corresponding to each other.
And between each of the plurality of external connection terminals.
Each of the plurality of wirings is provided for connection.
At least the electronic part of the plurality of external connection terminals
One or more of said external connections arranged inside a product package.
Each of the connection terminals and the one or more
One or more terminals respectively corresponding to each of the external connection terminals
1 for connecting each of the electronic element connection terminals
The first wiring and the second wiring of each of the above wirings
Each of the one or more sub-wirings is connected in series
It is characterized by being et provided connected in claim 1
7. The electronic component package according to any one of claims 1 to 6. 8. An electronic part according to claim 1,
Product package and the electronic component package
An electronic component comprising: an electronic device; 9. An electronic component comprising an electronic element and constituting an electronic component.
In the method of manufacturing a package for a child component, a package body and the electronic element provided so as to be exposed from the package body
An electronic element connection terminal connected to an external connection externally provided from the package body.
A terminal and the electronic element connection end provided in the package body.
Wiring between the terminal and the external connection terminal.
A first wiring on the electronic element connection terminal side, a second wiring on the external connection terminal side, and a serial connection between the first wiring and the second wiring.
In sub wiring provided in the package body with the
And one end connected to the first wiring and the first wiring.
Extending from the wire to the outside of the package,
A first sub-wiring provided in the package body, one end of which is connected to the second wiring;
Extending from the wire to the outside of the package,
Connecting a second sub-wiring provided in the package body to the other end of the first sub-wiring and the other end of the second sub-wiring;
A connecting portion for the a sub wiring having a said wiring having a front toward the outside of the package body from the sub-wiring
A plating pull extending through the package body
Lead wire and the plating lead exposed from the package body.
Preparing a package including a plating electrode provided in connection with the lead-out line; and forming the external connection terminal and the front through the plating electrode.
At least one of the electronic device connection terminals has an electrolytic
Manufacture of electronic component package, characterized in that it comprises a step of performing Tsu key, the
Method.