JP3264922B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having an electrode wiring forming step including a metal silicide layer.

(Prior Art) Conventionally, polycrystalline silicon has been widely used as an electrode wiring material of a semiconductor device. However, polycrystalline silicon has higher resistance than metals such as Al even when impurities are doped at a high concentration. For this reason, large-scale integrated circuits (LSI)
Signal delay due to the resistance of the polysilicon electrode wiring has become a problem. In particular, large capacity and high integration are progressing.
In a MOS LSI, polycrystalline silicon used for a gate electrode is commonly used for the first layer wiring, and its resistance is an obstacle to high-speed operation.

Therefore, recently, a refractory metal silicide exhibiting thermal stability and electrical low resistance has been used as an electrode wiring material instead of polycrystalline silicon.

Fig. 3 shows a MOS using metal silicide for the gate electrode.
3 shows a structure of a transistor. p-type silicon substrate
Gate oxide film in the region surrounded by field oxide film 32
A gate electrode 36 is formed via 33. Gate electrode
Here, reference numeral 36 denotes a laminated structure of a polycrystalline silicon layer 34 and a tungsten silicide (WSi) layer 35. Source and drain layers 37 and 38 are formed by ion implantation of impurities using the gate electrode 36 as a mask. Gate electrode 3
The surface of 6 is covered with an oxide film 39 by post-oxidation.

FIG. 3 shows a state in which the WSi layer 35 used for the gate electrode 36 has peeled off. When silicide is used for the electrode wiring, such peeling often occurs. This is because the gas trapped in the silicide layer 35 in the post-oxidation step after the formation of the gate electrode expands and bursts. The process leading to such peeling of the electrodes will be described in detail below.

As described above, the source and drain of the MOS transistor are formed by ion implantation after patterning the gate electrode. Prior to this ion implantation, a thin oxide film is formed on the substrate surface and the gate electrode surface. This is to prevent damage to the substrate due to ion implantation and to prevent outward diffusion of impurities during impurity activation heat treatment after ion implantation. In the case of a CMOS structure, the source and drain impurities are usually separated using a photoresist mask. However, the thin oxide film described above also has the purpose of preventing the photoresist from directly contacting the substrate in this case. is there. In order to perform ion implantation with a short ion range of 200 to 300 °, the oxide film needs to be as thin as about 100 °. Further, in order to prevent the gate breakdown voltage and the junction from being deteriorated, it is necessary to form this oxide film at a high temperature. From this point of view, this oxide film formation
For example, in a nitrogen-diluted atmosphere (N ₂ -10% O ₂ ),
It is performed under conditions such as ~ 60 minutes.

After the ions are implanted into the source and the drain, a thermal oxide film is formed on the surface of the gate electrode, that is, post-oxidation is performed in a dry oxygen atmosphere in order to improve the gate breakdown voltage and improve the gate characteristics. Thereafter, in the oxidation step, blisters and bursts occur due to gasification of impurities taken into the silicide layer of the gate electrode and further expansion of the gas volume, as shown in FIG. Peeling occurs. Specifically, what is incorporated in the silicide layer is argon (Ar) or WF ₆ when the silicide layer is formed by sputtering.
Fluorine (F) when formed by a CVD method using a gas, arsenic (As) implanted by ion implantation, etc., are vaporized in the post-oxidation step and expand in volume.

(Problems to be Solved by the Invention) As described above, conventionally, when metal silicide is used for the electrode wiring, there has been a problem that the silicide layer is peeled off due to blistering or explosion in the post-oxidation step. This significantly reduces the yield and reliability of the semiconductor device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing the peeling of an electrode wiring using a metal silicide layer and improving the yield and the reliability.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes the steps of: depositing a semiconductor layer including a metal silicide layer on a semiconductor substrate; A step of patterning the semiconductor layer to form an electrode wiring, and as a first heat treatment after the formation of the electrode wiring, an inert gas atmosphere containing substantially no nitrogen, or an inert gas containing substantially no nitrogen. And a step of performing at least one post-heat treatment after the first oxidation treatment.

(Operation) According to the results of detailed studies by the present inventors on the mechanism of peeling of the electrode wiring including the silicide layer described above,
It has been clarified that the major cause is that the gas is difficult to escape because the surface of the silicide layer is covered with the dense nitride film. That is, the silicide layer immediately after the film formation is usually an active amorphous material and contains a large amount of gas. This silicide layer is crystallized by a heat treatment in a nitrogen-containing atmosphere exceeding a crystallization temperature of 400 to 500 ° C., and at the same time, silicon on the surface is nitrided to form a stable nitride film. Therefore, as described in the above-described MOS transistor manufacturing process, if heat treatment is performed in an atmosphere containing nitrogen for the purpose of forming a thin oxide film before ion implantation of the source and drain, the surface of the gate electrode formed of the silicide layer is nitrided. Covered with membrane. This is because X-ray photoelectron spectroscopy (XP
S). When the surface of the silicide layer is covered with the nitride film as described above, the gas contained in the silicide layer becomes difficult to escape in the subsequent post-oxidation step, and the volume expands inside and bursts at a stretch.

Therefore, according to the first aspect, the first heat treatment after the formation of the silicide layer is performed in an atmosphere substantially free of nitrogen, so that a nitride film is not formed on the surface of the silicide layer. Gases such as argon and fluorine contained therein can be easily diffused outward, and the burst of the silicide layer can be prevented.

(Example) Hereinafter, an example of the present invention will be described.

1 (a) to 1 (e) show a manufacturing process of a MOS type semiconductor device according to one embodiment, focusing on a MOS transistor portion. As shown in FIG. 1A, a field oxide film 12 is formed by a LOCOS method using a p-type silicon substrate (for example, a specific resistance of 6 .OMEGA.cm) 11, and then a gate insulating film 13 having a thickness of 5 to 20 nm is formed. A silicon oxide film is formed by thermal oxidation. Next, as shown in FIG. 1 (b), the polysilicon layer 14, WS
i _{x (x} = 2.5~2.7) layer 15 are sequentially laminated form. The polycrystalline silicon layer 14 contains arsenic as an impurity in an amount of 1 to 5 × 10 ¹⁵ cm ⁻² and has a thickness of about 100 nm. The WSi _x layer 15 is formed by
It is a DC magnetron sputtering method in an Ar gas atmosphere using an alloy target of _2.7 , and has a thickness of about 300 nm. The Ar gas pressure during sputtering is 0.3 to 3 Pa, and the substrate is not actively heated. The target voltage (that is, the cathode voltage) is 400 to 600 V, and the distance between the substrate and the target is 60 to 100 nm. The substrate is usually floating and its potential is 0 to -20 V. In this embodiment, however, a positive bias is applied to the substrate so as to cancel the negative potential in the floating case.

The WSi _x layer 15 thus deposited was confirmed to be amorphous by X-ray diffraction. Further, according to Rutherford backscattering (RBS) method, when the distance between the substrate and the target is 70 mm, the inside WSi _x layer 15 obtained 0.5
It was confirmed that about 1.3 at% of Ar was contained. Ar
The content also depends on the Ar gas pressure in the atmosphere. Ie
It was found that the higher the Ar gas pressure, the lower the discharge voltage, the lower the energy of Ar ions reflected from the target, and the lower the amount of Ar contained in the silicide deposited on the substrate. However, it was difficult to reduce the amount of Ar contained in the silicide layer to 0.5 at% or less only by increasing the Ar pressure. In the case of this embodiment, by applying a positive bias to the substrate, it is difficult for Ar ions to be taken into the formed silicide layer, and the Ar content is actually reduced as compared to the case without such a bias. Has been confirmed. However, positively biasing the substrate means that negative ions such as O ⁻ , N ⁻ , and OH ⁻ are more likely to be taken into the substrate. Therefore, it is preferable that the total residual oxygen partial pressure, nitrogen partial pressure and water vapor partial pressure be less than 1 × 10 ⁻⁵ Pa.

Next, as shown in FIG. 1C, the electrode film thus formed is patterned by ordinary photolithography and reactive ion etching (RIE) to form a gate electrode 16. At this time, although not shown, a necessary first layer wiring is formed simultaneously with the gate electrode 16. After that, the first post-oxidation step, which is the first heat treatment step after the formation of the gate electrode, is performed in an oxidizing atmosphere (Ar-10% O ₂ ) diluted with argon at 1000 ° C. for 20 minutes. As shown in d), a thin oxide film 17 of about 10 nm is formed on the surface of the gate electrode 16. At this time, the oxidizing atmosphere does not substantially contain nitrogen, that is, the partial pressure of nitrogen is 1 ppm or less. Followed by conventional ion implantation step, arsenic acceleration voltage 50 keV, and implanted at a dose 5 × 10 ¹⁵ / cm ² to form source and drain diffusion layers 18 and 19.

After the first post-oxidation step described above, the Ar concentration in the WSi _x layer 15 was measured by Rutherford backscattering method and found to be below the detection limit, and at least 50% or more of the Ar during film formation was outside. It was confirmed that it was missing by diffusion.

After the source and drain diffusion layers are formed as described above, a second post-oxidation step is performed in a dry oxygen atmosphere at 950.
Oxidation is performed at 20 ° C. for 20 minutes. As shown in FIG.
To form Thereafter, although not shown, an interlayer insulating film is deposited according to a normal process, a contact hole is formed in the interlayer insulating film, and a metal wiring is formed to complete the process.

According to this example, even after the second post-oxidation step, the electrode wiring including the silicide layer was stable, did not cause swelling or peeling, and showed a higher yield as compared with the related art.

2 (a) to 2 (d) show a manufacturing process of another embodiment. Here, a wiring portion including silicide is shown instead of an active element portion. As shown in FIG. 2 (a), plasma CVD at 350 ° C. using a mixed gas of SiH ₄ and N ₂ O on a p-type (100) silicon substrate 21 having a specific resistance of 6Ω · cm.
A 0.8 μm silicon oxide film 22 is formed by the method.
Subsequently, at a substrate temperature of 620 ° C., a 50 nm
Is formed. Polycrystalline silicon layer 23
After film formation, arsenic is accelerated at a voltage of 40 keV and a dose of 5 × 10 ¹⁵ c
^Implant at m ^-2 . Next, as shown in FIG. 2B, a WSi _x (x = 2.5 to 2.7) layer 24 of about 300 nm is deposited by sputtering in an Ar atmosphere using a WSi alloy target. At the time of this sputtering, a positive bias is applied to the substrate as in the previous embodiment. As a result of X-ray diffraction, it was confirmed that the obtained WSi _x layer 24 was amorphous.

Thereafter, as shown in FIG. 2 (c), the polysilicon layer 23 by the ordinary photolithography and RIE and WSi _x layer 24
Is patterned to form a wiring. After the wiring pattern is formed, the first thermal process is performed in a pure Ar atmosphere.
The crystallization heat treatment is performed at 0 ° C. for 10 minutes, and then the oxidation treatment is performed continuously for 30 minutes by using the same furnace and changing the atmosphere gas to dry oxygen. Thus, an oxide film 25 of about 30 nm is formed on the surface of the WSi _x layer 24.

Then, the substrate temperature was set to 450 ° C., and a normal pressure CVD method using a mixed gas of monosilane (SiH ₄ ) and oxygen (O ₂ ) diluted with Ar gas was used, as shown in FIG. A silicon oxide film 26 of about 1 μm is formed.

Also according to this embodiment, the polysilicon layer 23 and the WSi _x layer
No wiring abnormality such as swelling or peeling was observed in the 24 laminated films, and it was confirmed that stable wiring was obtained.

The present invention is particularly applicable to an EPRO having a memory element having a floating gate structure.
This is effective when manufacturing memory devices such as M and EEPROM. In these devices, due to the reliability as a memory element, the charge accumulated in the floating gate must not leak through the surrounding insulating film, and it is necessary to form these insulating films at a high temperature for a long time. . Under these conditions,
The gasification of impurities in the silicide and the volume expansion of the gas are particularly likely to occur. According to the present invention, such a problem can be effectively solved.

In the above embodiment, by applying a positive bias to the substrate during the formation of the silicide layer, the incorporation of Ar is suppressed, and at the same time, the first heat treatment after the deposition is performed in an atmosphere containing no nitrogen to prevent the formation of the nitride film. Thus, outward diffusion of impurities such as Ar taken in silicide is facilitated. Therefore, a stable electrode wiring can be obtained due to a large synergistic effect.
That is, by performing either a positive bias on the substrate at the time of sputtering or the first heat treatment in an atmosphere containing no nitrogen, it is possible to form electrode wiring with sufficiently higher reliability than in the past.

In the embodiment, the silicide layer is formed by the sputtering method. However, the invention in which the first heat treatment is performed in an atmosphere containing no nitrogen is also effective when the silicide layer is formed by the CVD method. For example, when a silicide layer is formed by a CVD method using a WF ₆ gas and a SiH ₄ gas, F and the like incorporated in the layer are easily formed in a subsequent heat step according to the present invention in which a nitride film is not formed. It can be diffused, and is effective in preventing film rupture and the like.

In the embodiment, the case where WSi _x is used as the silicide layer has been described, but other metals such as Ti, Zr, Hf, V, Nb,
It has been confirmed that the present invention is also effective when silicides such as Ta, Cr, Mo, Ni, Rh, Pd, Ir, and Pt are used. A steam atmosphere can also be used as the oxidizing gas using an inert gas containing no nitrogen. Helium (He), neon (Ne), or the like may be used in addition to Ar as the inert gas containing no nitrogen.

Further, in the embodiment, the case of the laminated structure of the polycrystalline silicon layer and the silicide layer has been described. However, the same effect can be obtained by applying the present invention even when the electrode wiring is formed only by the silicide layer.

In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, in manufacturing a semiconductor device including an electrode wiring using a metal silicide layer, a gas taken into the silicide layer easily diffuses outward in a subsequent thermal process. By preventing unnecessary gas from being taken into the silicide layer, and by taking these into consideration at the same time, to prevent peeling of the electrode wiring, and to improve the yield and reliability of the semiconductor device. be able to.

[Brief description of the drawings]

1 (a) to 1 (e) are diagrams showing a manufacturing process of one embodiment of the present invention, FIGS. 2 (a) to 2 (d) are diagrams showing a manufacturing process of another embodiment, FIG. FIG. 2 is a diagram showing a MOS transistor structure using a silicide electrode according to a conventional method. 11 ... silicon substrate, 12 ... field oxide film, 13 ...
Gate electrode, 14 ... polycrystalline silicon layer, 15 ... WSi _x layer,
16 ... gate electrode, 17 ... thermal oxide film, 18 ... source layer,
19 ... Drain layer, 21 ... Silicon substrate, 22 ... CVD oxide film, 23 ... Polycrystalline silicon layer, 24 ... WSi _x layer, 25 ...
Thermal oxide film, 26 ... CVD oxide film.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/3205 -21/3213 H01L 21/768 H01L 29/78

Claims (10)

(57) [Claims] A step of depositing a semiconductor layer including a metal silicide layer on a semiconductor substrate; a step of patterning the semiconductor layer to form an electrode wiring; and a first heat treatment after the formation of the electrode wiring. A step of performing a first post-oxidation treatment in an oxidizing atmosphere diluted with an inert gas not containing nitrogen, and a step of performing a second post-oxidation treatment after the first heat treatment. Manufacturing method of a semiconductor device. 2. The temperature of said at least one post-heat treatment is:
2. The method according to claim 1, wherein the temperature is lower than the temperature of the first heat treatment. A step of depositing a semiconductor layer including a metal silicide layer on a semiconductor substrate; a step of patterning the semiconductor layer to form an electrode wiring; and a first heat treatment after the formation of the electrode wiring. A method of manufacturing a semiconductor device, comprising: a step of performing a crystallization heat treatment in an inert gas atmosphere that does not contain nitrogen; and a step of performing a post-oxidation treatment after the first heat treatment. 4. The method according to claim 2, wherein the semiconductor layer is deposited by a CVD method. 5. The method according to claim 2, wherein the semiconductor layer is deposited by a bias sputtering method. 6. The metal silicide layer is formed of WSi _x (x = 2.5 to 2.
7) The method for manufacturing a semiconductor device according to claim 1, wherein the method is a layer. 7. The method according to claim 1, wherein the nitrogen concentration in the oxidizing atmosphere is 1 ppm or less. 8. The method according to claim 1, wherein the electrode wiring is a floating gate electrode wiring of a memory having a floating gate structure. 9. A step of depositing a semiconductor layer including a WSi _x (x = 2.5 to 2.7) layer on a semiconductor substrate by a CVD method; a step of patterning the semiconductor layer to form a floating gate electrode wiring; Performing a first post-oxidation treatment in an oxidizing atmosphere diluted with an inert gas atmosphere having a nitrogen concentration of 1 ppm or less as a first heat treatment after the formation of the floating gate electrode wiring; Performing a second post-heat treatment with a low heat resistance. 10. A step of depositing a semiconductor layer including a WSi _x (x = 2.5 to 2.7) layer on a semiconductor substrate by a CVD method; a step of patterning the semiconductor layer to form a floating gate electrode wiring; The first heat treatment after the formation of the floating gate electrode wiring includes a step of performing a crystallization heat treatment in an inert gas atmosphere having a nitrogen concentration of 1 ppm or less, and a step of performing a post-oxidation treatment following the first heat treatment. A method for manufacturing a semiconductor device.