JP3438434B2 - Nonvolatile semiconductor device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, an EPROM.
(Electrically Programmable ROM), EEPROM
The present invention relates to a nonvolatile semiconductor device having a two-layer gate structure such as (Electrically Erasable ROM) and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device such as an EPROM or an EEPROM is, for example, as shown in FIG. 7, a first insulating layer 51 made of silicon oxide, a first gate electrode 52 made of polysilicon, and a first gate electrode made of silicon oxide on a substrate 50. 2 insulating layer 5
3 and a second gate electrode 54 made of polysilicon or a metal material are sequentially stacked to have a two-layer gate structure. Usually, the first gate electrode 52 is called a floating gate and the second gate electrode 54 is called a control gate. Conventionally, such a double gate structure is formed as follows, for example.

First, a silicon oxide film and a polysilicon layer are sequentially formed on a substrate 50. Then, they are patterned by lithography and etching to form a first insulating layer 51 and a first gate electrode 52. Then, reoxidation is performed to form a silicon oxide film on the surface of the first gate electrode 52, and a polysilicon layer is formed on the base body 50 in a state of covering the oxide film. Then, the second insulating layer 53 and the second gate electrode 54 are formed by patterning them by lithography and etching. In the semiconductor device having the two-layer gate structure, the storage operation is performed by accumulating charges in the first gate electrode 52.

[0004]

In the above-mentioned semiconductor device having the double gate structure, the second insulating layer is formed of a thin oxide film in order to increase the capacitance. However, since a high voltage of, for example, about 20 V is applied during the charge accumulation,
The withstand voltage of the insulating layer deteriorates, and a leak current is likely to occur.

Further, since the conventional manufacturing process is very complicated, the bit cost is high. Moreover, since a thin natural oxide film is formed on the second insulating layer, the reliability may be reduced unless the natural oxide film is removed before forming the second gate electrode. The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile semiconductor device having a high breakdown voltage double gate structure and capable of reducing the bit cost, and a manufacturing method thereof.

[0006]

A non-volatile semiconductor device of the present invention for solving the above-mentioned problems (hereinafter referred to as a device of the present invention) comprises a first insulating layer and polysilicon on a substrate.
The first gate electrode of the floating gate, the second insulating layer made of amorphous silicon, and the metallic material
It has a double gate structure in which the second gate electrode of the control gate is sequentially formed. The upper surface of the first gate electrode is preferably formed to be rough. For example, the first gate electrode formed of polysilicon having a hemispherical shape on at least the second insulating layer side is used.

[0007] manufacturing method (hereinafter, referred to as the present method) of the semiconductor device of the present invention in, first on a substrate, layer and the second insulating polysilicon to form the first insulating layer and the first gate electrode A layer of amorphous silicon for forming a layer and a layer of a metal-based material for forming the second gate electrode are sequentially stacked. The floating gate is then patterned by patterning those stacks.
Second gate electrode of the control gate and the first gate electrode of
Form a two-layer gate structure with poles . In the formation of the polysilicon layer, the upper surface of the polysilicon layer may be roughened. In this case, the roughening is performed by forming a layer of polysilicon from hemispherical polysilicon or by forming a layer of hemispherical polysilicon on the polysilicon layer.

Further, an insulating layer and a polysilicon layer are sequentially formed on the substrate and then patterned to form the insulating layer.
A first insulating layer made of a layer and a polysilicon layer made of polysilicon.
Forming a first gate electrode to be a loading gate ,
Then, after the amorphous silicon layer and the metal-based material layer was laminated in this order on the first insulating layer and on the substrate so as to cover the first gate electrode, said patterned amorpha
A second insulating layer composed of a silicon layer and the metal-based material layer
A two-layer gate structure may be formed by forming a second gate electrode which is to be a control gate .

According to the present invention, the following effects can be obtained. According to the device of the present invention, since the second insulating layer is made of amorphous silicon having a higher insulating property than the oxide film, it is possible to increase the capacitance of the second insulating layer without thinning the second insulating layer. Further, since the second gate electrode is made of a metal-based material, the reaction with the lower layer amorphous silicon at a low temperature can be suppressed as much as possible.

Further, since the upper surface of the first gate electrode is formed to be rough, the surface area of the first gate electrode is formed larger than in the conventional case. As a result, the contact area with the upper second insulating layer increases, and the capacitance of the second insulating layer increases. Further, since at least the second insulating layer side is made of hemispherical polysilicon, the upper surface of the first gate electrode is roughened.

According to the method of the present invention, an insulating layer is formed on the surface of the substrate,
Since the polysilicon layer, the amorphous silicon layer, and the metal-based material layer are continuously laminated, the metal-based material layer is formed without forming a natural oxide film on the surface of the amorphous silicon layer. Moreover, since the above layers are formed in a laminated manner and the laminated bodies are collectively patterned,
The manufacturing process is simplified and the number of steps is small.

By further roughening the upper surface of the polysilicon layer by forming the polysilicon layer, an amorphous silicon layer having a large contact area with the polysilicon layer is formed. Further, by using hemispherical polysilicon for forming the polysilicon layer, the upper surface of the polysilicon layer is roughened at the same time as the formation of the polysilicon layer, thus eliminating the need for a new roughening step. Become.

Even when the second insulating layer and the second gate electrode are formed on the first gate electrode after forming the first insulating layer and the first gate electrode, the amorphous silicon layer and the metal-based material are formed on the substrate. Since the material layer and the material layer are continuously laminated, formation of a natural oxide film on the surface of the amorphous silicon layer is prevented.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an apparatus and a method of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the device of the present invention. This semiconductor device 1 has a double gate structure, and for example, silicon oxide (SiO 2) is formed on a substrate 11 made of silicon (Si).
The first insulating layer 12 composed of ₂ ) is formed. A first gate electrode 13 made of polysilicon (Poly-Si) is formed on the first insulating layer 12, and a second insulating layer 1 made of amorphous silicon (a-Si) is formed on the first gate electrode 13.
4 and a second gate electrode 15 made of a metal material are sequentially formed.

At least the second insulating layer 14 side of the first gate electrode 13 is made of hemispherical grain Poly-Si (herein, simply referred to as hemispherical Poly-Si). In this embodiment, the entire first gate electrode 13 is formed of hemispherical Poly-Si. And hemispherical Po
The upper surface of the first gate electrode 13 is rough due to ly-Si.

Further, the second gate electrode 15 is formed of the lower layer a-S.
It is formed of a metal-based material such as an aluminum-copper (Al-Cu) alloy that can suppress reaction with i at a low temperature as much as possible.

In the above embodiment, the second insulating layer 14 is
Since it is made of a-Si, which has higher insulation than the oxide film, the capacity of the second insulating layer 14 can be increased without thinning the second insulating layer 14. That is, the amount of accumulated charge in the second insulating layer 14 when a voltage is applied can be increased. Therefore, since the second insulating layer 14 can be formed thicker than the oxide film, it is possible to suppress breakdown voltage deterioration of the second insulating layer 14 when a high voltage is applied.

Further, since the upper surface of the first gate electrode 13 is roughened by the hemispherical Poly-Si, the surface area of the first gate electrode 13 is larger than that of the conventional example. As a result, the contact area with the upper second insulating layer 14 increases, which also makes it possible to increase the amount of charges accumulated in the second insulating layer 14.

Therefore, it is possible to realize the semiconductor device 1 having a highly reliable double gate structure in which the withstand voltage deterioration of the second insulating layer 14 is small when a high voltage is applied. In addition, since a large amount of initial charge can be held by the second gate electrode 15 when charges are exchanged during writing and erasing, the hysteresis of the capacitance (C) -voltage (V) characteristics can be increased even at a lower voltage than before.

FIG. 2 shows C- of the semiconductor device 1 of the above embodiment.
It is a V characteristic figure, (a) has shown before writing, (b) has shown after writing. The substrate 11 has a surface concentration of 5.85.
An n-type Si substrate of × 10 ¹⁴ cm ^{-3 is used} , and the film thickness of the first insulating layer 12 is about 100 nm. The first gate electrode 13 is formed of hemispherical poly-Si doped with phosphorus (P), and the second gate electrode 15 is formed of an Al-Cu alloy with a thickness of 500 n.
It is formed to a film thickness of about m. In addition, a case where writing is performed by applying a low voltage of 10 V in a pulse shape is shown.

As is apparent from the figure, a normal CV characteristic can be obtained before writing, and a large hysteresis can be provided after writing. Therefore, in the semiconductor device 1 of the above-described embodiment, since writing and erasing can be performed even at a low voltage, it is possible to lower the voltage of the high breakdown voltage transistors in the periphery,
The reliability of the semiconductor device 1 can be improved.

In the above embodiment, the case where the first gate electrode 13 is formed of only hemispherical Poly-Si has been described. However, it suffices that at least the second insulating layer 14 side is formed of hemispherical Poly-Si, and the first gate electrode 13 is formed, for example, as shown in FIG.
It is also possible to have a structure in which a hemispherical Poly-Si layer 13b is laminated on top.

In this case as well, since the upper surface of the first gate electrode 13 is formed to be a rough surface, it is possible to obtain the same effect as in the above embodiment. In the above embodiment, the second insulating layer 1
4 has been described as being formed of a-Si, for example, oxygen-doped Poly-Si (SIPOS) or oxygen-rich Po.
Even if it is formed of ly-Si, it is possible to increase the amount of accumulated charge as in the case of a-Si.

In the above embodiment, the second gate electrode 15 is made of Al-Cu alloy.
The material is not limited to the above example as long as it is formed of a metal-based material that can suppress the reaction with i at a low temperature as much as possible.

Examples of such metallic materials include aluminum (Al), Al alloys such as Al-Cu, and general barrier metals. Common barrier metals are, for example, tungsten (W), titanium (T
i) and other refractory metals, their silicides, refractory metal nitrides such as titanium nitride (TiN), refractory metal oxynitrides such as titanium oxynitride (TiON), and titanium tungsten (TiW). . Second gate electrode 1
5 can be formed of one kind of these Al, Al alloy, or barrier metal, or can be formed by stacking Al alloys via the barrier metal. When the barrier metal is used, it is possible to use one kind of barrier metal or a combination of plural kinds of barrier metals.

The specific resistance of the Al-Cu alloy is 20 μΩ.
・ While about cm, barrier metal such as Ti
The specific resistance of N is four times that, about 80 μΩ · cm. However, the wiring resistance value of the second gate electrode 15 is
If the value is about the same as 800 μΩ · cm of Poly-Si, if the second gate electrode 15 is formed of only the barrier metal, the thickness can be reduced to 1/10. In other words, if the conventional film thickness of the second gate electrode is 10
Double resistance can be realized.

Next, one embodiment of the method of the present invention will be described with reference to the process chart shown in FIG. Here, a case of manufacturing the semiconductor device 1 shown in FIG. 3 will be described as an example. Figure 4
As shown in (a), the element isolation region 11b is formed in the substrate 11 so as to surround the element formation planned region 11a by, for example, the LOCOS method.

Next, as shown in FIG. 4B, thermal oxidation is performed at about 850 ° C. using hydrogen chloride (HCl) gas (2-4% with respect to O ₂ ) and oxygen (O ₂ ) gas. ,
An insulating layer 12a having a film thickness of about 10 nm is formed on the surface of the base 11. The flow rate ratio of HCl gas and O ₂ gas at this time is
Set to about 0.45: 15 SLM.

Subsequently, low pressure chemical vapor deposition (hereinafter referred to as LPCVD) is performed at about 550 ° C. to form the insulating layer 12a.
Poly-Si doped with P of about 200 nm on top
Form the layer 13a. The reactive species is silane (SiH ₄ )
Gas and phosphine (PH ₃ ) gas are used, and the flow ratio of SiH ₄ gas and PH ₃ gas is set to 500: 1 sccm.

Next, disilane (Si ₂ H ₆ ) gas or other polysilane gas is used to perform epitaxial growth at a temperature of about 650 ° C. for about 10 seconds. And Poly-
A hemispherical Poly-Si layer 13b having an average particle size of about 5 to 250 nm is formed on the Si layer 13a. At this time, Si ₂
The flow rate of H ₆ gas is set to about ₆ sccm, and the pressure in the growth chamber is set to about 1 mPa.

Subsequently, the formation temperature is set to about 575 ° C. or lower (40
Up to about 0 ° C.) and the pressure of the forming atmosphere is 13.3 to 1
33 Pa, with SiH ₄ gas and Si ₂ H _{6 as} reaction species
Gas or other polysilane gas for LPCV
Do D. In this embodiment, for example, the forming temperature is about 510.
LPCVD is performed under the conditions that the temperature of the Si ₂ H ₆ gas is about 500 sccm and the pressure of the forming atmosphere is 200 Pa. Then, 200n is formed on the hemispherical Poly-Si layer 13b.
The a-Si layer 14a having a thickness of about m is formed. And
Al is formed on the a-Si layer 14a by the sputtering method.
-The Cu layer 15a is formed to a thickness of about 500 nm.

Next, as shown in FIG. 4C, Al--C
After applying a resist on the u layer 15a, a resist pattern 16 is formed by lithography. After that, ECR plasma etching is performed using the resist pattern 16 as a mask, and the insulating layer 12a, the Poly-Si layer 13a, the hemispherical Poly-Si layer 13b, the a-Si layer 14a, and the Al are formed.
-Patterning the laminated body of the Cu layer 15a. ECR
The plasma etching is performed under the condition that the flow rate ratio of Cl ₂ gas and O ₂ gas is about 70:10 sccm and the microwave power is about 850 W, for example. Then, the resist pattern 16 is removed.

Through the above steps, as shown in FIG. 4D, a two-layer gate structure composed of the first insulating layer 12, the second gate electrode 13, the second insulating layer 14 and the second gate electrode 15 is formed. It

In the above embodiment, the hemispherical Poly-Si layer 13b is formed on the Poly-Si layer 13a.
In the step of laminating the Poly-Si layers 13a and 13b, the first gate electrode 13 is simultaneously roughened. Therefore,
A new roughening step is unnecessary.

Further, the insulating layer 12a, Poly
-Si layer 13a, hemispherical Poly-Si layer 13b, aS
Since the i layer 14a and the Al-Cu layer 15a are continuously formed in layers, the Al-Cu layer 15a can be formed without forming a natural oxide film on the surface of the a-Si layer 14a. Is not required.

Further, since the laminates are continuously formed and the laminates are collectively patterned, the manufacturing process can be simplified and the number of processes can be significantly reduced. Further, an a-Si layer 14a that forms the second insulating layer 14
Unlike the conventional oxide film, can be formed at a low temperature. Therefore, by using the embodiment described above, it is possible to manufacture the highly reliable semiconductor device 1 having the double gate structure having the second insulating layer 14 having a high breakdown voltage at a low bit cost and in a low temperature process.

Next, another embodiment of the method of the present invention will be described with reference to FIG.
It will be described with reference to FIGS. 5 and 6 based on the manufacture of the semiconductor device 1 shown in FIG. In addition, here, the base 11 of the semiconductor device 1 is used.
The case of forming a MOS transistor will also be described. This embodiment is different from the above embodiment in that the patterning using the resist pattern 16 is
This is a point that a double gate structure is formed by performing the process separately.

That is, first, as shown in FIGS. 5A and 5B, the same steps as those in the above-described embodiment are performed until the formation of the hemispherical Poly-Si layer 13b, and then, as shown in FIG. 5C. A resist is applied on the hemispherical Poly-Si layer 13b, and then a resist pattern 16 is formed by lithography.

After that, the insulating layer 12 is formed by ECR plasma etching using the resist pattern 16 as a mask.
The poly-Si layer 13a doped with a and P and the hemispherical poly-Si layer 13b are patterned to form a first insulating layer 12 and a first gate electrode 13 as shown in FIG. 5D. The ECR plasma etching is performed, for example, under the condition that the flow rate ratio between Cl ₂ gas and O ₂ gas is about 70:10 sccm and the microwave power is about 850 W. Then, the resist pattern 16 is removed.

Next, as shown in FIG. 6E, the substrate 11 is ion-implanted with boron difluoride (BF ₂ ).
The LDD region 17 is formed in the. Then, a SiO ₂ film is deposited on the entire surface of the base 11 by the CVD method, and then the SiO ₂ film is etched back by RIE to form LDD spacers 18 on the side walls of the first insulating layer 12 and the first gate electrode 13. Then, on the substrate 11, BF is formed to a depth of about 200 nm.
_{2 and the} like are ion-implanted to form a source / drain region 19, channel ion implantation and the like are further performed, and then activation annealing is performed at 850 ° C. for about 30 minutes in a nitrogen atmosphere to form a MOS transistor.

After the MOS transistor is formed in this way, as shown in FIG. 6F, the first insulating layer 12 and the first insulating layer 12 and the first insulating layer 12 are formed on the substrate 11 by the same method as that of the above-described embodiment.
An a-Si layer 14a is formed so as to cover the gate electrode 13, and subsequently, a TiON layer, an Au-Cu layer, and a TiON layer are laminated in this order by, for example, a sputtering method to form a metal multilayer film 15b. To do. Next, as shown in FIG. 6G, after applying a resist on the metal multilayer film 15b, this resist film is patterned into the same shape as the resist pattern 16 described above.

Then, by ECR plasma etching using the formed resist pattern 16 as a mask, a-
The Si layer 14a and the metal multilayer film 15b are patterned to form the second insulating layer 14 and the second gate electrode 15 as shown in FIG. 6 (h). The above etching is performed under the same conditions as the ECR plasma etching for forming the first insulating layer 12 and the first gate electrode 13 performed previously.
Through the above steps, a semiconductor device having a two-layer gate structure composed of the first insulating layer 12, the second gate electrode 13, the second insulating layer 14, and the second gate electrode 15 and having a MOS transistor formed on the base 11. 1 is obtained.

Also in the above embodiment, the Poly-Si layer 1
Since the first gate electrode 13 can be roughened at the same time in the laminating step of 3a and 13b, a new roughening step is not necessary and the a-Si layer 14a can be formed at a low temperature. Further, since the metal multilayer film 15b can be formed on the surface of the a-Si layer 14a without forming a natural oxide film, the step of removing the natural oxide film can be omitted. Furthermore, since the a-Si layer 14a and the metal multilayer film 15b are formed after performing the activation annealing which is a high temperature heat treatment, the a-Si layer 14a and the metal multilayer film 15b are not adversely affected by the high temperature heat treatment. Therefore, according to this embodiment,
It is possible to manufacture the highly reliable semiconductor device 1 having the double gate structure having the high breakdown voltage second insulating layer 14 by a low temperature process.

In the above embodiment, hemispherical Poly-
Although the patterning is performed after forming the Si layer 13b, the insulating layer 12a and the Poly-Si layer 13a may be patterned after forming the P-doped Poly-Si layer 13a. In this case, the insulating layer 12a and Poly
After patterning with the -Si layer 13a, MO is applied to the substrate 11.
An S transistor is formed, and subsequently, a hemispherical Poly-Si layer 13b, an a-Si layer 14a, and a metal multilayer film 15b are continuously laminated on the entire surface of the base 11. Then, these stacked bodies are patterned to form a double gate structure.
This method is also effective because the metal multilayer film 15b can be formed without forming a natural oxide film on the surface of the a-Si layer 14a.

In each of the embodiments of the method of the present invention described above, the case where the first gate electrode 13 is composed of the Poly-Si layer 13a and the hemispherical Poly-Si layer 13b has been described. When one gate electrode 13 is composed only of hemispherical Poly-Si 13b, the insulating layer 12
After forming a, hemispherical Poly-Si 13b may be formed.

Also, in an embodiment of the method of the present invention, LPCV
Although the a-Si layer 14a is formed by the D method, for example, plasma CVD method, ECR plasma CVD method, Poly-Si
Can be formed by a method such as ion implantation after the film formation and a sputtering method.

Further, although the upper surface of the first gate electrode 13 is roughened by forming the hemispherical Poly-Si layer 13b, it may be roughened by other methods. Hereinafter, an example of conditions for forming the a-Si layer 14a by another method and another method for roughening the upper surface of the first gate electrode 13 will be described.

First, an example of conditions for forming the a-Si layer 14a by another method will be described. Plasma CVD method, ECR
In the plasma CVD method, for example, the formation temperature is set to about 200 ° C. or lower, and SiH ₄ gas, Si ₂ H ₆ gas, or other polysilane gas is used as a reaction species. Then, under the condition that the pressure of the forming atmosphere is set to about 13.3 to 133 Pa, a
-Si layer 14a can be formed.

As a method of implanting ions after forming the Poly-Si film, there are a method of implanting Si ⁺ ions and a method of implanting other ion species. The method of implanting Si ⁺ ions is a method of destroying the Poly-Si crystal by Si ⁺ ion implantation to form a-Si. In this way, the original
The intermediate region between the Poly-Si and the amorphized layer is equivalent to the case where the surface is pseudo roughened. for that reason,
As described above, the hemispherical Poly-S is formed on the Poly-Si layer 13a.
Even if the i layer 13b is not formed, if the Poly-Si layer 13a is formed to a predetermined thickness and then ion implantation is performed, the upper surface of the first gate electrode 13 is roughened and the a-Si layer 14a is formed. Can be done at the same time.

The used film thickness of the a-Si layer 14a is 50 to 30.
The conditions for Si ⁺ ion implantation when the thickness is about 0 nm are as follows.
About 10 to 170 KeV, dose amount is 0.6 to 6 × 10
^The Rp is set to about ¹⁵ cm ⁻² and the Rp is set to about ¹⁵ to 250 nm. For example, the used film thickness of the a-Si layer 14a is 150 nm.
If it is about the same, the ion implantation of Si ⁺ is performed twice. The first time is about 75 KeV, the dose is about 3 × 10 ¹⁵ cm ^-2 , and the Rp is about 100 nm. The second time is about 30 KeV, the dose is about 1 × 10 ¹⁵ cm ^-2 , R
It is performed under the condition that p is about 50 nm.

Further, for example, the used film thickness of the a-Si layer 14a is
If it is about 50 nm, about 20 KeV, dose amount
1 x 10¹⁵cm^-2And Rp of about 28 nm
In Si⁺Ion implantation is performed. In addition, ion implantation
The Poly-Si layer is formed by LPCVD, for example. this
In this case, the forming temperature should be about 575 ° C or higher (up to about 650 ° C).
And the reaction species is SiH. _FourGas, Si₂H₆Gas
Or other polysilane gas is used, and the pressure of the forming atmosphere is
Can be carried out under the conditions of about 13.3 to 133 Pa.
Wear.

On the other hand, as ion species to be injected into Poly-Si other than Si ⁺ , for example, oxygen ion (O ⁺ ) or nitrogen ion (N ⁺ ) or argon ion (Ar ⁺ ) or neon ion (Ne ⁺ ) etc. There is noble gas. a-Si layer 1
O when the film thickness of 4a is about 50 to 300 nm
Conditions for ion implantation of ⁺ or N ⁺ are, for example, 5 to 110.
KeV is set, the dose is set to about 0.1 to 6 × 10 ¹⁵ cm ⁻² , and Rp is set to about ¹⁵ to 250 nm.

The film thickness of the a-Si layer 14a is set to 50 to
Ar in the case of about 300 nm⁺Ion implantation conditions
Is, for example, about 10 to 260 KeV and the dose amount is 0.1.
~ 6 × 10¹⁵cm^-2Degree, Rp is about 15 to 250 nm
Is set to. Further, the film thickness of the a-Si layer 14a is set to 5
Ne in the case of 0 to 300 nm ⁺Of ion implantation
The conditions are, for example, about 5 to 90 KeV and the dose amount is 0.1.
~ 6 × 10¹⁵cm^-2Degree, Rp is about 15 to 250 nm
Is set to.

The a-Si layer 14 is formed by the sputtering method.
The condition for forming a is that the substrate temperature is 25 to 200 ° C.
The sputtering target is Si, and the sputtering gas is Ar. And it can carry out on the conditions which set the sputtering pressure to about 13.3 to 133 Pa. In addition, poly-Si
And then poly-Si is hit by reverse sputtering using Ar as a sputtering gas.
i can be converted. At this time, the substrate temperature and the sputtering pressure can be the same as above.

Next, the roughening of the upper surface of the first gate electrode 13 by another method will be described. Examples of the roughening method include the following four methods. The first method is Po
After forming the ly-Si layer, the upper surface of the ly-Si layer is anodized in citric acid or phosphoric acid (porous oxidation), and is further etched off with hydrofluoric acid to roughen the surface.

The second method is to immerse the substrate in water or an oxidant after forming the Poly-Si layer, and apply high pressure (about 1 to 100 atm) and high temperature (about 25 ° C. to about 400 ° C. or less). so
The upper surface of the Poly-Si layer is porous-oxidized. Then, the surface is roughened by etching off with hydrofluoric acid. The third method is to perform poly-Si a-Si conversion by using the ion implantation method described in the method for forming the a-Si layer 14a, and then to roughen the surface by the first method or the second method. It is a method of converting.

The fourth method is similar to the third method in that Poly-
After converting Si into a-Si, it is processed at a temperature of about 575 ° C. or higher to form island-shaped Poly-Si. After that, etch off with potassium hydroxide (KOH) or hot phosphoric acid,
This is a roughening method.

[0058]

As described above, in the device of the present invention, since the second insulating layer is made of highly insulating a-Si, the amount of accumulated charge in the second insulating layer can be increased. Further, since the second insulating layer can be formed thicker than the oxide film, it is possible to suppress the breakdown voltage deterioration of the second insulating layer when a high voltage is applied. In addition, since the upper surface of the first gate electrode is formed to be a rough surface by, for example, hemispherical Poly-Si, the contact area with the upper second insulating layer increases, so that the amount of accumulated charge in the second insulating layer increases. It is possible to increase.

According to the method of the present invention, an insulating layer is formed on the surface of the substrate,
Since the Poly-Si layer, the a-Si layer and the metal-based material layer are continuously laminated, the step of removing the natural oxide film before forming the metal material layer becomes unnecessary. Moreover, since the above layers are continuously laminated and patterned, and the laminated bodies are collectively patterned, the manufacturing process can be simplified and the number of processes can be reduced. Hemispherical Po is used to form the Poly-Si layer.
By using ly-Si, the upper surface of the Poly-Si layer can be roughened simultaneously with the formation of the Poly-Si layer, so that the manufacturing process is not complicated. Further, even after patterning the first insulating layer and the first gate electrode and then patterning the second insulating layer and the second gate electrode on the first gate electrode, the amorphous silicon layer and the metal-based material are formed on the substrate. Since the layers and the layers are continuously formed, the step of removing the natural oxide film before forming the metal material layer can be omitted. Therefore, according to the present invention, it is possible to manufacture a highly reliable semiconductor device having a double gate structure having a second insulating layer having a high breakdown voltage at a low bit cost.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the device of the present invention.

FIG. 2 is a CV characteristic diagram of a semiconductor device.

FIG. 3 is a cross-sectional view showing a modified example of the embodiment.

FIG. 4 is a process drawing showing an embodiment of the method of the present invention.

FIG. 5 is a process drawing (No. 1) showing another embodiment of the method of the present invention.

FIG. 6 is a process diagram (2) showing another embodiment of the method of the present invention.

FIG. 7 is a cross-sectional view showing an example of a conventional semiconductor device.

[Explanation of symbols]

1 Semiconductor device 11 Base 12 First insulating layer 12a insulating layer 13 First gate electrode 13a Poly-Si layer 13b Hemispherical Poly-Si layer 14 Second gate electrode 14a a-Si layer 15 Second gate electrode 15a Al-Cu layer (metal-based material layer) 15b Metal multilayer film (metal material layer)

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-64-33973 (JP, A) JP-A-63-255972 (JP, A) JP-A-5-110107 (JP, A) JP-A-7- 38103 (JP, A) JP 7-45724 (JP, A) JP 64-11362 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27 / 115 H01L 29/788 H01L 29/792

Claims (5)

(57) [Claims] 1. A non-volatile semiconductor device having a two-layer gate structure
In this case, the first insulating layer formed on the substrate and the polysilicon layer formed on the first insulating layer are used.
Gate electrode of a gate and amorphous silicon formed on the first gate electrode
A second insulating layer formed of a metal-based material formed on the second insulating layer.
A non-volatile semiconductor device comprising: a second gate electrode of a roll gate, wherein an upper surface of the first gate electrode is formed as a rough surface. 2. A non-volatile semiconductor device according to claim 1, wherein the first gate electrode, a non-volatile semiconductor device, characterized in that at least the second insulating layer side is formed by the hemispherical polysilicon. 3. A first insulating layer and a first gate electrode on a substrate.
Forming a polysilicon layer and a second insulating layer for forming
Form the amorphous silicon layer and the second gate electrode for
The metal-based material layer for forming
By patterning these laminates,
First gate electrode of control gate and control gate
Forming a two-layer gate structure with a second gate electrode
That in the manufacturing method of the nonvolatile semiconductor device, wherein the formation of the polysilicon layer, a method of manufacturing a nonvolatile semiconductor device characterized by roughening the upper surface of the polysilicon layer. 4. The method for manufacturing a non-volatile semiconductor device according to claim 3 , wherein the roughening is performed by forming the polysilicon layer with hemispherical polysilicon, or on the polysilicon layer. A method for manufacturing a non-volatile semiconductor device, which is performed by forming a hemispherical polysilicon layer. 5. A method for manufacturing a non-volatile semiconductor device having a two-layer gate structure, comprising: forming an insulating layer and a polysilicon layer in this order on a substrate, and then forming the insulating layer and the polysilicon layer. Patterning to form a first insulating layer made of the insulating layer and a first gate electrode made of the polysilicon layer to be a floating gate; and a state of covering the first insulating layer and the first gate electrode. Then, an amorphous silicon layer and a metal-based material layer are sequentially formed on the substrate, and then the amorphous silicon layer and the metal-based material layer are patterned to form a second insulating layer composed of the amorphous silicon layer and the metal. From the system material layer
And a step of forming a second gate electrode to be a different control gate, the method for manufacturing a non-volatile semiconductor device.