JP3265384B2 - Logic simulation method and logic simulation device used therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method for logic verification for simulating the operation of a designed logic circuit by a computer and determining whether or not an expected operation is realized, and a logic simulation used for the same. About the device .

[0002]

2. Description of the Related Art In a conventional logic simulation apparatus , connection information between elements constituting a logic circuit to be verified, that is, a so-called netlist, and a test pattern input to the logic circuit are subjected to verification. Logic simulation is performed without change regardless of whether the area is wide or narrow.

FIG. 9 is a flowchart showing a procedure of a conventional logic simulation. First, a netlist of a logic circuit to be verified and a test pattern to be input to the logic circuit are set (step S20), and a logic simulation is started based on these. In the process of this logic simulation, the signal value changes on each signal line
It is determined whether or not there is an event (hereinafter referred to as an event) (step S21). If no event exists on any of the signal lines, the logic simulation ends.

If an event exists on any of the signal lines, an element connected to the signal line is specified (step S22), and an output value of the element is calculated (step S2).
3). It is determined whether or not the calculated output value changes (step S24), and if so, an event is generated in the output signal of the element (step S25). When it is determined that the event has disappeared, the logic simulation ends.

[0005]

In the conventional logic verification as described above, in the logic verification of a large-scale logic circuit, even when a test pattern that operates only a part of the logic circuit is input, the circuit to be verified is However, there is a problem that a long time is required for the logic simulation in order to perform the simulation using all the netlists related to.

An object of the present invention is to provide a method for simulating using a test pattern in which only a part of a large-scale circuit operates, or an unnecessary signal line even when using a test pattern in which all circuits operate. The present invention provides a logic simulation method and a logic simulation apparatus used for identifying a circuit portion and deleting the circuit portion from a netlist, thereby enabling a high-speed logic simulation.

[0007]

Logic simulation method of the invention according to claim 1 Means for Solving the Problems], the logic simulation in based on the net list and the test pattern of the verification target logic circuit sheet
A logic simulation method executed by the logic simulation device , wherein first extraction means in the logic simulation device extracts a signal whose logic value does not change over the entire simulation time from the test pattern ; The second extraction means does not affect all signal lines whose logic values are fixed over the entire simulation time based on the signal extracted by the first extraction means and the output level of the output terminal of the logic circuit to be verified. extracting the circuit portions from said net list, the logic simulation
Deleting means in the emission device, characterized by comprising a step of deleting data of the second extraction means extracts the signal line and the circuit portion from said net list. Logic simulation method according to the invention of claim 2 is based on the net list and the test pattern of the verification target logic circuit
In a logic simulation method executed by a logic simulation device, the logic simulation device
The first extraction means in location, from the test pattern, extracting a signal whose logic value does not change over a period of a predetermined percentage of the total simulation time, the mode determining means in said logic simulation apparatus, the second Determining as a single operation mode a period during which the value of the signal extracted by the first extraction unit is fixed; and wherein the second extraction unit in the logic simulation apparatus determines whether each of the operation modes is determined by the mode determination unit. wherein during operation mode, respectively, and the total signal lines whose logic value is fixed, and a circuit portion which does not affect the output value of the output terminal of the verification target logic circuit by the signal lines whose logic value is fixed to Extracting from netlist and before
Deleting means in serial logic simulation apparatus, characterized in that the data of said signal line and the circuit portion second extracting means has extracted and a step of deleting from said net list. Logic simulation apparatus of the invention according to claim 3, netlist verification object logic circuit and
Theory of performing logic simulation based on test patterns
In physical simulation device, from the test pattern, first extracting means for extracting and outputting signal not logical value is changed over the entire simulation time, all simulations based on the signal of the <br/> extracted Over time
And all the signal lines whose logic value is fixed I, the verification object logic
Circuit part that does not affect the output level of the output terminal of the circuit
Second extracting means for extracting the door from the net list,
The data of the extracted signal line and the circuit portion, characterized in that a means for deleting from said net list.

According to a fourth aspect of the present invention, there is provided a logic simulation apparatus comprising: a netlist and a test for a logic circuit to be verified;
Logic stain that performs logic simulation based on patterns
In the simulation device, from the test pattern ,
The time of the predetermined ratio is against the whole simulation time
First extracting and outputting a signal whose logic value does not change stand
Extraction means, means for determining that the value of the extracted signal is fixed as one operation mode, and wherein the logic value is fixed during each operation mode for each of the operation modes Is
And all the signal lines that, the front by a signal line whose logic value is fixed
Do not affect the output value of the output terminal of the logic circuit to be verified.
It is characterized and second extracting means for extracting have a circuit portion from said net list, that the data of the signal lines and the circuit section and means to remove from the network <br/> Trst
You .

[0009]

According to the first and third aspects of the present invention, a signal whose logical value does not change is extracted from the test pattern during the entire simulation time, and further based on the signal whose logical value does not change. of extraction circuit portion does not affect the signal line and the output terminal the logic value becomes fixed netlist
And these signal lines and circuit parts are deleted from the netlist.
Is done .

[0010] is extracted In the invention according to claim 2 and 4, the signal whose logic value does not change from test patterns for a time predetermined percentage of the total simulation time
Is further the unchanged value by the signal is identified as the operation mode is the one between the logical value is fixed for a predetermined time, by a signal whose logic value is fixed for each operating mode of the respective logic value is fixed that the signal line is determined, the signal line and a circuit portion does not affect the output by the logic value is extracted, removed it from the netlist
Is done.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. (Embodiment 1) FIG. 1 is a block diagram showing a logic simulation method according to the present invention and each unit constituting a logic simulation apparatus used therein, input and output data thereof, and a processing procedure. In the figure, 1 is a first extracting means, 2 is a second extracting means, 3 is a first deleting means, 4 is a second deleting means, 5
Indicates simulation means. Prior to execution of the logic simulation, the first extraction means 1 tests the test pattern D ₁ to be input to the logic circuit to be verified.
Logic value extracts a signal that does not vary over the entire simulation time on the basis of the outputs this as the signal data D ₂ whose logic value does not change.

[0012] The second extraction means 2 is a first extraction means 1
Based on the net list D ₃ is a connection information between logical functions and elements of the respective elements of the signal data D ₂ and the logic circuit unchanged extracted from the entire signal lines whose logic value is fixed over the entire simulation time, and extracting a circuit portion which does not affect the output value of the output terminal of the verification target logic circuit by the total signal line the logic value is fixed from the netlist D _3, and outputs it as data D _4.

The first deleting means 3 deletes the signal data D ₂ whose logical value extracted by the first extracting means 1 does not change from the first test pattern D _1, and simulates the test pattern D ₅ after the deletion. Give to means 5. The second deleting means 4 deletes from the netlist D ₃ the data D _{4 of the} circuit portion which does not affect the output values of all the signal lines and the output terminals to which the extracted logical values are fixed. to output a netlist D _6. 5 is a logic simulation means performs a logic simulation on the basis of the net list D ₆ of the test pattern D ₅ and after removing after the deletion.

Next, the operation of the first embodiment will be described with reference to the flowchart shown in FIG. First element of the verification object logic circuit and the netlist D ₃ is a wiring information between the elements,
Setting the test pattern D ₁ to provide the verification target logic circuit (step S1). Level of the signal over the entire simulation time on the basis of the test pattern D ₁ is seen in the logic value "0", search for "1" or "X (undefined)" signal that does not change in any of (input signal) (step S
2)

For example, a case where the logic verification is performed on the logic circuit shown in FIG. 3 by using a test pattern shown in FIG. 4 will be specifically described. In FIG. 3, 11 and 13 are AND gates, 12 and 16 are OR gates, 14 and 15 are inverting elements, and L _{1 to} L ₁₀
Indicate signal lines. In FIG. 4, A, B,
C and D are signal lines L ₁ , L ₂ , L ₃ ,
It is the input signal for the L _7. Since the input signal A shown in FIG. 4A remains unchanged at the "L" level, that is, the logical value "0" over the entire simulation time, the input signal A is determined to be a signal that does not change over the entire simulation time.

Next, due to the influence of the signal A determined in step S2, the signal level value becomes a logical value of "0", "1" or "X".
(Indefinite) "is determined (step S3). For example, in the logic circuit of FIG. 3, the signal lines L ₁ , L ₅ , and L ₆ are fixed at the logical value “0” due to the influence of the input signal A, and therefore the signal lines L ₁ , L ₅ , and L ₆ have the logical values It is determined as a fixed signal line.

All the elements (circuit portions) and signal lines that converge only on the determined signal lines and the elements gated by the logic values of these signal lines are deleted from the netlist, and the test pattern set in step S1 is deleted. From the input signal searched in step S2 (step S4)
. For example, in the case of the logic circuit shown in FIG. 3, although the signal lines L ₁ , L ₅ , and L ₆ have already been determined to be fixed to the logical value “0” in step S3, the AND gate 11 is fixed because the logical value is fixed to “0”. , 1
3 gates the values of the signal lines L ₄ and L ₈ respectively.

[0018] Therefore to remove from the signal line L ₄ from the OR gate 12 and the signal line L _2, L _3, L ₄ the netlist D ₃ converging only to the signal line L ₄ by going back a netlist.
Furthermore the AND gate 11 and the signal line L _4, which is gated to gating is also deleted from the netlist D _3. Elements and signal lines even netlist D converges only to the signal line L ₈ by going back a netlist D ₃ from Similarly the signal line L ₈
It will be removed from the _3, but the signal line L ₈ is inverting element 15
End up back in netlist D ₃ because it is also the input to, remove the AND gate 13 to gating netlist D _3, the logical value "0 over the entire simulation time to the output signal line L ₆ Are connected, and the process in step S4 is completed. When the process of step S4 is completed, the netlist D3 of the logic circuit shown in FIG. ₃ becomes equivalent to the netlist of the logic circuit shown in FIG.

[0019] To initiate a logic simulation on the basis of the net list D ₆ similarly and deleted deleted test pattern in step S4. In the course of this logic simulation, it is determined whether or not there is an event on each of the signal lines L ₆ , L ₇ , L ₈ , L ₉ and L ₁₀ (step S5). End the simulation. If there is an event, an element connected to the signal having the event is extracted as in the conventional case (step S6), and the output value of the element is calculated (step S7).
It is determined whether or not there is a change in the output value (step S8) .If there is no change, the process returns to step S5.If there is, an event is generated and information of the change is added to the signal line (step S8).
S9). In the first embodiment, a test pattern,
In particular the netlist D ₃ is greatly simplified, and thus is less time gas required for logic simulation.

(Embodiment 2) FIGS. 6A and 6B show various means constituting Embodiment 2 of the present invention, and the components thereof.
It is a block diagram showing output data and a processing procedure . During In the second embodiment from the test pattern D ₁ at the first extraction means 1 time a predetermined percentage of the total simulation time input, extracts the input signal data D ₂ in which the logic value does not change, that this extract The signal data D _{2 is given} to the operation mode determining means 6 and the first deleting means 3. The operation mode determining means 6 identifies a period during which the value of the input signal is fixed as one operation mode, for example, specifies the operation mode as “1”, and provides the operation mode data D ₇ to the second extraction means 2. .

The second extracting means 2 includes, for each operation mode based on the operation mode data D ₇ and the netlist D ₃ , all signal lines whose logic values are fixed over the entire time of each operation mode, by the signal lines to be fixed to extract a circuit portion which does not affect the output value of the output terminal of the verification target logic circuit, providing it as data D ₄ to the second deleting means 4. The first deleting means 3 deletes the signal data D ₂ whose value does not change, extracted by the first extracting means ₁ from the first test pattern D _1, and sends the deleted test pattern D ₅ to the simulation means 5. give. The second deletion means 4 extracts the data D of all the extracted signal lines and circuit portions.
₄ was removed from the netlist D _3, giving a net list D ₆ after deletion to the simulation means 5. Simulation means 5 performs logic verification based on the net list D ₆ and the test pattern D ₅ after the deletion.

Next, the operation of the second embodiment will be described with reference to the flowchart shown in FIG. In the first embodiment, a signal whose logic value is fixed to “0”, “1” or “X (undefined)”, that is, a signal that does not change, is extracted from the test pattern over the entire simulation time. When the logical value is fixed to "0", "1" or "X (indefinite)" for a predetermined ratio of time to, the period during which the value is fixed is specified as one operation mode (step S11). .

For example, in the case where the logic circuit shown in FIG. 3 is verified using the test pattern shown in FIG. 8, in the test pattern shown in FIG. 8, the signal value changes over, for example, 50% or more of the entire simulation time. Search for missing signals. Remove the retrieved signal from the test pattern D _1, giving it as a test pattern D ₅ after deletion to the simulation means 5. Since the value of the input signal A shown in FIG. 8A is fixed to the logical value "0" for at least 50% of the total simulation time, the period in which the input signal A is the logical value "0" is set in the operation mode. "1" is determined. The ratio to the total simulation time is not particularly limited to 50% or more, but may be less than 50%.

After the operation mode is determined in this way, the test mode is divided by time, in other words, the test mode is divided by time and the operation mode is set to "1" in the same manner as in the first embodiment. In step S12, an input signal whose logical value does not change is determined, and a signal line whose value is fixed to a logical value "0", "1" or "X (undefined)" is determined by the influence of the determined signal. (Step S13), all the elements converging only to the element gated by the logical value of the signal line, that is, the circuit portion and the signal line are deleted from the netlist (Step S14), and the The netlist D _{6 is provided} to the simulation means 5. After that, logic verification is performed by the logic simulation means 5 as in the first embodiment.

[0025]

As described above, according to the first and third aspects of the present invention, a signal whose logical value does not change over the entire simulation time is extracted from the test pattern and extracted.
Signal lines whose logic value is fixed determined by the influence of the signal
Is constant, the signal lines are removed from the netlist and the circuit portion which is gated by the logic value of the signal line
Therefore, the size of the logic circuit to be
Reduced size enables high-speed logic simulation.
Accordingly, stain while substantially reduction large logic circuit
Simulation can be performed at a high speed.

According to the second and fourth aspects of the present invention, a signal whose logic value does not change for a predetermined ratio of time to the entire simulation time is extracted from the test pattern and extracted.
The period during which the logical value of this signal is fixed is determined as one operation mode, and the signal line whose logical value is fixed is determined by the effect of the signal whose logical value is fixed for each operation mode. Since the circuit portion gated by the logical value of the signal line and the signal line are deleted from the netlist, the netlist is reduced and the high-speed logical system is reduced.
Simulation becomes possible. Therefore, it is possible to simulate a large-scale logic circuit in a substantially reduced state.
It is possible to perform simulation at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a logic circuit to be subjected to logic verification;

FIG. 4 is a timing chart showing a test pattern input to a logic circuit to be subjected to logic verification;

FIG. 5 is a circuit diagram of an equivalent circuit after the processing according to the first embodiment is performed on the verification target logic circuit illustrated in FIG. 3;

FIG. 6 is a block diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a flowchart illustrating a processing procedure according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing another test pattern input to the verification target logic circuit shown in FIG. 3;

FIG. 9 is a flowchart showing a processing procedure of logic verification by a conventional logic simulation apparatus .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st extraction means 2 2nd extraction means 3 1st deletion means 4 2nd deletion means 5 Simulation means 6 Operation mode determination means

Continuation of the front page (56) References JP-A-5-6407 (JP, A) JP-A-4-260974 (JP, A) JP-A-4-115365 (JP, A) JP-A-4-111071 (JP) JP-A-3-250262 (JP, A) JP-A-1-197868 (JP, A) JP-A-63-223926 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) G06F 17/50 664 JICST file (JOIS)

Claims (4)

(57) [Claims] We claim: 1. based on the net list and test pattern of the verification target logic circuit to logic simulation apparatus
In the logic simulation method performed Ri, first extraction means in the logic simulation apparatus, from said test pattern, extracting a signal whose logic value does not change over the entire simulation time, the second in the logic simulation apparatus Extracting means for all signal lines whose logic values are fixed over the entire simulation time based on the signal extracted by the first extracting means, and a circuit portion which does not affect the output level of the output terminal of the logic circuit to be verified. Extracting from the netlist, and the deleting means in the logic simulation apparatus deleting the data of the signal line and the circuit portion extracted by the second extracting means from the netlist. Logic simulation method. 2. A based on the net list and test pattern of the verification target logic circuit to logic simulation apparatus
A logic simulation method to be executed , wherein the first extraction means in the logic simulation apparatus extracts, from the test pattern, a signal whose logic value does not change for a predetermined ratio of time to the total simulation time; The mode determining means in the logic simulation device determines, as one operation mode, a period during which the value of the signal extracted by the first extracting means is fixed, and the second extracting means in the logic simulation device All signal lines whose logical values are fixed during each operation mode for each of the operation modes determined by the mode determination means.
And a circuit portion that does not affect the output value of the output terminal of the logic circuit to be verified by the signal line to which the logic value is fixed.
Extracting retrieved from said net list, delete means in the logic simulation apparatus, that the data of said signal line and the circuit portion second extracting means has extracted and a step of deleting from said netlist A featured logic simulation method. 3. A logic simulation apparatus for performing a logic simulation based on a netlist of a logic circuit to be verified and a test pattern, wherein a signal whose logic value does not change over the entire simulation time is extracted and output from the test pattern. Extraction means, all signal lines whose logic values are fixed over the entire simulation time based on the extracted signals, and a circuit part that does not affect the output level of the output terminal of the logic circuit to be verified are extracted from the netlist. A logic simulation apparatus comprising: a second extracting unit for extracting; and a unit for deleting data of the extracted signal line and circuit portion from the netlist. 4. A logic simulation apparatus for performing a logic simulation based on a netlist and a test pattern of a logic circuit to be verified, wherein a signal whose logic value does not change for a predetermined ratio of the total simulation time is output from the test pattern. First extracting means for extracting and outputting, a means for determining while the value of the extracted signal is fixed as one operation mode, and a logical value for each operation mode for each operation mode Extracting from the netlist all signal lines for which the logic value is fixed and circuit portions that do not affect the output value of the output terminal of the logic circuit to be verified by the signal line for which the logic value is fixed.
And a means for deleting the data of the signal line and the circuit portion from the netlist.