JP3269643B2 - Delay detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential detection circuit for a quaternary phase modulated signal.

[0002]

2. Description of the Related Art FIG. 7 is a schematic block diagram of a conventional delay detection circuit.

[0003] Delay detection of a phase modulated signal is a detection method for detecting a relative phase difference from a preceding symbol, and is differentially coded during modulation. Differential coding is a method of making information to be sent not correspond to an absolute phase but to a phase difference.

In FIG. 7, a modulated wave of an intermediate frequency differentially encoded is input from an input terminal 700. Unnecessary frequency components are cut from the input modulated wave by the IF filter 701. After that, the signal that has passed through the IF filter is phase-detected by a mixer 703 with a signal that is delayed by one symbol that passes through a delay circuit 702, is passed through a low-pass filter 704, and is output as a detection output.

As described above, conventionally, the delay and the
Signal processing such as detection was performed.

[0006] Therefore, the conventional differential detection circuit has a problem that it is difficult to form an integrated circuit because the signal processing is performed in a relatively high frequency band of an intermediate frequency.

[0007]

As described above, since the conventional differential detection circuit for detecting a differentially encoded signal is performed in the intermediate frequency band, it is difficult to integrate the differential detection circuit into an integrated circuit. I was

Accordingly, an object of the present invention is to provide a differential detection circuit which eliminates such a problem and facilitates integration into an integrated circuit.

[0009]

SUMMARY OF THE INVENTION A differential detection circuit according to the present invention has an input phase-modulated with a quaternary transmission signal having a relative phase difference of ± (π / 4) or ± (3π / 4) with respect to a preceding phase. In a delay detection circuit for demodulating a digital phase modulation wave, the phase-modulated input digital phase modulation wave is subjected to quadrature demodulation with a local oscillation frequency substantially equal to the center frequency of the input modulation wave, and the input modulation signal is subjected to in-phase and quadrature components. Frequency conversion means for converting into two baseband signals, and in-phase and quadrature components of a signal obtained by rotating the baseband signal by + (π / 4) and + (3π / 4) from the two baseband signals, respectively. Signal processing means for respectively generating a signal, an in-phase and quadrature component signal of a signal obtained by delaying the baseband signal by one symbol, and a signal generated by the signal processing means. And from a quadrature component signal, the baseband signal and the baseband signal + ([pi /
And 4) and + (3π / 4) phase-rotated signals.

[0010]

In the delay detection circuit according to the present invention, the input digital phase-modulated wave subjected to phase modulation is quadrature-demodulated by the frequency conversion means with a local oscillation frequency substantially equal to the center frequency of the input modulated wave to convert the input modulated signal. A signal obtained by converting the two baseband signals into two baseband signals of in-phase and quadrature components and performing phase rotation of the baseband signals from the two baseband signals by + (π / 4) and + (3π / 4), respectively. Respectively, and generates the in-phase and quadrature component signals of
From the in-phase and quadrature component signals of the symbol-delayed signal and the in-phase and quadrature component signals generated by the signal processing means, the baseband signal and the baseband signal are added by +
The inner product of the signal rotated by (π / 4) and + (3π / 4) is used as a detection output. According to such a configuration,
The signal processing related to the detection processing can be performed in the baseband, thereby easily realizing integration.

[0011]

FIG. 1 is a block diagram showing an embodiment of a delay detection circuit according to the present invention. FIG. 1 shows a delay detection circuit for a (π / 4) shifted QPSK signal. A phase modulation wave is input from a signal input terminal 100.

Here, the differential encoding of (π / 4) shift QPSK will be described with reference to FIG. FIG. 2 is a constellation diagram of a (π / 4) shifted QPSK modulated wave shown on a complex amplitude plane. In FIG. 2, a square (200) including a circle and a square (210) including a cross have an arrangement rotated by π / 4, and the phase of the carrier is any of the points indicated by the circles (201 to 204). And x mark (21
It is assumed that any one of the points indicated by 1 to 214) is alternately taken. Which of the phases of the circles and the crosses is selected depends on the quaternary signal transmitted. At this time, the phase change at successive symbol times is ± (π /
4) or ± (3π / 4),
Delay detection on the receiving side means detecting the relative phase change.

Now, returning to FIG. 1, the operation of the differential detection circuit will be continued. The output of the local oscillator 120 is given a phase difference of π / 2 by the phase circuit 130,
Divided into two. The bisected local oscillation signal and the input phase modulated wave are mixed by mixers 141 and 142, respectively, and frequency-converted into baseband signals. Further, each baseband signal is a low-pass filter 1
51 and 152 perform band limiting of input noise and shaping of a received waveform. That is, the input phase modulated wave is divided into two by the orthogonal vector by the orthogonal demodulation method. The bisected signal after passing through the low-pass filter can be expressed as a vector A (t) on a complex amplitude plane based on the I-axis and the Q-axis as shown in Expression (1).

A (t) = Io (t) + j (Qo (t)) (1) Here, consider a vector A1 (t) obtained by advancing the phase of the vector A (t) by π / 4. On the complex amplitude plane, advancing the phase of the vector by π / 4 is nothing but rotating the vector by π / 4. Therefore, the rotation of A (t) by π / 4 can be expressed as Expression (4) by Expressions (2) and (3).

_{J (π / 4)} e = cos (π / 4) + jsin (π / 4) (2) _(1/2) = (1/2) · (1 + j) (3) _{j (π / 4)} A1 (t) = A (t) · e _(1/2) = (Io + j (Qo)) · (1/2) · (1 + j) _(1/2) = (1/2) · ((Io− Qo) + j (Io + Qo)) (4) Vector A3 obtained by advancing the phase of vector A (t) by 3π / 4.
Similarly, (t) is obtained by multiplying equation (5) by vector A (t), as shown in equation (6).

_{J (3π / 4)} e = cos (3π / 4) + jsin (3π / 4) _(1/2) = (1/2) · (−1 + j) (5) _{j (3π / 4)} A3 ( t) = A (t) · e _(1/2) = (Io + j (Qo)) · (1/2) · (−1 + j) _(1/2) = (1/2) · (− (Io + Qo) ) + J (Io-Qo)) (6) Thus, the vector A1 (t) obtained by rotating the vector A (t) by π / 4 and the vector A3 obtained by rotating the vector A (t) by 3π / 4
(T) is the components of the vector A (t), Io and Qo
And Io + Qo,-(Io + Qo), and Io-Qo.

Now, referring to FIG.
The I-axis component subjected to quadrature demodulation through the mixer 141 and the low-pass filter 151 is defined as Io (S1).
2. Q that is quadrature demodulated through the low-pass filter 152
Assuming that the axis component is Qo (S2), Io + Qo (S5) is obtained by the adding circuit 161 and Io−Qo (S5) is obtained by the subtracting circuit 164 including the sign inverting circuit 163 and the adding circuit 162.
6), by the addition circuit 161 and the sign inversion circuit 165;
(Io + Qo) (S7) is obtained. Further, in order to perform the delay detection, if the delay time τ is selected as the symbol period T of the transmission signal in the delay circuits 171 and 172, the delay circuit 17
1, 172, respectively, the vector A1 (t−T)
(S3) and the vector A3 (t−T) (S4) are output. This vector A1 (t−T) and vector A3
(T−T) has a phase difference of ± π / 4 or ± 3π / 4 with respect to the vector A (t) due to the differential encoding. Therefore, the inner product of the vector A1 (t) and the vector A (t-T) is obtained. That is, the vector A1
The real part (Io-Qo) of (t) (S6) and the vector A1
(T−T) (S3) multiplied by the multiplication circuit 184 (S9) and the imaginary part (Io + Qo) of the vector A1 (t)
(S5) and the vector A3 (t−T) (S4) multiplied by the multiplication circuit 181 (S8) are added by the addition circuit 191 to obtain the vector A1 (t) and the vector A1 (t−T).
T) are 0 °, ± 90 °, ± 180 °, and the result obtained as the sum of the inner products of the respective orthogonal components is 1, 0, −1, which is output from the detection output signal terminal 193. You. However, the amplitude component is ignored.

The vector A3 (t) and the vector A
When the inner product with (t−T) is taken, that is, the vector A3
The multiplication circuit 182 multiplies the real part (− (Io + Qo)) (S7) of (t) by the vector A1 (t−T) (S3) (S10), and the imaginary part (Io) of the vector A3 (t) −Q
o) The multiplication circuit 183 multiplies (S6) and the vector A3 (tT) (S4) (S11) by the addition circuit 19
2, the vector A1 (t) and the vector A (t
The result obtained in the same manner as the inner product of −T) is 1, 0, −1, and is output from the detection output signal terminal 194.

FIG. 3 shows the above-described phase relationship. FIG. 3 shows the input signal and 1 in FIG.
FIG. 3 is a diagram illustrating a phase relationship of a symbol delay signal. (A) and (c) of FIG. 3 will be described. The vector A (t) in (a) is a modulation signal input from the input signal terminal, and the component is (Io, Qo). Where the vector A
(T) does not coincide with the I axis because the local oscillator is used as the reference for the I axis. The vector A1 (t) is obtained by rotating the vector A (t) by π / 4, and its component is a scalar multiple in units of (Io-Qo, Io + Qo). The vector A (t−T) delayed by one symbol shown in (c) is differentially coded, so that any one of ± π / 4 or ± 3π / 4 with respect to the vector A (t). One. Therefore, the vector A1 rotated by + π / 4
(T) and a vector A (t−) having a phase difference of + π / 4
In the case of T), the phases match, and when the inner product is taken, it becomes 1. Similarly, when the vector A (t−T) has a phase difference of + 3π / 4 and −π / 4, the vector A (t−T) becomes 0, and when the vector A (t−T) has a phase difference of −3π / 4, the vector A (t−T) becomes −1. Due to the difference,
One of 1, 0, and -1 is output.

Further, the vector A3 (t) in (b) is
The vector A (t) is obtained by rotating the vector A (t) by 3π / 4, and its component is (− (Io + Qo), Io−Qo).
The vector A (t−t) delayed by one symbol shown in FIG.
T) is a vector A (t) because it is differentially encoded.
Is ± π / 4 or ± 3π / 4. Therefore, when the vector A3 (t) rotated by + 3π / 4 and A (t−T) have a phase difference of + 3π / 4, the phases match, and when the inner product is obtained, it becomes 1. Similarly, the vector A
When (t−T) has a phase difference of + π / 4 and −3π / 4, it becomes 0, and when it has a phase difference of −π / 4, it becomes −1. Either 0 or -1 will be output.

FIG. 4 is a diagram showing the relationship between the phase difference in differential encoding and the value of the detection output signal terminal. As a result, the ternary judgment output from the detection output signal terminal 193, which is the inner product of the vector A1 (t) and the vector A (t−T), and the vector A
By the ternary determination output from the detection output signal terminal 194 which is the inner product of 3 (t) and the vector A (t-T), the phase difference between successive symbol values can be detected. For example, the value of the detection output signal terminal 193 is 1 and the detection output signal terminal 194 is
Is 0, the relative phase difference between successive symbol values is + π /
It becomes 4.

FIG. 5 is a block diagram showing a configuration of an optimum adjustment circuit of the detection timing of the detection output signal. The detection signals output from the detection output signal terminals 193 and 194 in FIG. 1 are input to the input terminals 593 and 594 in FIG. 5, respectively. The input detection output signals are compared with comparison circuits 511 and 512.
, And each signal is input to a full-wave rectifier circuit 521, 52
2 and are added by an adding circuit 550.

FIG. 6 shows an example of a detection waveform in the circuit of FIG. With respect to the input detection output signals at the points B and C in FIG. 5, the point A in FIG. 5 after passing through the addition circuit 550 is as shown in the lowermost part of FIG. 6. Further, the comparison circuits 511 and 51 have a function of holding the comparison result at the moment when the trigger is input until the next trigger input, by making a rectangular wave by the limiting amplifier 540 and appropriately delaying the signal by the timing adjustment circuit 530.
By inputting to the second trigger input, it is possible to optimize the timing for comparing the detected signals. In this way, an output signal by delay detection is obtained from the output terminals 561 and 562.

[0024]

As described above, according to the present invention, a signal which has been subjected to quadrature demodulation and converted to baseband is subjected to signal processing to obtain a delayed detection output. Therefore, there is an advantage that the delay detection circuit can be easily used, the size and weight of the mounted device can be reduced, and the circuit operation can be stabilized.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a differential detection circuit according to the present invention.

FIG. 2 is a constellation diagram of a (π / 4) shifted QPSK modulated wave.

FIG. 3 is a diagram showing a phase relationship between an input signal and a one-symbol delayed signal with reference to a local oscillator in FIG. 1;

FIG. 4 is a diagram illustrating a relationship between a phase difference in differential encoding and a value of a detection output signal terminal.

FIG. 5 is a block diagram showing a configuration of an optimum adjustment circuit of a detection timing of a detection output signal in the embodiment.

FIG. 6 is a diagram showing an example of a detection waveform in the circuit of FIG. 5;

FIG. 7 is a schematic block diagram of a configuration of a conventional delay detection circuit.

[Explanation of symbols]

 Reference Signs List 100 signal input terminal 120 local oscillator 130 phase circuit 141, 142 mixer 151, 152 low-pass filter 161, 162, 191, 192 addition circuit 163, 165 sign inversion circuit 164 subtraction circuit 171, 172 delay circuit 181, 182, 183 184 Multiplication circuit 193, 194 Detection output terminal S1 to S11 Separated or synthesized signal 511, 512 Comparison circuit 521, 522 Full-wave rectification circuit 530 Timing adjustment circuit 540 Limiting amplifier 550 Addition circuit 561, 562 Output terminal 593, 594 Input terminal 700 Input terminal 701 IF filter 702 Delay circuit 703 Mixer 704 Low-pass filter 705 Output terminal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-82349 (JP, A) JP-A-3-278648 (JP, A) JP-A-2-214245 (JP, A) JP-A 64-64 12646 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] A relative phase difference with respect to a preceding phase is ± (π /
4) A delay detection circuit for demodulating an input digital phase modulation wave phase-modulated with a quaternary transmission signal of ± (3π / 4), wherein the phase-modulated input digital phase modulation wave is Frequency conversion means for performing quadrature demodulation with a local oscillation frequency substantially equal to the center frequency to convert the input modulation signal into two baseband signals having an in-phase and a quadrature component; and converting the baseband signal from the two baseband signals into + (Π / 4) and + (3π / 4) signal processing means for respectively generating in-phase and quadrature component signals of a signal rotated in phase, and in-phase and quadrature component signals of a signal obtained by delaying the baseband signal by one symbol; From the in-phase and quadrature component signals generated by the signal processing means, the baseband signal and the baseband signal are converted into + (π / 4) and + (3π /
4) A delay detection circuit comprising detection processing means for obtaining an inner product with a signal whose phase has been rotated.