JP3276908B2 - Semiconductor device and processing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of processing the same, and more particularly, to the workability of a semiconductor device in performing FIB (focused ion beam) processing for, for example, delay adjustment. The technology relates to the improvement of

[0002]

2. Description of the Related Art A conventional semiconductor device and its processing method will be described below with reference to the drawings. FIG. 3 is a diagram illustrating a pattern configuration of a conventional multilayer wiring (for example, two-layer wiring). As shown in FIG. 3, the lower first layer wiring 10
The second layer wiring 11 is configured to intersect via an interlayer insulating film (not shown).

In a semiconductor device having such a multilayer wiring structure, FIB processing is performed for delay adjustment and the like. Here, the FIB is used, for example, when an insulating film on a semiconductor substrate is opened to form a connection hole reaching a wiring, or when the wiring is cut. The FIB is characterized in that the spot size of the ion beam can be reduced to about 0.1 μm, so that the insulating film and fine wiring of Al or the like can be cut with high accuracy.

FIGS. 4A and 4B are circuit diagrams as an example for explaining the delay adjustment. FIG. 4A shows a state in which a plurality of inverters 12, 13, 14, and 15 are connected in series. Direct inverter 15
In the case where the inverter 12 and the inverter 13 are FIB-processed and cut (see the cross mark in FIG. 4A) to connect
FIG. 4B shows a case where the inverter 16 and the inverter 17 are FIB-processed and cut (see the mark “x” in FIG. 4B), and the inverters 18, 19, 20, 21, 22 and 23 are passed between the inverters 23 and 17. Shows a case where the dotted line portions are connected by FIB.

[0005]

At this time, the FIB S
In an EM (scanning electron microscope) image, it is difficult to see the pattern shape of the first layer wiring 10 via the interlayer insulating film, and F
A problem such as cutting off a position deviated from the IB work location (see C in FIG. 3), for example, if the first layer wiring 10 is cut down, a short circuit occurs between the first layer wiring 10 and the second layer wiring 11, etc. There is a risk of occurrence of the problem, and there is a problem in workability when performing FIB processing.

In addition to the above-mentioned pattern in which the first layer wiring 10 and the second layer wiring 11 intersect, for example, each wiring in a single layer wiring structure is arranged in a number of rows. In a pattern, when a desired wiring is cut by FIB processing for delay adjustment or the like, there is a problem that it is confusing which wiring should be cut. Accordingly, it is an object of the present invention to provide a semiconductor device and a method for processing the same which improve workability during FIB processing.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and has been described in connection with an FIB for delay adjustment and the like.
In a semiconductor device having a wiring pattern to be processed,
This is a mark by making the line width of the working portion in the wiring narrower than the other line widths. And the processing method is
An operator performs the FIB processing on the work location on the basis of the mark formed so that the line width of the work area where the FIB processing is performed in the wiring is smaller than other line widths.

Further, in a semiconductor device having a multilayer wiring structure, the line width of a work portion in the uppermost layer wiring where FIB processing is performed is made narrower than other line widths, thereby being used as a mark. In the processing method, the worker performs the FIB processing on the work location using the mark formed so that the line width of the uppermost layer wiring of the work location on which the FIB processing is performed is smaller than the other line widths. .

Further, in a semiconductor device having a multilayer wiring structure of two or more wiring layers and having a work place for performing FIB processing for delay adjustment or the like on a wiring pattern where a lower wiring and an upper wiring intersect, And a notch provided on the side surrounding the mark of the lower wiring located in the vicinity of the work point, the mark being formed so that the line width of the work point where the FIB processing is performed is narrower than the other line widths.

[0010] The processing method is based on the F
A mark formed by forming the line width of the work portion to be subjected to the IB processing narrower than the other line width, and a notch provided on a side surrounding the mark of the lower layer wiring located near the work portion, and the notch and the mark are provided. The operator performs FIB processing on the work location with reference to (1).

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention and a processing method thereof will be described below with reference to the drawings. FIG. 1 is a plan view for explaining a pattern configuration of a semiconductor device according to one embodiment. As shown in FIG. 1, a second layer wiring 2 intersects a first layer wiring 1 via an interlayer insulating film (not shown). Is configured.

The line width of a working portion where the second layer wiring 2 is subjected to FIB (focused ion beam) processing is
It is formed thinner than the other line widths (see mark A in FIG. 1). In the present embodiment, for example, the line width of the second-layer wiring 2 is about 2.8 μm, and the line width of the work part serving as the mark A is about 1.2 μm (minimum design rule of this semiconductor device).

As described above, for example, by forming the line width of the work portion where the FIB processing is performed to be thinner than other line widths as a mark at the work position where the FIB processing of the uppermost wiring is performed, FIB processing such as delay adjustment may be performed using the mark as a guide, and the FIB processing error as in the conventional case, for example, the first layer wiring is cut down, and the possibility that the first layer wiring and the second layer wiring are short-circuited is eliminated. can do.

Further, even in a pattern in which the wirings in the single-layer wiring structure are arranged in rows, the line width of the working portion of the wiring to be subjected to delay adjustment or the like is formed narrower than the other line widths. Thus, the worker can perform the FIB processing using the mark as a mark, and the workability is improved. Next, another embodiment of the present invention will be described.

FIG. 2 is a plan view showing a pattern configuration of a semiconductor device according to another embodiment of the present invention. The difference from the pattern configuration of the semiconductor device according to one embodiment is that
The line width of the work place where the FIB processing of the layer wiring 2 is performed is made narrower than the other line widths, a mark A is attached, and the first layer wiring 3 on the side surrounding the work place where the FIB processing of the second layer wiring 2 is processed is applied.
The notch (see notch B in FIG. 2) makes it easier to recognize the work location.

In the processing method, the line width of the work portion where the second layer wiring 2 is subjected to the FIB processing is formed narrower than the other line widths, a mark A is attached, and the FI line processing of the second layer wiring 2 is performed.
By forming the notches B in the first layer wiring 3 on the side surrounding the work location where the B processing is to be performed, the worker can easily recognize the work location by using them as a guide.
FIB processing can be performed.

[0017]

As described above, according to the present invention, the workability in FIB processing is improved by providing a mark on the wiring as a guide when performing FIB processing for, for example, delay adjustment. improves. Also, in a semiconductor device having a multilayer wiring structure of two or more wiring layers, the FIB
By attaching marks when processing, the FIB
At the time of processing, the pattern shape of the first layer wiring is difficult to see through the interlayer insulating film, and the position shifted from the work location is cut, and for example, the first layer wiring and the second layer wiring are cut off. It is possible to prevent a problem such as a short circuit between the layer wirings.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a pattern configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view illustrating a pattern configuration of a semiconductor device according to another embodiment of the present invention.

FIG. 3 is a plan view illustrating a pattern configuration of a conventional semiconductor device.

FIG. 4 is a circuit diagram for explaining delay adjustment.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57) [Claims] A multilayer wiring structure, comprising a lower wiring and an upper wiring.
For delay adjustment etc. on wiring patterns where lines intersect
In a semiconductor device having a work place for performing FIB processing
Te, other lines the line width of the working position for performing FIB processing in the upper layer wirings
A mark formed narrower than the width and a mark near the work location
Cut the notch on the side of the lower layer wiring
A semiconductor device, comprising: 2. A semiconductor device having a multilayer wiring structure, comprising: a lower wiring layer and an upper wiring layer.
For delay adjustment etc. on wiring patterns where lines intersect
Method of processing a semiconductor device having a work place for performing FIB processing
In the method, the line width of the work place in the upper wiring where FIB processing is performed is set to another line width.
A mark formed narrower than the width and a mark near the work location
Cut the notch on the side of the lower wiring to surround
Then, use the notch and mark as a guide to
A method for processing a semiconductor device, comprising processing.