JP3278766B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an LDD (Lightly Doped Dr.).
The present invention relates to a CMOS semiconductor device having an n-channel transistor having an ain) structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the miniaturization of MOS (Metal-Oxide-Semiconductor) transistors, deterioration of transistor characteristics due to a short channel effect has become evident. Transistors having an LDD structure have been widely used as a preventive measure. C
As one of the methods of configuring a MOS semiconductor device, there is a method of using an n + type polycrystalline silicon as a gate electrode, an n-channel transistor as a surface channel type LDD structure, and a p-channel transistor as a buried channel type single drain structure. . The most basic technique for forming the source / drain of such a CMOS semiconductor device is to cover a p-channel region with a photoresist in a first lithography step, form an n- layer only in an n-channel region, and form a gate. Sidewall spacers are formed on the electrode side walls, the p-channel region is covered with a photoresist in a second lithography step, an n + layer is formed only in the n-channel region, and the n-channel region is covered with a photoresist in a third lithography step. This is a method of forming a p + layer in a channel region.

However, this method requires three lithography steps to form the source / drain, which undesirably increases the manufacturing cost. Therefore,
As a method of forming the source / drain by two lithography steps, there is a method of forming an n- layer in both an n-channel region and a p-channel region without using a lithography technique.

The prior art will be described with reference to the drawings. 6 to 10 are sectional views of a conventional semiconductor device in the order of steps.
An n-well (52) is formed in a p-channel device formation region of a p-type silicon substrate (51), and a field oxide film (53) is formed.
The active region and the non-active region were separated by the above, and the structure of FIG. 6 was obtained. Next, a gate oxide film (54) and a gate electrode (55) are formed in the active region, and a field oxide film (53) is formed.
7 is obtained by ion-implanting phosphorus into the gate electrode (55) in a self-aligned manner, thereby forming an n − layer (56) having a higher impurity concentration than the n well layer (52). Then, the side wall (6) is formed on the side wall of the gate electrode (55).
1) is formed, the area other than the p-channel element formation region is covered with a first photoresist (62), and using this as a mask, boron difluoride is ion-implanted to form ap + layer (58), and FIG. Get the structure. Subsequently, after removing the first photoresist, the p-channel element formation region is covered with a second photoresist (64), and arsenic is ion-implanted to form an n + layer (57), and the structure of FIG. 9 is formed. obtain. Further, an interlayer insulating film (64) is formed, a contact hole is opened at a desired location, and a wiring electrode (66) is formed.
0 structure is obtained.

FIGS. 4 and 5 of JP-A-59-210660 show that after forming an n− layer in both a p-channel region and an n-channel region, a p + layer is formed without forming a sidewall. A method of forming is described.

[0006]

What is problematic in the above manufacturing process is that the p-channel transistor formed in the n-well (52) is located between the channel region immediately below the gate electrode and the p + layer (58). That is, the n− layer (56) remains and an offset occurs between the p + layer (58) and the gate electrode (55). In the portion where the n− layer (56) remains, the threshold value of the transistor is locally high,
Also, since the inversion layer is always cut at the offset part,
The drain current value decreases. Further, even if the remaining width of the n- layer (56) is slightly changed due to fluctuations in manufacturing conditions or the like, the transistor characteristics are greatly changed, and the stable operation of the CMOS semiconductor device is impaired.

[0007] These phenomena are particularly remarkable with the progress of miniaturization of transistors. In order to advance miniaturization without increasing the manufacturing cost, the n-layer (56) is required.
The position of the junction between the p + layer and the p + layer (58) has been required to be controlled more and more precisely. Incidentally, Japanese Patent Application Laid-Open No. 59-21
In the method of forming a p + layer without forming a sidewall disclosed in Japanese Patent No. 0660, the lateral expansion of the p + layer largely enters the lower part of the gate electrode, and a short channel effect is remarkably exhibited. Can not.

As described above, the object of the present invention is to provide an n-channel L
In a CMOS semiconductor device having a DD transistor and a p-channel transistor, in order to eliminate a characteristic variation factor of the p-channel transistor, an n- layer between a channel region immediately below a gate electrode of a p-channel transistor formed in an n-well and a p + layer is removed. The purpose of the present invention is to prevent the remaining layer and to prevent the offset between the p + layer and the gate electrode.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device according to the present invention, which comprises an n- layer formed in source / drain regions of both an n-channel transistor and a p-channel transistor; Side walls formed on both side walls of the gate electrode and p + formed so as to cover the n− layer of the source / drain region of the p-channel transistor, respectively.
And a layer.

[0010] By adopting the above structure of the present invention,
The n- layer of the n-channel transistor can also be formed in the p-channel region without using a lithography process,
To stabilize the characteristics of a p-channel transistor in a channel transistor by removing the n- layer remaining between the channel region immediately below the gate electrode and the p + layer and the p-channel transistor due to the offset between the p + layer and the gate electrode. Can be.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the semiconductor manufacturing method according to the present invention, an impurity constituting an n- layer is self-aligned with a gate electrode and ion-implanted into the entire surface, and a first side wall is formed on a side wall of the gate electrode. Forming a p + transistor, ion-implanting a p + layer forming impurity into the p-channel transistor formation region by self-alignment with the first sidewall, and forming a p-channel transistor forming region on the side wall of the first sidewall. 2) and a step of ion-implanting an impurity constituting the n + layer into the n-channel transistor formation region by self-alignment with the sidewall after the addition of the second sidewall.

According to the present embodiment, the step of self-aligning the impurity constituting the n − layer with the gate electrode and ion-implanting the entire surface thereof allows the source / drain regions of both the n-channel transistor and the p-channel transistor in the above structure to be formed. An n-layer can be formed simultaneously without using a lithography process.

The step of forming a first sidewall on the side wall of the gate electrode and the step of adding a second sidewall to the side wall of the first side wall are divided into two steps. Side walls are formed on the side walls of the gate electrodes of both the channel transistor and the p-channel transistor.

The p + layer of the p-channel transistor in the above structure is formed by ion-implanting the impurity constituting the p + layer into the p-channel transistor formation region by self-alignment with the first sidewall. This impurity implantation step is performed after the formation of the first side wall and before the addition of the second side wall, by being self-aligned with the narrow first side wall. The p + layer can be diffused laterally and the p + layer can cover the n− layer. Thus, it is possible to prevent the n- layer from remaining between the channel region immediately below the gate electrode of the p-channel transistor and the p + layer, and prevent the offset between the p + layer and the gate electrode.

Further, the step of ion-implanting the impurity constituting the n + layer by self-alignment with the side wall of the n-channel transistor formation region after the addition of the second side wall is performed. Form a layer. Since this impurity implantation step is performed by self-alignment with the wide (first + second) sidewall after the addition of the second sidewall, the lateral extension of the n + layer exceeds that of the n− layer. Never.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to FIGS. 1 to 5 which are longitudinal sectional views in the order of steps.

The method of manufacturing a semiconductor device according to the present embodiment is performed by using n-
A step of self-aligning an impurity constituting the layer with the gate electrode and ion-implanting the entire surface, a step of forming a first sidewall on a side wall of the gate electrode, and a step of forming a p-channel transistor formation region on the first sidewall. A step of ion-implanting an impurity constituting the p + layer by self-alignment, a step of additionally forming a second sidewall on the side wall of the first sidewall, and a step of forming the second sidewall in an n-channel transistor formation region. Ion-implanting impurities constituting the n + layer by self-alignment with the sidewalls.

First, an n-well (2) is formed in a p-channel device formation region of a p-type silicon substrate (1), and a field oxide film (3) is formed to partition an active region and an inactive region. The structure was obtained.

Next, a film thickness of 1 is formed on the active region by a thermal oxidation method.
A thermal oxide film of 0 nm is formed, and LPCVD (Low Pressure
Chemical Vapor Deposition) 200nm
Depositing polysilicon with low resistance by adding phosphorus
The polysilicon was processed into a desired shape by a photolithography process to form a gate electrode (5). Therefore, phosphorus is implanted by ion implantation at a beam angle of 0 degree and an energy of 30 k.
Under the conditions of eV and a dose amount of 1 × 10 13 cm −2,
The self-aligned gate electrode (5) and field oxide film (3) were injected over the entire surface of the substrate to obtain the structure shown in FIG.

An oxide film is deposited to a thickness of 80 nm by LPCVD,
The entire surface is etched back by RIE (Reactive Ion Etching) to leave a first sidewall (21) on the side wall of the gate electrode (5), and the n-channel element formation region is covered with a first photoresist (22). Boron fluoride at a beam angle of 0 degree, energy of 30 keV, and dose of 1 × 1015
Injection was performed under the condition of cm-2 to obtain the structure shown in FIG.

After stripping the first photoresist (22), an oxide film is deposited to a thickness of 40 nm by LPCVD, and the p-channel region is covered with a second photoresist (24) to form an RI.
Etch back by E, add a second side wall (23) to the side wall of the side wall (21) of the side wall of the gate electrode (5) in the n-channel region, and arsenic ions with a beam angle of 0 degree, energy of 30 keV, dose Quantity 1 × 1015
Injection was performed under the condition of cm-2 to obtain the structure shown in FIG.

The second photoresist (24) was peeled off, and an interlayer insulating film (11), a contact hole, and a wiring electrode (12) were sequentially formed by a known technique to obtain a structure shown in FIG.

In this case, the concentration distribution of the n− layer (6) and the offset amount (sidewall thickness) between the n− layer (6) and the n + layer (7) are determined so that the n-channel transistor has desired characteristics. However, it is desirable that the sidewall thickness of the p-channel transistor be set so that the p + layer (8) just covers the n− layer (6).

Although the present invention has been described based on the preferred embodiment, the semiconductor device of the present invention and the method for manufacturing the same are not limited to the configuration of the above-described embodiment. Various modifications and changes from the configuration of the example are also included in the scope of the present invention.

[0025]

As described above, according to the present invention,
In a CMOS semiconductor device having an n-channel LDD transistor and a p-channel transistor, an n- layer having a higher impurity concentration than an n-well layer is formed in source / drain regions of both the n-channel transistor and the p-channel transistor. Of the gate electrode side wall of the n channel transistor is made thinner than the side wall of the gate electrode side wall of the n channel transistor, and the n − layer of the source / drain region of the p channel transistor is covered with the p + layer. Since the n- layer can be formed also in the p-channel region without using a lithography step, the number of manufacturing steps can be reduced, and in the p-channel transistor formed in the n-well, the n-layer between the channel region immediately below the gate electrode and the p + layer
The-layer can be prevented from remaining, and the offset between the p + layer and the gate electrode can be prevented. As a result, there is an effect that the characteristics of the p-channel transistor are stabilized.

[Brief description of the drawings]

FIG. 1 is a sectional view in the order of steps in an embodiment of the present invention.

FIG. 2 is a sectional view in the order of steps in an embodiment of the present invention.

FIG. 3 is a sectional view in the order of steps in an embodiment of the present invention.

FIG. 4 is a sectional view in the order of steps in an embodiment of the present invention.

FIG. 5 is a sectional view in the order of steps in an embodiment of the present invention.

FIG. 6 is a sectional view of a conventional technique in the order of steps.

FIG. 7 is a sectional view of a conventional technique in the order of steps.

FIG. 8 is a sectional view of a conventional technique in the order of steps.

FIG. 9 is a sectional view of a conventional technique in the order of steps.

FIG. 10 is a sectional view of a conventional technique in the order of steps.

[Explanation of symbols]

 1, 51: p-type silicon substrate 2, 52: n well 3, 53: field oxide film 4, 54: gate oxide film 5, 55: gate electrode 6, 56: n-layer 7, 57: n + layer 8, 58 .. P + layer 11, 65 interlayer insulating film 12, 66 wiring electrode 21 first sidewall 22, 62 first photoresist 23 second sidewall 24, 64 second photoresist 61 sidewall

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-58430 (JP, A) JP-A-63-217655 (JP, A) JP-A-6-268165 (JP, A)

Claims (4)

(57) [Claims] 1. An n-channel LDD transistor and a p-channel LDD transistor
Manufacturing of CMOS semiconductor device having channel transistor
In production method, the steps of the remaining forming an impurity constituting the n- layer by self-alignment by ion implantation into the entire surface n- layer in the gate electrode, the first sidewall on a sidewall of the gate electrode Covering the n-channel element formation region with a first photoresist, ion-implanting a p + layer-forming impurity into the p-channel device formation region by self-alignment with the first sidewall, and covering the n- layer. Forming a p + layer, stripping the first photoresist, covering the p-channel element formation region with a second photoresist, and forming the gate on the n-channel element formation region. Adding a second sidewall to the sidewall of the first sidewall on the sidewall of the electrode; and self-aligning the sidewall after the addition of the second sidewall. Impurities constituting the n + layer Te wherein n
Forming a n + layer by ion implantation into a channel element formation region. 2. The step of forming the first sidewall includes depositing an oxide film by an LPCVD method and etching back the entire surface by RIE, and the step of adding the second sidewall is performed by an LPCVD method. 2. The method according to claim 1, wherein an oxide film is deposited by a method and etched back by RIE. 3. The thickness of an oxide film deposited in the step of forming the first sidewall and the step of adding the second sidewall are 80 nm and 40 nm, respectively.
3. The method of manufacturing a semiconductor device according to claim 2, wherein 4. An impurity constituting the n− layer, the p +
2. The method according to claim 1, wherein the impurities forming the layer and the impurities forming the n + layer are phosphorus, boron difluoride, and arsenic, respectively.