JP3279907B2 - Digital receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus for a digital communication apparatus, and more particularly to a receiving apparatus for a digital communication apparatus. The present invention relates to a digital receiver capable of selectively receiving synchronous detection and delay detection. Furthermore, the present invention relates to a receiver for a digital communication device, and more particularly to a diversity receiver at a baseband signal stage.

[0002]

2. Description of the Related Art Conventionally, in digital communication, FSK, BP
Various modulation schemes such as SK and QPSK are used depending on the system, and demodulation circuits corresponding to the respective modulation schemes are applied. Furthermore, various detection methods such as synchronous detection, IF band delay detection, and baseband delay detection are appropriately adopted as demodulation methods for the QPSK-specific modulation method, for example. Which detection method to use for the communication device is determined by the modulation method, the propagation environment such as the presence or absence of fading, the size of the communication device, the cost of the device, etc.
Sometimes a diversity effect is expected, for example, as disclosed in
As disclosed in Japanese Patent No. 336081, a method of applying a plurality of detection methods to one communication device and selectively using the same is also proposed.

On the other hand, as an element that can characterize mobile communication, there is a poor propagation environment. That is, in the receiving system, the received signal level fluctuates deeply and steeply due to fading, and therefore, the synchronous detection method, which originally has excellent performance in static characteristics, generates a burst-like error due to loss of PLL lock. Therefore, in communication in which fading is expected, an adaptive equalizer is used, or a delay detection method having theoretically inferior characteristics is used. Furthermore, diversity reception is widely used as one of the powerful means for overcoming a poor propagation environment. This is to prepare a plurality of receiving systems and select / combine a plurality of obtained signals. As the branches to be selected / combined, various parameters such as space, time, frequency, directivity, transmission path, and polarization are known.

[0004]

In the conventional method, if the detection method is different, the circuit configuration is not the same. Therefore, a plurality of detection circuits are formed by different independent circuits and components corresponding to the detection method. Must be configured. Further, in order to reduce the size and weight of the communication device, it is desirable that the circuit be formed as an IC as much as possible. It is desirable to mass-produce versatile ICs that do not depend on the method or detection method. However, according to the conventional technology, an IC having high versatility is realized even when detecting the same modulation signal as well as the modulation method, for example, since the specific circuits are completely different between, for example, delay detection and synchronous detection. In this case, the IC is not a general-purpose IC but a so-called ASIC, which impairs mass productivity and makes it impossible to produce ICs efficiently.

[0005] Diversity is a system in which a single system is provided with a plurality of sufficient receiving systems, and the system scale becomes very large. Also, the adaptive equalizer applied to synchronous detection has a large circuit scale, and is extremely difficult to realize in addition to an increase in circuit scale due to problems of algorithm convergence and operation time of signal processing. Also, the time during which the signal level drops sharply due to fading is a very short time during communication, and the use of delay detection, which is theoretically inferior to synchronous detection in preparation for that instant, is not sufficient for communication over the entire communication time. It is not a good idea considering quality.

[0006]

SUMMARY OF THE INVENTION The present invention solves these problems of the prior art and uses very simple and small circuitry to detect FM signals, synchronous and delay detection of BPSK and QPSK signals, and Baseband signal processing such as multi-mode detection such as AFC of BPSK signal is possible.
The purpose of the present invention is to realize a circuit configuration suitable for versatile IC integration. In a baseband signal processing device in a demodulation unit of a digital communication device, FSK, BPSK, QP
An arithmetic unit that performs an operation to obtain a detection output according to various detection methods such as various modulation methods such as SK, synchronous detection, IF band delay detection, and baseband delay detection, and whether to perform delay detection or synchronous detection. To specify the operation of the delay circuit, the operation of the delay circuit, or to specify the delay time at the time of the delay detection, or to select the arithmetic expression according to the modulation method and the detection method in the arithmetic unit,
Provided is a digital signal demodulation baseband signal processing device including a control unit for designating calculation contents such as calculation.

Further, the present invention provides a receiving unit for digital communication, comprising: an operation unit for performing an operation for obtaining a detection output according to a synchronous detection system or a delay detection system in various modulation systems; Specify the operation of the delay circuit according to the operation, non-operation, or the delay time at the time of delay detection, and / or select the arithmetic expression corresponding to the modulation method and the detection method in the arithmetic unit, and calculate the operation contents. The present invention provides a digital receiving apparatus including a control unit for performing designation and capable of selectively receiving synchronous detection and delay detection with a single circuit configuration.

Further, the present invention provides a receiving apparatus having a diversity effect by switching between synchronous detection and delay detection according to the propagation environment. Further, the present invention uses a receiving system capable of performing both synchronous detection and delayed detection by a control signal from a control unit, and prepares only one receiving system, usually uses synchronous detection, and delays when fading. A digital receiver having a diversity effect of switching to detection is provided on a very small system scale.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a configuration of an embodiment of the present invention. In FIG. 1, an input modulated signal in the IF band is converted into a baseband band by mixers 1 and 2 and low-pass filters LPF4 and LPF5. The I, Q, and baseband signals are sampled by A / D converters 6 and 7, and input to arithmetic unit 10 as a digital signal processing circuit together with data delayed by shift registers 8 and 9 as delay circuits. You. The arithmetic unit 10 is a DSP or CP
U and the like. Numeral 11 designates the operation or non-operation of the delay circuit according to the delay detection or the synchronous detection, or the designation of the delay time at the time of the delay detection, and the arithmetic unit 10 selects and calculates the arithmetic expression according to the modulation method and the detection method. It is a control unit which is a controller for designating the content of the operation such as the operation.

Here, the following equation is calculated.

[0011]

(Equation 1)

Here, ωh is a frequency error between the modulated signal and the local signal, φk is a phase, θk is a phase variation due to a transmission line or the like, and θ is a phase of the local signal. In the digital signal processing circuit, the input samples X1 and Y1 and the samples X2 and Y2 delayed by the time specified by the external control port are used to calculate one of the following equations according to the external command. Do some of the

[0013]

(Equation 2)

[0014]

(Equation 3)

[0015]

(Equation 4)

[0016]

(Equation 5)

[0017]

(Equation 6)

The operation in such a configuration will be described below. First, a case of synchronous detection of a QPSK signal according to a first embodiment of the present invention will be described with reference to the drawings. The VCO 12 is used as a local signal generator. The calculations of the five equations are performed under the control of the control unit 11. If the AFCs in all stages are working well, ωK does not occur. Also, the phase information is quadrupled and μK becomes 2nπ, which can be ignored. Therefore, Equation 6 becomes

[0019]

(Equation 7)

As a result, only the phase error is generated, and by controlling the VCO 12, a coherent carrier is reproduced. This method is widely known as a Costas loop as a synchronous detection method for a QPSK signal.

Next, a second embodiment of the present invention will be described with reference to FIG. In the figure, AFC is used as the input IF signal.
Assume a BPSK signal that is not performed. A control signal from the control unit 11 specifies an interval T, which is an integral multiple of the data symbol rate, as a delay time, and performs the following equation.

[0022]

(Equation 8)

Here, attention is paid to the fluctuation of the frequency level of the signal, and the fluctuation of the phase level is ignored. In the case of BPSK, sin (φk, k−T) is zero, and the second term on the right side of Expression 10 is zero. The effect of the data on the second term on the right-hand side is simply the reversal of the polarity and can be easily determined. Therefore,

[0024]

(Equation 9)

As a result, BPSK AFC can be realized.

Next, a third embodiment of the present invention will be described with reference to FIG. In the figure, the VCO 12 operates as a local signal generator under the control of the control unit 11. Assuming a QPSK signal as an input IF signal and designating a symbol interval T as a delay time by an external control signal, the following equation is calculated.

[0027]

(Equation 10)

Assuming that the AFC works well and that the phase fluctuation due to the external environment can be neglected at most within the symbol time,

[0029]

[Equation 11]

Then, information is immediately required. This is widely known as baseband differential detection, and although it is inferior to synchronous detection in static characteristics, it does not generate a burst-like error due to loss of loop lock due to fading or the like, and is therefore widely used particularly in mobile communication.

Next, a fourth embodiment of the present invention will be described with reference to FIG. In the figure, an FM (FSK) signal is assumed as an input signal input IF signal, and a minimum unit 1 sample time (immediate data) is designated as a delay time under the control of the control unit 11, and the following equation is calculated. .

[0032]

(Equation 12)

Since the signal is an FM signal, Δμk, k−1 is zero, and it is considered that the phase change can be ignored compared to the frequency change. At this time,

[0034]

(Equation 13)

Then, the FM signal is demodulated. This technique is widely known as cross-product detection.

In this embodiment, a circuit which can be used in common for many modes has been described. However, when the number of modes is small, the minimum circuit configuration necessary for the mode and the operation and control devices are sufficient. Of course.

FIG. 2 is a schematic diagram showing the configuration of still another embodiment of the present invention. In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals, and hereinafter, mainly different parts will be described in detail. First, in the present embodiment, the control unit 11
In addition to the operation described above, it also functions as a phase difference detector (lock detector) of the PLL, and both the synchronous detection and the delay detection will be described using the QPSK modulation method as an example.

In FIG. 2, a received signal converted into an IF band signal is converted into a base band signal by a local signal and mixers 1 and 2, a 90 ° shifter 3, and low-pass filters 4 and 5, and an A / D converter 6 7 becomes digital data. Each data is delayed by shift registers 8 and 9 by about one data symbol time. As a result, the following four types of signals are input to the digital signal processing device 10.

[0039]

(Equation 21)

Here, φk is the information phase, θk is the phase variation due to the transmission path or the like, and θ is the phase of the local signal. When performing synchronous detection, the following calculation is executed by an external control signal.

[0041]

(Equation 22)

In the case of the QPSK signal, when the signal is multiplied by four, the modulation component is canceled and only the other phase fluctuation information is obtained. Therefore, by using the VOC 12 as a local signal generator and controlling the VOC with this information, a coherent carrier is reproduced and synchronous detection can be realized.
This technique is widely known as the Costas Loop. When delay detection is performed using the same circuit configuration, the control unit 11
The following operation is executed by the control signal of (1).

[0043]

(Equation 23)

The phase of the local signal is canceled,
Assuming that the phase fluctuation due to the external environment for at most one symbol time is negligible, the calculation result of Expression 3 indicates the phase difference between the symbols, which means that the differential detection has been performed. This technique is well known as baseband differential detection. The present embodiment of the present invention uses only one device described above, and switches between synchronous detection operation and delay detection operation according to the propagation environment to use, so that optimal reception is always performed without using a plurality of branches. Next, we will discuss its operation.

In FIG. 2, when the propagation environment is good,
The control section 11 acting as a phase difference judging section judges that synchronous detection is possible, outputs, for example, a logical 1 and controls the digital signal processing apparatus 10 to perform the operation of the equation 22, and sets the switching section 15 to the digital signal. The synchronous detection is continued by causing the VOC 12 to perform a feedback operation by being connected to the output of the processing device 10.

When fading or the like occurs and the control unit 11 acting as a phase difference determination unit determines that synchronous detection is impossible,
The control unit 11 acting as a phase difference judging unit judges that synchronous detection is possible and outputs a logical 0 to control the digital signal processing unit 10 to switch to the operation of Expression 23, and at the same time, sets the switching unit 15 to generate a constant voltage. Switch to vessel 16 and VO
Let C12 be a fixed frequency transmitter.

[0047]

As described above, according to the configuration and method of the present invention, it is possible to provide very various functions by using exactly the same hardware configuration (IC).
By reducing the types of ICs to be manufactured and mass-producing a single IC, a communication device can be manufactured very efficiently. Furthermore, by merely providing one receiving circuit in the communication device, it is possible to select a QPSK detection method having different characteristics and perform FM demodulation, and a small, lightweight, inexpensive, and highly compatible communication device can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an embodiment of the present invention.

FIG. 2 is a schematic view showing another embodiment of the present invention.

[Explanation of symbols]

 1, 2 mixer 3 90 ° shifter 4, 5 low-pass filter 6, 7 A / D converter 8, 9 shift register / delay unit 10 digital signal processing circuit / arithmetic unit 11 controller / control unit 12 VCO / voltage control transmitter 13 D / A converter 14 Loop filter 15 Switch 16 Constant voltage generator

Claims (2)

(57) [Claims] 1. A receiving unit for digital communication, comprising: an operation unit for performing an operation for obtaining a detection output according to a synchronous detection method or a delay detection method in various modulation methods;
Activate or deactivate the delay circuit depending on whether synchronous detection or delay detection, or specify the delay time at the time of delay detection, or select the modulation method in the calculation unit, the calculation formula according to the detection method, A digital receiving device comprising: a control unit for designating calculation contents such as calculation, and capable of selectively receiving synchronous detection and delay detection with a single circuit configuration. 2. The receiver according to claim 1, wherein a diversity effect is provided by switching between synchronous detection and delay detection according to the propagation environment.