JP3282234B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a large capacity capacitive element.

[0002]

2. Description of the Related Art In recent years, the speed of processors such as microcomputers and digital signal processors (hereinafter abbreviated as DSP) has been increased.
Consumer electronic devices are becoming more sophisticated due to lower power consumption. Accordingly, unnecessary radiation, which is electromagnetic noise generated from electronic devices, has become a major problem. For this reason, measures for reducing unnecessary radiation have been taken on the electronic device side, and measures for reducing unnecessary radiation have been strongly required for microcomputers and DSPs.

[0003] A conventional semiconductor device taking measures against unnecessary radiation will be described below. FIG. 4 is a sectional view of a main part of a conventional semiconductor device. In FIG. 4, 41 is a P-type silicon substrate,
42 is an N-type well; 43 is an N-type region which is a P-ch transistor isolation region; 44 is a P-type region which is an N-ch transistor isolation region; 45 is a silicon oxide film which is a transistor isolation region; A gate electrode, 47 is a polysilicon film serving as an electrode of the capacitor, 48 is a gate oxide film, 49 is an interlayer insulating film, and 50 is a wiring. As shown in FIG. 4, in the conventional semiconductor device, the capacitive element has a polysilicon film 47 as an upper electrode, a silicon oxide film 45 as a capacitive insulating film, and an isolation region 43 as a lower electrode.
Although not shown, the capacitive element is composed of an upper electrode formed of the same material as the gate electrode 46, a capacitive insulating film formed of the same oxide film as the gate oxide film 48, and the silicon substrate 41 or 4.
It may be composed of two lower electrodes. By inserting such a capacitive element between a power supply line and a ground line, a method of reducing a transient component of a current flowing through the power supply line and reducing unnecessary radiation has been adopted.

[0004]

However, in the above conventional structure, the value of the capacitance element that can be built in the chip is at most several tens of pF because the dielectric constant of the silicon oxide film as the capacitance insulating film is as small as 3.9. Yes, unnecessary radiation is 10
%.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device capable of reducing unnecessary radiation by 50% or more without increasing the area of the conventional structure.

[0006]

In order to achieve the above object, a semiconductor device according to the first aspect of the present invention is provided on a semiconductor substrate on which an integrated circuit is formed.
On a part thereof, a capacitive element including a lower electrode, a dielectric thin film having a high dielectric constant and an upper electrode is formed via a first insulating film, and a second insulating film is formed on the capacitive element. A semiconductor device in which a wiring that is formed and is electrically connected to an upper electrode and a lower electrode is formed in an opening provided in the second insulating film, wherein the capacitive element built in a chip is connected to the wiring via the wiring. Characterized by being inserted between a power supply line and a ground line, one of the upper electrode and the lower electrode being connected to a power supply line and the other to a ground line, and absorbing unnecessary radiation. It is. With this configuration, the capacitance element that absorbs the unnecessary radiation can be several n without increasing the area.
More than F capacitors can be built into the chip.

[0007]

With this configuration, a capacitance of several nF or more can be inserted between the power supply line and the ground line, so that the transient component of the current flowing through the power supply line can be substantially reduced without increasing the area as compared with the conventional structure. It can be reduced to zero and unnecessary radiation is reduced to 5
It can be reduced by 0% or more.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1 is a P-type silicon substrate, 2 is an N-type well, 3 is an isolated N-type region, 4 is an isolated P-type region, 5 is a silicon oxide film for element isolation, 6 is a gate electrode, 7 Is an interlayer insulating film, 8 is a lower electrode, 9 is a dielectric thin film having a high dielectric as a capacitive insulating film (hereinafter referred to as a high dielectric thin film), 10 is an upper electrode, 11 is a protective film of a capacitive element, and 12 is a barrier. Metal, 13a is lower electrode 8
The wiring 13b is a wiring that conducts to the upper electrode 10. The upper electrode 10 and the lower electrode 8 are connected to a power supply line and a ground line by wirings 13b and 13a, respectively.

In the semiconductor device configured as described above,
Utilizing the large dielectric constant of the high dielectric thin film 9, a capacitance element having a capacitance of several tens to several hundreds times the capacitance formed by a normal silicon oxide film can be incorporated. Since the transient component of the power supply current can be reduced to almost zero by being inserted between the power supply and the ground line, unnecessary radiation can be reduced to zero.

Further, in the structure of this embodiment, since the capacitive element formed of the high dielectric thin film 9 is disposed on the interlayer insulating film 7, the maximum temperature in the subsequent steps is equal to the wiring 13
The maximum temperature is 500 ° C. for forming a and 13b, and a capacitor with stable characteristics can be realized.

Next, a second embodiment of the present invention will be described. FIG. 2 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention. In FIG. 2, the same parts as those in the first embodiment shown in FIG. This embodiment is different from the first embodiment in that the shapes of the high dielectric thin film 20 and the upper electrode 21 are different. That is, in this embodiment, the high dielectric thin film 20 and the upper electrode 21 are formed so as to cover the end of the lower electrode 8. Therefore, the wiring 13 which makes contact with the upper electrode 21
b can be arranged so as not to pass over the lower electrode 8, so that the wiring 13 b
And the lower electrode 8 can be prevented from conducting.

Next, a third embodiment of the present invention will be described. FIG. 3 is a sectional view of a main part of a semiconductor device according to a third embodiment of the present invention. In FIG. 3, the same parts as those in the first embodiment shown in FIG.
This embodiment is different from the first embodiment or the second embodiment in that the shape of the high dielectric thin film 20, the shape of the upper electrode 21, and the formation of the protective film 11 for extracting the wiring 13b from the upper electrode 21 are described. The different positions of the openings are different. That is, in this embodiment, the high dielectric thin film 30 and the upper electrode 31 are formed so as to cover the lower electrode 8, and the opening of the protective film 11 for making contact between the upper electrode 31 and the wiring 13b is formed. 8 is provided at a position that does not overlap. Therefore, in addition to the effect of the second embodiment, there is a new effect that the contact portion between the upper electrode 31 and the wiring 13b is away from the portion where the capacitor is formed, and does not affect the capacitance characteristic. Have.

In these embodiments, even if the upper electrode is connected to the power line and the lower electrode is connected to the ground line, the upper electrode is connected to the ground line.
It goes without saying that the same effect can be obtained even if the lower electrode is connected to the power supply line.

Further, in the present embodiment, an example in which a capacitor is formed in a structure in which an N-type well 2 is formed in a P-type silicon substrate 1 has been described. However, the present invention is not limited to this, and other circuit configurations or A similar effect can be obtained by applying the present invention to a semiconductor device having a structure.

[0015]

As described above, according to the present invention, since the capacitive element using the high dielectric thin film as the capacitive insulating film is formed between the power supply line and the ground line, unnecessary electromagnetic noise caused by power supply noise is eliminated. An excellent semiconductor device capable of reducing radiation can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a sectional view of a main part of a semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a sectional view of a main part of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 P-type silicon substrate (semiconductor substrate) 7 interlayer insulating film (first insulating film) 8 lower electrode 9 high dielectric thin film (dielectric thin film) 11 protective film (second insulating film) 10 upper electrode 13 a, 13 b wiring

Continuing from the front page (72) Inventor Toru Nasu 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Denshi Kogyo Co., Ltd. ) Inventor Yasuhiro Shimada 1006 Kadoma, Kazuma, Osaka Prefecture Inside Matsushita Electronics Corporation (56) References JP-A-3-212969 (JP, A) JP-A-2-186669 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/822 H01L 27/04

Claims (3)

(57) [Claims] 1. An element of a semiconductor substrate on which an integrated circuit is formed.
Forming a capacitive element including a lower electrode, a dielectric thin film having a high dielectric constant, and an upper electrode via a first insulating film on a part of the area excluding the element forming area; A semiconductor device in which a second insulating film is formed on the semiconductor device, and wirings that are electrically connected to the upper electrode and the lower electrode are formed in openings provided in the second insulating film, respectively. The capacitive element is inserted between a power supply line and a ground line via the wiring, and one of the upper electrode and the lower electrode is connected to a power supply line and the other is connected to a ground line; A semiconductor device, characterized by absorbing light. 2. The semiconductor device according to claim 1, wherein at least a part of the dielectric thin film having a high dielectric constant is formed over a part of the lower electrode. 3. An opening in the second insulating film for leading out the upper electrode, wherein at least a part of the dielectric thin film having a high dielectric constant and the upper electrode are both formed at least partially beyond a part of the lower electrode. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed at a position that does not overlap with the lower electrode.