JP3285772B2 - Power failure / restoration detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power failure / restoration detection circuit applied to a toll collection device such as a toll road.

[0002]

2. Description of the Related Art Toll collection devices used on toll roads or parking lots are often operated continuously for a long time.
In such a toll collection device, a power failure / restoration detection circuit for detecting a power failure and a power recovery in preparation for a power failure during operation is provided to store data or the like by a power failure, and to operate by a subsequent power recovery. There is something that was made to resume.

FIG. 5 shows an example of a conventional power failure / recovery detection circuit, and FIG. 6 shows an example of an output signal waveform of each component of the power failure / recovery detection circuit. In this case, the power supply voltage from the AC power supply (commercial power supply) is first reduced to a predetermined voltage by the transformer 51, and the output signal S51 of the transformer 51 is full-wave rectified by the rectifier circuit 52.

[0004] The output signal S52 of the rectifier circuit 52 is monitored by a voltage detection circuit 53.
When the peak value of the voltage of the output signal S52 is equal to or higher than the reference value A, the output signal S53 is set to H level, and when the voltage is smaller than the reference value A, the output signal S53 is set to L level and output.

[0005] An output signal S53 of the voltage detection circuit 53 is input to an output signal generation circuit 54. Output signal generation circuit 5
4, the output signal S53 is as in AC power feed state at H level, the made to correspond to the rising edge of the output signal S53 output during the time the power failure signal P_FAIL the H level T ₁ and. Further, as the output signal generating circuit 54 follows the output signal S53 within the time T ₁ is when not in H level, the AC power is a power failure,
Until the output signal S53 becomes H level, the power interruption signal P_FA
IL is set to L level and output.

[0006] Thereafter, when the output signal S53 becomes H level, as the output signal generation circuit 54 AC power is power returns, the power interruption signal P_FAIL waits for the time T ₂ of the order of the voltage stabilization of the AC power source Output at H level.

Further, the output signal generation circuit 54 when outputting a power failure signal P_FAIL at H level in a powered state, and outputs a clear signal S_CLR delays by time T ₃ from the power failure signal P_FAIL at H level. Further, the power interruption signal P_FAIL
Is output at the H level, the power interruption signal P_FAI
L than by time T ₄ is delayed to output a clear signal S_CLR at H level.

The time T ₁ is set so as to be equal to or more than a time corresponding to 0.5 cycles of alternating current by the AC power supply, and to be equal to or less than the time T ₅ during which the DC power supply _VCC keeps the reference value B after the AC power failure. And the time T ₃ is the power interruption signal P_FAIL
Is set to a time equal to or longer than the time required for the microprocessor or the like controlled by the CPU to save the register and the like. In addition,
The voltage detection circuit 53 and the output signal generation circuit 54 always operate by the battery power supply VBT.

[0009]

As described above, the conventional power failure / recovery detection circuit detects a power failure and a power recovery based on whether or not the peak value of the voltage is equal to or higher than a reference value. Therefore, if the waveform of the power supply voltage is distorted, even if the effective value of the voltage is equal to or higher than the reference value and the toll collection device or the like can sufficiently operate, the power failure is erroneously detected if the peak value is smaller than the reference value. There was a problem. SUMMARY OF THE INVENTION It is an object of the present invention to provide a power failure / recovery detection circuit that is not affected by distortion of a power supply voltage waveform.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention obtains an average value of a power supply voltage from a commercial power supply, and detects a power failure when the average value falls below a predetermined reference value. Thereafter, when the average value becomes larger than the reference value, the power recovery is detected. More specifically, the power outage / restoration according to the present invention
A rectification circuit for rectifying an output of a commercial power supply,
Averaging circuit for determining an average value of the output signal of the rectifier circuit
A predetermined level when the average value is equal to or higher than a predetermined reference value.
A voltage detection circuit for intermittently generating an output signal;
After the detection circuit generates the output signal of the predetermined level,
The power supply voltage of the voltage detection circuit is
Within the first time holding the predetermined value, the next predetermined level
When no output signal is generated, the commercial power
When the power interruption signal is set to the first level and output
Output a clear signal for a first delay time,
After that, when the output signal of the predetermined level is generated,
Assuming that the commercial power has recovered, the voltage of the commercial power has stabilized
After a second time period required for the
And outputs the clear signal after a second delay time.
And an output signal generation circuit for outputting a signal.
I do. According to the present invention, even when the waveform of the power supply voltage is distorted, the average value of the obtained power supply voltage does not greatly change, so that it is possible to accurately detect the power failure and the power recovery.

[0011]

FIG. 1 is a block diagram showing a configuration of a power failure / restoration detection circuit according to an embodiment of the present invention.
The power failure / recovery detection circuit includes a transformer 1, a rectifier circuit 2, an averaging circuit 3, a voltage detection circuit 4, and an output signal generation circuit 5.
It is constituted by.

A power supply voltage is supplied to the transformer 1 from an AC power supply (commercial power supply). The voltage detection circuit 4 is connected to a DC power supply _Vcc . The DC power supply V _cc during after a power failure of the AC power and time T ₅ (e.g. 35ms) is to hold a reference value B. The averaging circuit 3, the voltage detection circuit 4, and the output signal generation circuit 5 always operate by the battery power supply VBT.

The operation of the power failure / restoration detection circuit will be described below with reference to FIG. FIG. 2 shows the output signal waveforms of the transformer 1, the rectifier circuit 2, the averaging circuit 3, the voltage detection circuit 4, the output signal generation circuit 5, and the DC power supply _Vcc in order from the top, and the horizontal axis represents time t. The vertical axis represents the magnitude of the output signal.

The power supply voltage from the AC power supply is stepped down to a predetermined voltage (for example, 100 V) by a transformer 1, and an output signal S 1 of the transformer 1 is input to a rectifier circuit 2. The rectifier circuit 2 performs full-wave rectification on the output signal S1 of the transformer 1 and outputs it. The output signal S2 of the rectifier circuit 2 is input to the averaging circuit 3 and the voltage detection circuit 4.

The averaging circuit 3 outputs the output signal S of the rectifier circuit 2.
2 and outputs the average value to the voltage detection circuit 4. The voltage detection circuit 4 monitors the output signal S3 of the averaging circuit 3, and its voltage value, that is, the average value of the output signal S2, is set to a predetermined reference value A (for example, when the output signal S1 is 100V).
Is the output signal S4 to the H level, is smaller than the reference value and outputs an output signal S4 to the output signal generating circuit 5 in the L level when 85 V) than when the.

The output signal generating circuit 5, as when the output signal S 4 of the voltage detection circuit 4 is at the H level AC power is in the powered state, corresponding to the rising edge of the output signal S 4, the power failure signal P_FAIL is set to H level and output for a time T ₁ (for example, 20 ms). Further, the output signal generation circuit 5 outputs the next output signal S 4 within this time T _1.
When but not to H level, the power failure signal to the output signal S 4 as AC power is power failure becomes H level P_
FAIL is set to L level and output.

[0017] Thereafter, when the output signal S 4 becomes H level, as the output signal generating circuit 5 is AC power is power returns, the time for voltage stabilization of the AC power source T ₂ (e.g.,
After waiting for 2s), the power interruption signal P_FAIL is set to the H level and output.

When the output signal generation circuit 5 outputs the power interruption signal P_FAIL at the H level in the power supply state, the output signal generation circuit 5 outputs a time T ₃ (for example,
1 ms), and outputs the clear signal S_CLR at the H level. Further, when a power interruption signal P_FAIL in association with the power recovery AC power output in the H level as described above, and outputs a clear signal S_CLR at H level is delayed from the power interruption signal P_FAIL by time T _4.

Here, the time T ₁ is equal to or longer than a time corresponding to 0.5 cycles of alternating current by an AC power source, for example, when the frequency is 5
When 0Hz is not less than 10 ms, it is set so that the DC power supply V _CC after a power failure of the AC power is less than the time T ₅ for holding the reference value B. The time T ₃ is set to be longer than the time the microprocessor (not shown) or the like is required to retract the receiving power interruption signal P_FAIL register or the like.

Next, a specific example of the averaging circuit 3 will be described. FIG. 3 is a diagram illustrating an example of a circuit configuration of the averaging circuit 3. One end of a resistor 7a is connected to the input terminal 9, and the other end of the resistor 7a is connected to one end of a resistor 7b and a capacitor 8a.
Is connected to one end of the The other end of the resistor 7b
The non-inverting input terminal of the operational amplifier 6 and one end of the capacitor 8b are connected, and the other end of the capacitor 8b is grounded. On the other hand, the other end of the capacitor 8a is connected to an inverting input terminal and an output terminal of the operational amplifier 6, and
Are connected to the output terminal 10. In this case, the resistance values of the resistors 7a and 7b and the capacitors 8a and 8
b by appropriately determining the capacitance value of the output signal S2.
Is output.
When averaging is not sufficiently performed by a single-stage averaging circuit using one operational amplifier, a plurality of operational amplifiers may constitute a multiple-stage averaging circuit.

The averaging circuit 3 is constructed by connecting a plurality of capacitors (13a to 13d in FIG. 4) of a predetermined capacity in parallel between the input terminal 11 and the output terminal 12, as shown in FIG. You may. In this case, the circuit configuration is simplified, but many capacitors are required to make the output signal S3 a complete direct current, and it is difficult to reduce the size of the circuit. Therefore, when miniaturization is desired, it is desirable to use a circuit using an operational amplifier as shown in FIG.

As described above, in the power failure / recovery detection circuit of this embodiment, after the power supply voltage from the AC power supply is transformed and rectified,
An average value is obtained, and power failure and power recovery are detected based on the average value. Therefore, even when the waveform of the power supply voltage is distorted, the average value does not greatly change, so that it is possible to accurately detect the power failure and the power recovery.

[0023]

As described above, according to the present invention, by detecting the average value of the power supply voltage, it is possible to accurately detect the power failure and the power recovery without being affected by the distortion of the power supply voltage waveform. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a power failure / recovery detection circuit according to an embodiment of the present invention.

FIG. 2 is a view showing a waveform of an output signal according to the embodiment;

FIG. 3 is a diagram showing an example of an averaging circuit in FIG. 1;

FIG. 4 is a diagram showing another example of the averaging circuit in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a conventional power failure / recovery detection circuit.

FIG. 6 is a diagram showing a waveform of an output signal of a conventional power failure / recovery detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Transformer 2 ... Rectifier circuit 3 ... Averaging circuit 4 ... Voltage detection circuit 5 ... Output signal generation circuit 6 ... Op amp 7a, 7b ... Resistance 8a, 8b ... Capacitor 9 ... Input terminal 10 ... Output terminal 11 ... Input terminal 12 ... output terminals 13a to 13d ... capacitors 51 ... transformers 52 ... rectifier circuits 53 ... voltage detection circuits 54 ... output signal generation circuits

──────────────────────────────────────────────────続 き Continued from the front page (56) References JP-A-59-87371 (JP, A) JP-A-51-82934 (JP, U) JP-A-2-107226 (JP, U) JP-A-4- 14445 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 19/165 G05F 1/10 301

Claims (1)

(57) [Claims] A rectifier circuit for rectifying an output of a commercial power supply, and an averaging circuit for calculating an average value of an output signal of the rectifier circuit.
And output of a predetermined level when the average value is equal to or more than a predetermined reference value.
A voltage detection circuit that generates a signal intermittently, and the voltage detection circuit generates the output signal of the predetermined level.
After the power failure of the commercial power supply,
Within a first time during which the source voltage holds a predetermined value,
When no commercial output signal is generated,
Sets the power interruption signal to the first level and outputs it as a power failure
Output a clear signal for the first delay time
Then, when the output signal of the predetermined level is generated
Indicates that the commercial power has been restored.
After the second time required for voltage stabilization, the power interruption signal is
2 levels and output, and after a second delay time
Power outage / power recovery detection circuit, characterized by chromatic and an output signal generating circuit that outputs a clear signal.