JP3296304B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a gettering step of removing heavy metals existing in a region where an element is formed, and more particularly to a method of manufacturing a semiconductor device with improved gettering efficiency. About the method.

[0002]

2. Description of the Related Art With the miniaturization and high integration of semiconductor devices, it is one of the important factors in the manufacturing process of semiconductor devices to eliminate trace metal heavy elements from element active regions, that is, to perform gettering. Has become one.

Therefore, usually, an extrinsic gettering (EG) method in which a strain field or a chemical action is applied to the substrate from the outside, or an intrinsic gettering (IG) method utilizing oxygen precipitation generated in the substrate. Two approaches have been adopted.

[0004] The former, SiO ₂ and Al ₂ O on the back surface of the substrate
Abrasive fluid, such as ₃ and high-pressure injection mechanical damage BD (B
(Polycrystalline-silicon Back Sea) by depositing a polycrystalline silicon film on the backside of the substrate
ling) method. The latter is 1100 to 1200
Formation of defect-free layer by outward diffusion of oxygen at high temperature
Oxygen dissolved in the silicon substrate is deposited inside the substrate through three steps of forming precipitation nuclei at a low temperature of 00 to 800 ° C. and increasing the deposition size at a temperature of about 1000 ° C. This is a method in which a complex with a crystal defect such as dislocation generated due to the above is used as a gettering site.

[0005] However, these gettering methods cannot cope with a low temperature in a manufacturing process accompanying high integration and miniaturization of a semiconductor element and a large-diameter substrate. For example, in the EG method in which a gettering site is present on the back surface of a silicon substrate, since the distance between the element active region and the gettering site is large, heavy metal contaminants cannot sufficiently diffuse to the gettering site in a low-temperature process, and the It remains in the area. On the other hand, in the IG method, oxygen precipitates are reduced due to a lower temperature in the manufacturing process, and gettering ability is reduced.

Therefore, a method of manufacturing a semiconductor device in which a gettering site is provided in a region immediately below an isolation oxide film has been disclosed (Japanese Patent Application Laid-Open No. 8-8262). 5A to 5G are cross-sectional views showing a conventional method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. 8-8262 in the order of steps.

In the conventional manufacturing method, first, FIG.
As shown in FIG. 1A, a silicon oxide film 22 and a silicon nitride film 23 are sequentially formed on a P-type silicon substrate 21.

Next, as shown in FIG. 5B, the silicon nitride film 23 is patterned so as to remain only in the element formation region. Thereafter, a silicon oxide film 24 is formed on the entire surface.

Next, as shown in FIG. 5C, a side wall film 25 is formed on the side surface of the silicon nitride film 23 by etching back the silicon oxide film 24.
Thereafter, a crystal defect region 26 having a crystal defect serving as a gettering site is formed near the surface of the silicon substrate 21 by ion implantation of carbon.

Next, as shown in FIG. 5D, the entire surface is washed with dilute hydrofluoric acid to remove the sidewall film 25. At this time, a part of the silicon oxide film 22 is also removed.

Next, as shown in FIG. 5E, the silicon substrate 21 is selectively thermally oxidized using the silicon nitride film 23 as an oxidation resistant film. Thus, a field oxide film 27 made of a silicon oxide film is formed.

Next, as shown in FIG. 5F, the silicon nitride film 23 and the silicon oxide film 22 are sequentially removed. Thereafter, a gate oxide film 28 is formed on the silicon substrate 21 in the element formation region surrounded by the field oxide film 27. Further, a gate electrode 29 is selectively formed on the gate oxide film 28, and ion implantation is performed using the gate electrode 29 as a mask, thereby forming source / drain diffusion layers 30a and 30b on the surface of the silicon substrate 21.

Next, as shown in FIG. 5G, an interlayer insulating film 31 is formed on the entire surface, and the source insulating film 31 is formed on the interlayer insulating film 11.
Contact holes 32a and 32b reaching the drain diffusion layers 30a and 30b, respectively, are opened. Thereafter, the aluminum wiring layer 33 is provided in each of the contact holes 32a and 32b.
a and 33b are buried.

According to such a conventional method of manufacturing a semiconductor device, since a crystal defect region having a gettering site is formed immediately below the field oxide film 27 (element isolation oxide film), the heavy metal near the element active region is formed. Is eliminated.

[0015]

However, according to the conventional manufacturing method disclosed in Japanese Patent Application Laid-Open No. 8-8262,
There is a problem in that the defect is recovered by the heat treatment step after the introduction of the crystal defect, and the heavy metal is re-emitted due to a decrease in the gettering ability. Further, even when the recovery does not occur, the device characteristics such as the device isolation characteristics are deteriorated due to the residual defect existing immediately below the field, and the junction leak occurs.

Furthermore, in the detailed description of the invention of Japanese Patent Application Laid-Open No. 8-8262, since the ion implantation is performed using the sidewall film 25 as a mask, the diffusion layer
0a and 30b are not affected, but the heat treatment for defect introduction performed immediately after ion implantation is performed in a heat treatment atmosphere containing oxygen.
Implantation defects are likely to grow greatly into the diffusion layers 30a and 30b, adversely affecting device characteristics.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of preventing the re-emission of heavy metal and the growth of implantation defects in an element active region and improving the efficiency of gettering. It is intended to provide a manufacturing method.

[0018]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: ion-implanting a plurality of elements in a semiconductor substrate on which a plurality of elements are formed; Forming a crystal defect in the element isolation region by heat-treating the semiconductor substrate in a non-oxidizing atmosphere at a first heat treatment temperature; and subjecting the semiconductor substrate to a second heat treatment temperature lower than the first heat treatment temperature. Forming a device isolation oxide film in the device isolation region by heat treatment, wherein a projection range at the time of the ion implantation is Rp, and a thickness of the device isolation oxide film is t. Rp <0.45 × t holds.

In the present invention, since the projection range at the time of ion implantation for forming a crystal defect is appropriately defined, the crystal defect is taken into the element isolation oxide film and the residual is prevented. . Further, since the heat treatment temperature is appropriately specified, re-emission of the gettered heavy metal is prevented. Further, since the heat treatment atmosphere for forming the crystal defects is a non-oxidizing atmosphere, deterioration of the bonding characteristics is prevented.

Before the step of performing ion implantation,
The method may include forming a silicon nitride film pattern having an opening in the element isolation region on the semiconductor substrate.

The step of forming the silicon nitride film pattern includes forming a silicon nitride film on the semiconductor substrate and forming a photoresist pattern having an opening in the element isolation region on the silicon film. And a step of patterning the silicon nitride film using the photoresist pattern as a mask or a step of patterning the silicon nitride film and the semiconductor substrate using the photoresist pattern as a mask.

Further, the ions to be implanted in the step of performing the ion implantation may be at least one ion selected from the group consisting of Si, N, O, F, Ar, B and P.

Further, the non-oxidizing atmosphere may be a nitrogen atmosphere.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. The first embodiment is an example applied to an element isolation method using a LOCOS oxide film. 1A to 1D and 2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, a pad oxide film (first oxide film) 2 having a thickness of, for example, about 20 nm is formed on a p-type silicon substrate 1 by a thermal oxidation method.

Next, as shown in FIG. 1B, a silicon nitride film 3 having a thickness of, for example, about 150 nm is formed on the pad oxide film 2 by a CVD method.

Next, as shown in FIG. 1C, a photoresist is applied on the silicon nitride film 3 and a photoresist having an opening in an element isolation region for isolating elements to be formed. The pattern 4 is formed by a known lithography technique.

Next, as shown in FIG. 1D, using the photoresist pattern 4 as a mask, the silicon nitride film 3 is selectively removed by a known dry etching method.
A silicon nitride film pattern 5 for COS oxidation is formed.

Next, as shown in FIG. 2A, the photoresist pattern 4 is removed. Thereafter, using the silicon nitride film pattern 5 as a mask, silicon ions 7 are implanted into the element isolation oxide film formation region 6 in the element isolation region. At this time, the energy of the ion implantation is set so that the projection range of the implantation species is at least smaller than the consumption of the substrate due to the oxidation of the element isolation oxide film to be formed later. Specifically, assuming that the projection range of the implanted species is Rp and the film thickness of the element isolation oxide film is t, the energy conditions are set so that the following equation 1 is satisfied.

[0030]

## EQU1 ## Rp <0.45 × t

For example, the silicon ions 7 are implanted under the conditions that the implantation energy is 40 keV and the dose is 1 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 2B, the silicon substrate 1 is heated in a non-oxidizing atmosphere, for example, a nitrogen atmosphere by using a lamp annealing (RTA) apparatus at a heat treatment temperature of 1050.degree. The first heat treatment is performed under the condition that the time is about 30 seconds to form the implantation defect layer 8 having the ion implantation defect, thereby gettering the heavy metal element existing in the device active region there (the implantation defect layer 8). I do.

Next, as shown in FIG. 2C, at a temperature lower than the heat treatment temperature (1050 ° C.) of the first heat treatment, for example, 980 ° C., for example, LOCOS oxidation (second time) for about 2 hours.
Heat treatment), the film thickness becomes, for example, 400
A device isolation oxide film 9 of about nm is formed in the device isolation oxide film forming region 6 where the implantation defect layer 8 is formed and in the vicinity thereof.
In the present embodiment, the projection range Rp of the silicon ions is about 50 nm, and the energy condition shown in Expression 1 is sufficiently satisfied.

Next, as shown in FIG. 2D, the silicon nitride film pattern 5 is removed. Thereafter, a device (not shown) such as a transistor is formed in a region (device active region) where the element isolation oxide film 9 is not provided.

In this embodiment, an implantation defect layer 8 having an ion implantation defect is formed in advance in the element isolation oxide film forming region 6 of the element isolation region, and after the heavy metal is gettered in the implantation defect layer 8, the defect is removed. Since the implantation defect layer 8 containing the metal and the heavy metal is incorporated in the element isolation oxide film 9, a clean device active region can be formed. Therefore, it is possible to prevent the element characteristics from deteriorating due to heavy metals. Further, since the oxidation temperature for forming the element isolation oxide film 9 is set lower than the heat treatment temperature for forming defects (gettering sites), the gettering ability does not decrease due to defect recovery. Therefore, re-emission of the heavy metal element gettered by the defect into the substrate is prevented.

Further, since the energy condition of the ion implantation is properly defined, no implantation defect remains immediately below the element isolation oxide film 9, so that the element isolation characteristics do not deteriorate due to the defect. If the above formula 1 is not satisfied, the implantation defect may remain immediately below the element isolation oxide film and the element isolation characteristics may be degraded. In addition, since heat treatment in a non-oxidizing atmosphere is performed as heat treatment for forming ion implantation defects, introduction of interstitial silicon into the substrate caused by oxidation of the silicon surface is suppressed. As a result, the growth of the implantation defect in the diffusion layer region is prevented, and the junction characteristics do not deteriorate due to the implantation defect.

As described above, according to the present embodiment, the re-emission of heavy metal due to the recovery of the implantation defect and the deterioration of the device characteristics due to the growth of the implantation defect in the device active region and the like are prevented.
Heavy metals existing in the element active region are effectively gettered by implantation defects formed by ion implantation.

Next, a second embodiment of the present invention will be described. The second embodiment is an example applied to a recessed (Recessed) LOCOS method which is known to be effective in flattening an element. 3 (a) to 3 (d) and FIG.
6A to 6D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

In the present embodiment, the first step is performed up to an intermediate step.
Is performed in the same manner as in the embodiment of

That is, first, as shown in FIG.
A pad oxide film (first oxide film) 12 having a thickness of, for example, about 20 nm is formed on the mold silicon substrate 11 by a thermal oxidation method.

Next, as shown in FIG. 3B, a silicon nitride film 13 having a thickness of, for example, about 150 nm is formed on the pad oxide film 12 by a CVD method.

Next, as shown in FIG. 3C, a photoresist is applied on the silicon nitride film 13 and a photoresist having an opening in an element isolation region for isolating elements to be formed. The pattern 14 is formed by a known lithography technique. The steps up to here are the same as in the first embodiment.

Next, as shown in FIG. 3D, the silicon nitride film 1 is
3. The pad oxide film 12 and the silicon substrate 11 are selectively removed by a known dry etching method. Thereby, the silicon nitride film pattern 1 for LOCOS oxidation
5 are formed. The etching depth from the surface of the silicon substrate 11 is, for example, about 50 nm. In the first embodiment, as a step corresponding to this step, as shown in FIG. 1D, only the silicon nitride film 3 is selectively removed by a dry etching method.

Next, as shown in FIG. 4A, using the photoresist pattern 14 and the silicon nitride film pattern 15 as a mask, silicon ions 17 are deposited in the element isolation oxide film formation region 16 under the energy conditions satisfying the expression (1). inject. For example, if the implantation energy is 40 keV (Rp: about 50
nm) and a dose of 1 × 10 ¹⁵ cm ⁻² is implanted with silicon ions 17.

Next, as shown in FIG. 4B, the photoresist pattern 14 is removed. Thereafter, the silicon substrate 11 is placed in a non-oxidizing atmosphere, for example, a nitrogen atmosphere using a lamp annealing (RTA) apparatus, for example, at a heat treatment temperature of 1050 ° C. and a heat treatment time of about 30 seconds for the first time.
Is performed to form an implantation defect layer 18 having an ion implantation defect, and the heavy metal element existing in the device active region is gettered there (the implantation defect layer 18).

Next, as shown in FIG. 4C, LOCOS oxidation (first time) at a temperature lower than the heat treatment temperature of the first heat treatment (1050 ° C.), for example, 980 ° C. for about 2 hours, for example.
Heat treatment), the film thickness becomes, for example, 400
A device isolation oxide film 19 of about nm is formed in the device isolation oxide film forming region 16 where the implantation defect layer 18 is formed and in the vicinity thereof.

Next, as shown in FIG. 4D, the silicon nitride film pattern 15 is removed. Thereafter, a device (not shown) such as a transistor is formed in a region (device active region) where the element isolation oxide film 9 is not provided.

In the recessed LOCOS method, since the silicon substrate 11 is also removed by etching, the normal LOCOS method is used.
Compared with the COS method, there is a concern that the introduction of damage due to dry etching and the adverse effect on element characteristics due to the mixing of heavy metals. However, according to the present embodiment, as described in the first embodiment, effective gettering can be performed. Therefore, even if the recessed LOCOS method is applied, the yield can be reduced by preventing the characteristic deterioration of the element. An improvement is realized.

In the first and second embodiments,
Although silicon ions are used as ion implantation species for forming the gettering defect layer, similar effects can be obtained by using other ion species (N, O, F, Ar, B or P, etc.). Can be

[0050]

As described in detail above, according to the present invention,
Since the projection range and the heat treatment temperature at the time of ion implantation for forming a crystal defect are appropriately specified, it is possible to prevent the crystal defect from remaining and prevent the heavy metal from being re-emitted. Further, since the heat treatment atmosphere for forming the crystal defects is a non-oxidizing atmosphere, it is possible to prevent the deterioration of the bonding characteristics. Therefore, gettering efficiency can be improved.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIGS. 2 (a) to 2 (d) are views showing a first embodiment of the present invention, and are cross-sections showing the steps subsequent to the steps shown in FIGS. 1 (a) to 1 (d) in the order of steps; FIG.

FIGS. 3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIGS. 4 (a) to 4 (d) are views showing a second embodiment of the present invention, and are cross-sections showing the steps subsequent to the steps shown in FIGS. 3 (a) to 3 (d) in the order of steps; FIG.

FIGS. 5A to 5G are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. H8-8262 in the order of steps.

[Explanation of symbols]

 1, 11, 21; silicon substrates 2, 12; pad oxide films 3, 13, 23; silicon nitride films 4, 14; photoresist patterns 5, 15; silicon nitride film patterns 6, 16; Silicon ion 8, 18; implantation defect layer 9, 19; element isolation oxide film 22, 24; silicon oxide film 25; sidewall film 26; crystal defect region 27; field oxide film 28; gate oxide film 29; Electrodes 30a, 30b; source / drain diffusion layers 31; interlayer insulating films 32a, 32b; contact holes 33a, 33b; aluminum wiring layers

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-10-214844 (JP, A) JP-A-5-267661 (JP, A) JP-A-7-161704 (JP, A) JP-A-10- 50694 (JP, A) JP-A-11-297703 (JP, A) JP-A-11-150181 (JP, A) JP-A-10-173039 (JP, A) JP-A-7-273121 (JP, A) JP-A-6-275710 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/322 H01L 21/316 H01L 21/76

Claims (6)

(57) [Claims] A step of implanting ions into an element isolation region of a semiconductor substrate on which a plurality of elements are to be formed, separating the plurality of elements from each other; and subjecting the semiconductor substrate to a non-oxidizing atmosphere at a first heat treatment temperature. Forming a crystal defect in the element isolation region by heat treatment; and forming an element isolation oxide film in the element isolation region by heat treating the semiconductor substrate at a second heat treatment temperature lower than the first heat treatment temperature. Wherein, when the projection range at the time of the ion implantation is Rp and the thickness of the element isolation oxide film is t, a mathematical formula Rp <0.45 × t is satisfied. Device manufacturing method. 2. The method according to claim 1, further comprising a step of forming a silicon nitride film pattern having an opening in the element isolation region on the semiconductor substrate before the step of performing the ion implantation. A method for manufacturing a semiconductor device. 3. The step of forming the silicon nitride film pattern includes forming a silicon nitride film on the semiconductor substrate, and forming a photoresist pattern having an opening in the element isolation region on the silicon film. 3. The method according to claim 2, further comprising a step of: patterning the silicon nitride film using the photoresist pattern as a mask. 4. The step of forming the silicon nitride film pattern includes forming a silicon nitride film on the semiconductor substrate and forming a photoresist pattern having an opening in the element isolation region on the silicon film. And a step of patterning the silicon nitride film and the semiconductor substrate using the photoresist pattern as a mask,
3. The method for manufacturing a semiconductor device according to claim 2, comprising: 5. The method according to claim 1, wherein the ions implanted in the step of performing ion implantation are at least one ion selected from the group consisting of Si, N, O, F, Ar, B, and P. A method for manufacturing a semiconductor device according to claim 1. 6. The method according to claim 1, wherein the non-oxidizing atmosphere is a nitrogen atmosphere.