JP3301915B2 - Package for housing semiconductor element and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element such as an LSI (large-scale integrated circuit element) is usually made of an electrically insulating material such as an aluminum oxide sintered body, and has a substantially upper central portion. An insulating base having a plurality of metallized wiring layers made of a refractory metal powder of tungsten, molybdenum, manganese or the like drawn out from the periphery of the recess to the outer peripheral edge thereof for mounting and housing the semiconductor element on the semiconductor element; An insulating substrate comprising: a plurality of external lead terminals attached to the metallized wiring layer via a brazing material such as silver brazing to electrically connect each electrode to an external electric circuit; and a cover. The semiconductor element is bonded and fixed to the concave portion via an adhesive made of glass, resin, brazing material or the like, and each electrode of the semiconductor element is bonded to a predetermined metallized wiring layer with a bonding wire. By connecting the lid to the upper surface of the insulating base via a sealing material such as glass or resin, and hermetically housing the semiconductor element inside a container consisting of the insulating base and the lid. As a semiconductor device.

The semiconductor element housing package has a poor bonding property between the metallized wiring layer provided on the insulating base and the bonding wires, and therefore, the region of the metallized wiring layer where the electrodes of the semiconductor element are connected via the bonding wires. Is provided with a protective metal layer made of nickel, gold, or the like by a plating method, and the bonding of the bonding wire to the metallized wiring layer is improved by the protective metal layer.

In the package for housing a semiconductor element, the insulating base is generally formed of a sintered body of aluminum oxide, and an organic solvent or a solvent is added to a ceramic raw material powder such as aluminum oxide, silicon oxide, magnesium oxide or calcium oxide. A slurry is formed by adding and mixing, and the slurry is formed into a sheet-like ceramic forming body by employing a doctor blade method or a calendar roll method. Then, the average particle size of tungsten, molybdenum, etc. is 2 μm to 3 μm.
An organic solvent is added to the metal powder of m, and a metal paste obtained by adding and mixing a solvent is applied on the surface of the ceramic forming body in a predetermined pattern by a screen printing method to form a wiring pattern, and thereafter, the wiring pattern is formed. Are formed by laminating a plurality of ceramic forming bodies on which are formed, baking them at a temperature of about 1600 ° C. in a reducing atmosphere, forming wiring patterns as metallized wiring layers, and forming the ceramic forming bodies as insulating bases. I have.

[0005]

However, in this conventional package for housing a semiconductor element, the metallized wiring layer is formed of a metal powder such as tungsten or molybdenum having an average particle diameter of 2 to 3 μm, and the particle diameter is large. The contact area between the metal powders was small, and the sheet resistance of the metallized wiring layer was as large as about 15 mΩ / sq. Therefore, when a semiconductor element that performs high-speed driving in recent years is housed in the conventional semiconductor element housing package and an electric signal is input / output to / from the semiconductor element via the metallized wiring layer, the electric signal is transferred to the large sheet resistance of the metallized wiring layer As a result, the semiconductor device has a drawback that an electrical signal cannot be accurately taken in and out of the semiconductor device and the semiconductor device malfunctions.

Therefore, in order to solve the above-mentioned drawbacks, the average particle size of the metal powder of the metal paste forming the metallized wiring layer is reduced to about 1 μm to 2 μm, thereby increasing the contact area between the metal powders and increasing the metallized wiring. It is conceivable to lower the sheet resistance of the layer.

However, the average particle size is 1 μm to 2 μm
Although the metallized wiring layer formed by using the metal powder having a low degree can reduce the sheet resistance, the surface becomes smooth, and at the same time, the region of the metallized wiring layer to which the electrode of the semiconductor element is connected via the bonding wire. The surface roughness of the protective metal layer deposited on the substrate is extremely smooth with a center line average roughness (Ra) of Ra <0.25 μm. Therefore, the bonding wire is bonded to the protective metal layer by sliding the bonding wire on the protective metal layer attached to the surface of the metallized wiring layer and causing the bonding wire to mechanically deform plastically. When connecting each electrode of the device, the bonding wire slides on the protective metal layer and the bonding between the bonding wire and the protective metal layer is weakened. As a result, the electrical connection between each electrode of the semiconductor device and the external electric circuit is made. This leads to a drawback that the reliability of the device becomes low.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to connect each electrode of a semiconductor element firmly to a predetermined metallized wiring layer via a bonding wire, and An object of the present invention is to provide a package for housing a semiconductor element, which is capable of reliably and accurately transferring an electric signal to and from a semiconductor element via a wiring layer.

According to the present invention, an electrode of a semiconductor element is connected via a bonding wire and has an average particle size of 1 μm.
A semiconductor element housing comprising: an insulating base having a plurality of metallized wiring layers made of metal powder having a thickness of 2 to 2 μm; and a lid, wherein the semiconductor element is hermetically accommodated in a container formed by the insulating base and the lid. Wherein the sheet resistance of the metallized wiring layer is 12 mΩ / sq or less, and the surface of a region of the metallized wiring layer where at least the electrode of the semiconductor element is connected via a bonding wire is formed with unevenness of 1 to 2 μm. A protective metal layer is adhered to the surface and the surface roughness of the protective metal layer is adjusted to a center line average roughness (R) specified in JIS-B-0601.
It is characterized in that 0.3 μm ≦ Ra ≦ 0.5 μm in a).

The present invention also provides a step of preparing a ceramic forming body, wherein the surface of the ceramic forming body has an average particle size of 1%.
forming a wiring pattern by applying a metal paste made of a metal powder having a thickness of 2 μm to 2 μm, and pressing a film having a surface roughness of 1 to 2 μm on a surface of a region of the wiring pattern to which a bonding wire is to be connected. Forming an unevenness of 1 to 2 μm on the surface, firing the ceramic forming body on which the wiring pattern is formed in a reducing atmosphere, and forming an insulating base having a metallized wiring layer having a sheet resistance of 12 mΩ / sq or less. And a step of plating the surface of at least the region of the metallized wiring layer to which the electrode of the semiconductor element is connected via a bonding wire by a plating method so that the surface has a center line average roughness (Ra) specified in JIS-B-0601. ) And a step of applying a protective metal layer of 0.3 μm ≦ Ra ≦ 0.5 μm.

According to the semiconductor device housing package of the present invention, the sheet resistance of the metallized wiring layer is 12 mΩ / sq.
When an electric signal is input / output to / from the semiconductor element through the metallized wiring layer, the electric signal is not greatly attenuated by the metallized wiring layer. The element can always be operated normally.

According to the semiconductor device housing package of the present invention, a protective metal layer is applied to the surface of at least the region of the metallized wiring layer to which the electrodes of the semiconductor device are connected via bonding wires, and the protective metal layer is provided. Since the surface roughness of the layer was set to an appropriate value of 0.3 μm ≦ Ra ≦ 0.5 μm with a center line average roughness (Ra) specified in JIS-B-0601, the bonding wire was used to protect the metallized wiring layer surface with a protective metal. Can be firmly bonded to the layers,
Thus, each electrode of the semiconductor element can be reliably electrically connected to an external electric circuit via the bonding wire and the metallized wiring layer.

[0013]

Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base made of an electrically insulating material, and 2 is a lid. The insulating base 1 and the lid 2 constitute a container for housing the semiconductor element 3.

The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body, etc. A stepped recess 1a for accommodating the semiconductor element 3 is provided at a substantially central portion of the recess 1a.
The semiconductor element 3 is bonded and fixed to the bottom surface via an adhesive such as glass, resin, brazing material or the like.

A plurality of metallized wiring layers 4 are formed on the insulating substrate 1 from the periphery of the concave portion 1a to the outer peripheral edge, and a semiconductor element is provided in a region of the metallized wiring layer 4 which is located around the concave portion 1a. 3 are electrically connected to each other through bonding wires 5, and the insulating substrate 1
An external lead terminal 6 is soldered and attached to a portion led out to the outer peripheral edge of the wire.

The metallized wiring layer 4 provided on the insulating substrate 1 is made of a high melting point metal powder such as tungsten, molybdenum, manganese, etc. The metallized wiring layer 4 is connected to an external lead terminal 6 connected to an external electric circuit by a semiconductor element 3. To electrically connect the respective electrodes.

The metallized wiring layer 4 has a sheet resistance of 12 μm by setting the average particle diameter of the metal powder such as tungsten, molybdenum or the like to 1 μm to 2 μm.
mΩ / SQ or less, so that when an electric signal is put into or taken out of the semiconductor element 3 via the metallized wiring layer 4, the electric signal is not greatly attenuated by the metallized wiring layer 4, and as a result, An electric signal is accurately transferred into and out of the semiconductor element 3 so that the semiconductor element 3 can always operate normally.

Further, the metallized wiring layer 4 is provided with a protective metal layer 7 made of nickel, gold or the like in a region where each electrode of the semiconductor element 3 is connected via a bonding wire 5. 7 is JIS surface roughness
-B-0601 with a center line average roughness (Ra) of 0.
It has an appropriate roughness of 3 μm ≦ Ra ≦ 0.5 μm.

The protective metal layer 7 has a surface roughness JI.
Since the center line average roughness (Ra) specified in SB-0601 has an appropriate roughness of 0.3 μm ≦ Ra ≦ 0.5 μm, the bonding wire 5 is slid on the protective metal layer 7 for bonding. The bonding wire 5 and the protective metal layer 7 are mechanically deformed by mechanically deforming the wire 5.
When the metallized wiring layer 4 and the electrodes of the semiconductor element 3 are connected to each other, the bonding wire 5 is favorably plastically deformed on the protective metal layer 7 to join the bonding wire 5 and the protective metal layer 7. As a result, the reliability of the electrical connection between each electrode of the semiconductor element 3 and the external electric circuit can be made extremely high.

The protective metal layer 7 has a surface roughness of JI
When the center line average roughness (Ra) specified in SB-0601 is 0.3 μm> Ra, the surface of the protective metal layer 7 becomes smooth and the bonding wire 5 cannot be firmly joined, and Ra> When the thickness is 0.5 μm, the bonding area between the bonding wire 5 and the surface of the protective metal layer 7 decreases, and the bonding strength decreases. Therefore, the surface roughness of the protective metal layer 7 applied to the region where the electrodes of the semiconductor element 3 of the metallized wiring layer 4 are connected via the bonding wires 5 has a surface roughness specified in JIS-B-0601. Center line average roughness (Ra) 0.3 μm ≦ Ra ≦
It is specified in the range of 0.5 μm.

External lead terminals 6 are brazed to the metallized wiring layer 4 via a brazing material such as silver brazing. The external lead terminals 6 brazed to the metallized wiring layer 4 are made of iron-nickel. It is made of a metal material such as a cobalt alloy or an iron-nickel alloy, and functions to electrically connect each electrode of the semiconductor element 3 to an external electric circuit.

The external lead terminal 6 is formed in a predetermined plate shape by employing a conventionally known metal rolling method, stamping method, or the like, for example, of an ingot (lumps) of an iron-nickel-cobalt alloy or the like.

Further, the external lead terminal 6 is provided with a metal having good conductivity and excellent corrosion resistance made of nickel, gold or the like on its surface by plating to a thickness of 1 μm to 20 μm. The oxidation corrosion of the terminal 6 can be effectively prevented, and the electrical connection between the external lead terminal 6 and the external electric circuit can be made good. Therefore, it is preferable that a metal having excellent corrosion resistance, such as nickel and gold, and a good wettability with a brazing material is applied to the surface of the external lead terminal 6 to a thickness of 1 μm to 20 μm by plating.

In such a package for housing a semiconductor element, the semiconductor element 3 is bonded and fixed to the concave portion 1a of the insulating base 1 with an adhesive such as glass, resin, brazing material or the like, and each electrode of the semiconductor element 3 is connected to the metallized wiring layer 4. Are electrically connected to each other via a bonding wire 5, and thereafter, the lid 2 is joined to the upper surface of the insulating base 1 with a sealing material such as glass, resin, brazing material, or the like. The semiconductor device as a final product is obtained by hermetically housing the semiconductor element 3 inside the container.

Next, a method of manufacturing the above-described insulating substrate of the semiconductor device housing package will be described with reference to FIG. First, as shown in FIG. 2A, three sheet-shaped ceramic forming bodies 10a, 10b, and 10c are prepared.

The three ceramic forming bodies 10a, 1
0b and 10c are, for example, aluminum oxide, silicon oxide,
An organic solvent and a solvent are added to and mixed with a ceramic raw material powder such as magnesium oxide or calcium oxide to form a slurry, and the slurry is formed into a sheet by employing a doctor blade method or a calendar roll method. .

The ceramic forming bodies 10b and 1
0c is a hole 11 for forming a cavity for accommodating a semiconductor element by employing a conventionally known punching method.
a and 11b are formed.

Next, as shown in FIG. 2B, a wiring pattern 12 to be a metallized wiring layer is formed on the upper surface of the ceramic forming body 10b from the periphery of the hole 11a to the outer peripheral edge.

The wiring pattern 12 has an average particle size of 1 μm.
An organic solvent and a solvent obtained by adding and mixing an organic solvent and a solvent to a high melting point metal powder such as tungsten or molybdenum having a thickness of 2 μm to 2 μm are applied to a ceramic forming body 10 by screen printing.
It is formed by printing and applying a predetermined pattern on the upper surface of b.

In the wiring pattern 12 formed on the upper surface of the ceramic forming body 10b, a region where each electrode of the semiconductor element is connected via a bonding wire;
That is, the surface roughness is 1 in the area located around the hole 11a.
A film 13 such as a metallic paper having a thickness of 2 μm to 2 μm is pressed at 50 kg / cm ² , and irregularities of about 1 μm to 2 μm are formed on the surface of the wiring pattern 12 located around the hole 11 a. The irregularities formed on the surface of the wiring pattern 12 indicate the surface roughness of a protective metal layer described later according to JIS-B-060.
0.3 μm ≦ Ra at centerline average roughness (Ra) specified in 1.
≦ 0.5 μm.

Next, as shown in FIG. 2C, the three ceramic forming bodies 10a, 10b, and 10c are vertically stacked to form a green laminate 14, and the green laminate 14 is placed in a reducing atmosphere. By firing at about 1600 ° C. and sintering and integrating the ceramic raw material powder of each of the ceramic forming bodies 10a, 10b, and 10c and the metal powder in the wiring pattern 12, a plurality of pieces as shown in FIG. Metallized wiring layer 4
Is obtained. In this case, since the metallized wiring layer 4 has a fine average particle diameter of 1 μm to 2 μm of the refractory metal powder such as tungsten or molybdenum in the wiring pattern 12, the contact area between the metal powders is widened and the sheet resistance is 12 mΩ /. It is lower than SQ.

Finally, as shown in FIG. 2 (d), if a protective metal layer 7 is applied to a region of the metallized wiring layer 4 where each electrode of the semiconductor element is connected via a bonding wire, the semiconductor The insulating base 1 used for the element storage package is completed. Nickel and gold are used for the protective metal layer 7. Nickel has a thickness of 2 μm to 8 μm and gold has a thickness of 1 μm by employing a conventionally known plating method.
Deposited to a thickness of ２．５2.5 μm. Since the surface of the metallized wiring layer 4 is appropriately roughened, the protective metal layer 7 has a center line average roughness (R) specified in JIS-B-0601.
a) has a surface roughness of 0.3 μm ≦ Ra ≦ 0.5 μm, whereby the bonding wire slides on the protective metal layer 7 and mechanically plastically deforms the bonding wire to form a bonding wire. When joining the protective metal layer 7 and the protective metal layer 7, the joining becomes extremely strong.

The present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention.

[0034]

According to the semiconductor device storage package of the present invention, the sheet resistance of the metallized wiring layer is 12 mΩ / s.
When an electric signal is put into and taken out of the semiconductor element through the metallized wiring layer because of the low q, the electric signal is not greatly attenuated in the metallized wiring layer, and as a result, the electric signal is put in and out of the semiconductor element accurately and the semiconductor The element can always be operated normally.

According to the package for accommodating a semiconductor element of the present invention, a protective metal layer is applied to a surface of at least a region of the metallized wiring layer to which the electrode of the semiconductor element is connected via a bonding wire. Since the surface roughness of the layer was set to an appropriate value of 0.3 μm ≦ Ra ≦ 0.5 μm with a center line average roughness (Ra) specified in JIS-B-0601, the bonding wire was used to protect the metallized wiring layer surface with a protective metal. Can be firmly bonded to the layers,
Thus, each electrode of the semiconductor element can be reliably electrically connected to an external electric circuit via the bonding wire and the metallized wiring layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a package for housing a semiconductor element according to the present invention.

2 (a), (b), (c) and (d) are cross-sectional views for each step for explaining a method of manufacturing the insulating base of the package shown in FIG.

Claims (2)

(57) [Claims] An electrode of a semiconductor element is connected via a bonding wire and has an average particle size of 1 μm to 2 μm.
A semiconductor element housing package comprising: an insulating base having a plurality of metallized wiring layers made of a metal powder ; and a lid, wherein the semiconductor element is hermetically housed in a container formed by the insulating base and the lid. Wherein the sheet resistance of the metallized wiring layer is 12 mΩ / sq or less, and the surface of at least the region of the metallized wiring layer to which the electrode of the semiconductor element is connected via the bonding wire is 1 to
The protective metal layer on the surface as well as to have the irregularities of 2μm by depositing a surface roughness of the protective metal layer JIS
-B-0601 with a center line average roughness (Ra) of 0.
A semiconductor element housing package, wherein 3 μm ≦ Ra ≦ 0.5 μm. 2. A step of preparing a ceramic forming body, wherein the surface of the ceramic forming body has an average particle size of 1 μm to 2 μm.
Forming a wiring pattern by applying a metal paste made of a metal powder of
Press a 2 μm film to form a 1-2 μm depression on the surface.
Forming a projection , firing the ceramic forming body on which the wiring pattern is formed in a reducing atmosphere to form an insulating substrate having a metallized wiring layer having a sheet resistance of 12 mΩ / sq or less; At least the surface of the region where the electrode of the semiconductor element is connected via a bonding wire has a surface roughness of JIS by plating.
-B-0601 with a center line average roughness (Ra) of 0.
The method of manufacturing a semiconductor device housing package which comprises a step of depositing a protective metal layer of 3μm ≦ Ra ≦ 0.5μm.